EELE 262 Logic Circuits Lab Lab #8 Sequential Logic in VHDL (Ripple Counter)

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1 Objective EELE 262 Logic Circuits Lab Lab #8 Sequential Logic in VHDL (Ripple Counter) The objective of this lab is to introduce sequential logic in VHDL. This lab will cover the design of a simple binary counter circuit called a ripple counter which is made with D-flip-flops. The counter will drive your existing 7- segment display decoder in order to create an incrementing hex counter on your breadboard. Outcomes After completing this lab you should be able to: Design a 4-bit ripple counter on an FPGA using D-flip-flops. Use the counter output to drive the inputs to a 7-segment display decoder. Pre-Lab A) A ripple counter is made from D-flip-flops that are connected in a toggle flop configuration (e.g., the Qn output is wired back to the D input). This configuration provides an output on the Q of the D-flip-flop that has a frequency exactly ½ of the incoming clock. An inverted version of this divided down signal (e.g., Qn) can then be used to clock the next stage of the counter to provide a signal that is ¼ of the original clock. These divided down signals provide a simple binary counter and can be scaled to whatever size is desired by adding more D-flip-flops. The following logic diagram shows the architecture of a ripple counter. In your lab notebook, draw the logic diagram for a 4-bit ripple counter. Lab Work & Demonstration You are going to design and implement the circuit in the following figure. You will be provided a Dflipflip.vhd file that models a D-flip-flop in VHDL. You will design a 4-bit ripple counter on the DE0-nano FPGA which will be clocked by the KEY1 push button on the FPGA board. You will use KEY0 as the reset to your counter. The 4-bit output of the ripple counter will be used to drive the inputs to your 7-segment decoder from last week. You will also drive the 4-bit counter to the LEDs on the DE0-nano board.

2 1) Creating an FPGA Design for today s lab. A) Connect the DE0-nano board located in the lab to your breadboard as in the above pictures. B) Log into the lab computers using your MSU domain account. C) Create a folder for today s lab. If you wish, you can work on the desktop for now and then copy over to your own drive when finished. Name the folder something descriptive such as Lab08_ripple. D) Start the Altera Quartus II design tool - Start All Programs Altera 12.1 Build 177 (Web Edition) Quartus II 12.1 Quartus II 12.1 The following window will appear (it might take a minute). 2

3 E) Create a new project using the Project Wizard File New Project Wizard The following Window will appear (i): Click Next In the next window (ii), browse to the folder you created and choose Select Folder. Enter top as the name of the project and top-level design entity. i ii Click Next The next screen (iii) allows you to add existing VHDL files. We will create a new file later. Click Next In the next window (iv), choose the FPGA device. The DE0-nano board contains a Cyclone IV E, EP4CE22F17C6. Choose the Cyclone IV E as the Device Family and Select the EP4CE22F17C6 as the device. iii iv 3

4 Click Next on the next screen (v) and Finish on the last screen (vi). v vi F) Create a new VHDL design file called top.vhd File New VHDL File OK. A blank text file will appear. We need to first save this as top.vhd File Save As. The file name should default to top.vhd, verify it is named correctly and click Save We will enter the VHDL for our system in this file later. G) Add the Dflipflop.vhd file to your design Download the Dflipflop.vhd file from the course website and put into your Lab08_ripple folder. Use the pull down menu to add the file: Project Add/Remove Files in Project Click the button, browse to the Dflipflop.vhd file, and click Open Then click the Add button on the next screen to add to your project. Click OK H) Enter the VHDL entity for the system. Based on the block diagram provided above, the ports are: Inputs: Clock, Reset These will be driven by KEY1 and KEY0 on the DE0-nano board. Outputs: LED (3 downto 0) This is the 4-bit vector for the LEDs (0,1,2,3) on the DE0-nano Segment_a These lines will drive the LED segments of the 7-segment display. Segment_b They go to the GPIO_0 header on the DE0-nano board. Segment_c These pins are connected to your breadboard using jumper wires. Segment_d Segment_e Segment_f Segment_g 4

5 Type in the following entity definition in your top.vhd file: (if not active, click on the Files tab and then double click on top.vhd. entity top is port (Clock, Reset : in BIT; LED : out BIT_VECTOR (3 downto 0); Segment_a : out BIT; Segment_b : out BIT; Segment_c : out BIT; Segment_d : out BIT; Segment_e : out BIT; Segment_f : out BIT; Segment_g : out BIT); end entity; I) Create the VHDL architecture for our system. Our architecture will include the 7-segment decoder from last week in addition to the ripple counter. In order to create the ripple counter, we need to use the Dflipflop.vhd file. To do this, we treat is as a component. A component is first declared in the architecture before the begin statement and then instantiated as many times as desired. We will need internal nodes to connect to the ports of the 4 Dflipflops. We ll also need to define two vectors COUNT(3 downto 0) and COUNTn(3 downto 0). Enter the following architecture pieces prior to the begin statement: 5

6 architecture top_arch of top is signal COUNT, COUNTn : BIT_VECTOR (3 downto 0); signal DISPLAY : BIT_VECTOR (6 downto 0); component Dflipflop port (Clock : in BIT; Reset : in BIT; D : in BIT; Q, Qn : out BIT); end component; begin Now we will instantiate 4 Dflipflops and connect the ports as in the above block diagram. We will wire the Qn output of each Dflipflop back to its D input using the signals COUNTn. The output Q of the Dflipflop will be connected to COUNT. The input port Clock will drive the Clock of the first Dflipflop. The COUNTn output of the first Dflipflop will drive the Clock input of the subsequent Dflipflop and so on. The Reset port will be connected to all Dflipflops. Enter the following Dflipflop instantiations after the begin statement: -- 4-bit ripple counter. U1 : Dflipflop port map (Clock, Reset, COUNTn(0), COUNT(0), COUNTn(0)); U2 : Dflipflop port map (COUNTn(0), Reset, COUNTn(1), COUNT(1), COUNTn(1)); U3 : Dflipflop port map (COUNTn(1), Reset, COUNTn(2), COUNT(2), COUNTn(2)); U4 : Dflipflop port map (COUNTn(2), Reset, COUNTn(3), COUNT(3), COUNTn(3)); This configuration will produce a 4-bit binary counter that is located on COUNT. We want to drive this value to the LEDs and also use it as the input to our 7-segment decoder. Copy your decoder VHDL from last week into your top.vhd and change the input signal in your selected signal assignment from SWn to COUNT. Also add the assignment from COUNT to LED: with (COUNT) select DISPLAY <= " " when "0000", " " when "0001", " " when "0010", " " when "0011", " " when "0100", " " when "0101", " " when "0110", " " when "0111", " " when "1000", " " when "1001", " " when "1010", " " when "1011", " " when "1100", " " when "1101", " " when "1110", " " when "1111"; Segment_a <= DISPLAY(6); -- Display Segment "a" Segment_b <= DISPLAY(5); -- Display Segment "b" Segment_c <= DISPLAY(4); -- Display Segment "c" Segment_d <= DISPLAY(3); -- Display Segment "d" Segment_e <= DISPLAY(2); -- Display Segment "e" Segment_f <= DISPLAY(1); -- Display Segment "f" Segment_g <= DISPLAY(0); -- Display Segment "g" LED <= COUNT; end architecture; 6

7 At this point, compile your design to make sure there are no syntax errors. You can compile by either using the pull-down menus (Processing Start Compilation) or by double clicking on the Compile Design task in the Flow window on the left side of the Quartus window. If you experience compile errors, fix them and recompile until you are successful. J) Assign the pins of the FPGA Open the Pin Planner (Assignments Pin Planner) and assign the pins: Clock,PIN_E1 Reset,PIN_J15 LED[0],PIN_A15 LED[1],PIN_A13 LED[2],PIN_B13 LED[3],PIN_A11 Segment_a,PIN_D3 Segment_b,PIN_C3 Segment_c,PIN_A3 Segment_d,PIN_B4 Segment_e,PIN_B5 Segment_f,PIN_D5 Segment_g,PIN_A6 7

8 Once done, close the Pin Planner window (it will save automatically). Now recompile your design. Lab Grading K) Program the FPGA Connect the DE0-nano board to the computer using the retractable USB cable. In the Flow window of Quartus, double click on Program Device (Open Programmer). Click the Start button in the programmer window: L) Test your design You should be able to press the KEY1 button and see your 7-segment display increment through all 16 HEX characters. You should also see the 4-bit binary count value on the LEDs of the DE0- nano board. TA will check off Pre-Lab / 10 Lab Demo (step 1) / 90 Total / 100 8