Bin. Befehl mnem. Op. meaning operation Flags clocks
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1 Bin. Befehl mnem. Op. meaning operation Flags clocks nop no operation ddddrrrr movw v,v copy register word Rd+1:Rd Rr+1:Rr ddddrrrr muls d,d multiply signed R1:R0 Rd*Rr ZC ddd0rrr mulsu a,a multiply signed with unsigned R1:R0 Rd*Rr ZC ddd1rrr fmul a,a fractional multiply unsigned R1:R0 (Rd*Rr)<<1 ZC ddd0rrr fmuls a,a fractional multiply signed R1:R0 (Rd*Rr)<<1 ZC ddd1rrr fmulsu a,a fr. multiply signed with unsigned R1:R0 (Rd*Rr)<<1 ZC rdddddrrrr cpc r,r compare with carry Rd Rr ZCNVH rdddddrrrr sbc r,r subtract with carry Rd Rd - Rr - C ZCNVH rdddddrrrr lsl r logical shift left Rd (n+1) Rd (n),rd (0) 0 ZCNV rdddddrrrr add r,r add two registers Rd Rd + Rr ZCNVH rdddddrrrr cpse r,r compare, skip if equal if (Rd==Rr) PC+=2 or 3 1/2/ rdddddrrrr cp r,r compare Rd Rr ZCNVH rdddddrrrr sub r,r subtract two registers Rd Rd Rr ZCNVH rdddddrrrr rol r rotate left through carry Rd (0) C,Rd (n+1) Rd (n),c Rd (7) ZCNV rdddddrrrr adc r,r add with carry Rd Rd + Rr + C ZCNVH rdddddrrrr and r,r logical AND Rd Rd & Rr ZNV rdddddrrrr tst r test for zero or minus Rd Rd and Rd ZNV rdddddrrrr eor r,r exclusiv or Rd Rd xor Rr ZNV rdddddrrrr clr r clear register Rd Rd xor Rd ZNV rdddddrrrr or r,r logical OR Rd Rd Rr ZNV rdddddrrrr mov r,r move between registers Rd Rr KKKKddddKKKK cpi d,m compare reg with constant Rd K ZNVCH KKKKddddKKKK sbci d,m subtract with carry const from reg Rd Rd -C -K ZNVCH KKKKddddKKKK subi d,m subtract constant from register Rd Rd -K ZNVCH KKKKddddKKKK ori d,m logical OR with constant Rd Rd K ZNV 1 Seite 1
2 0110KKKKddddKKKK sbr d,m set bits in register Rd Rd K ZNV KKKKddddKKKK andi d,m logical and with immidiate Rd Rd and K ZNV KKKKddddKKKK cbr d,n clear bits in register Rd Rd and (0xFF K) ZNV 1 100!000dddddee-+ ld r,e load from X,Y,Z Rd [X],[Y],[Z],/++/--, pre/post 2 100!001rrrrree-+ st e,r store into X,Y,Z [X],[Y],[Z],/++/--, pre/post Rr ddddd0000 lds r,i load direct fvrom SRAM Rd [16 Bit Constant] ddddd010+ lpm r,z load program memory Rd [Z], ev. Z ddddd011+ elpm r,z rrrrr1111 pop r pop register from stack Rd Stack ddddd0000 sts i,r store direct to SRAM [16 Bit Constant] Rr rrrrr1111 push r push register into stack Stack Rr sec set carry C 1 C ijmp indirect jump to Z PC Z sez set zero flag Z 0 Z sen set negative flag N 1 N sev set Two complents overflow V 1 V ses set signed test flag S 1 S seh set half carry flag H 1 H set set T in SREG T 1 T sei set global Interrupt (enable Int) I 1 I SSS1000 bset S set flag SREG[s]=1 S clc clear carry C 0 C clz clear zero flag Z 0 Z cln clear negative flag N 0 N clv clear two complents overflow V 0 V cls clear signed test flag S 0 S clh clear half carry flag H 0 H clt clear T in SREG T 0 T 1 Seite 2
3 cli clear global Interrupt (disable Int) I 0 I SSS1000 bclr S clear flag SREG[s]=0 S ret return PC Stack icall indirect call to Z PC Z reti return from Int PC Stack I eicall sleep sleep break wdr watch dog reset lpm? load program memory R0 [Z] elpm? spm store into program memory [Z] R1:R hhhhh110h jmp h hhhhh111h call h rrrrr0000 com r one's complement Rd 0xFF - Rd ZCNV rrrrr0001 neg r two's complement Rd 0x00 - Rd ZCNV rrrrr0010 swap r swap nibbles Rd (0..3) Rd (4..7) rrrrr0011 inc r increment register Rd++ ZNV rrrrr0101 asr r arithmetic shift right Rd (n) Rd (n+1),n=0..6 ZCNV rrrrr0110 lsr r logical shift right Rd (n+1) Rd (n), Rd 0 (0) rrrrr0111 ror r rotation rignt over carry Rd (7) C, Rd (n) Rd (n+1),c Rd (0) ZCNV rrrrr1010 dec r decrement register Rd-- ZNV KKddKKKK adiw w,k add immediate to word Rdh:Rdl Rdh:Rdl + Constant CZHVS KKddKKKK sbiw w,k subtract constant from wordreg. Rdh:Rdl Rdh:Rdl - Constant CZHVS pppppsss cbi p,s clear bit in I/O register I/O(P,b) pppppsss sbic p,s skip, if Bit in I/O reg. Is clear If P(b) ==0 PC PC+ 2, 3 1/2/ pppppsss sbi p,s set bit in I/O register I/O(P,b) pppppsss sbis p,s skip, if bit in I/O reg. Is set If P(b) ==1 PC PC+ 2, 3 1/2/3 Seite 3
4 100111rdddddrrrr mul r,r multiply unsigned R1:R0 RD*Rr ZC PPdddddPPPP in r,p in port Rd Port PPrrrrrPPPP out P,r out to port Port Rr 1 10o0oo0dddddbooo ldd r,b load indirect with displacement Rd [Y+disp], Rd [Z+disp] 2 10o0oo1rrrrrbooo std b,r store indirect with displacement [Y+disp] Rd, [Z+disp] Rd LLLLLLLLLLLL rjmp L relative jump PC PC + k LLLLLLLLLLLL rcall L relative call PC PC + k dddd1111 ser d set register Rd 0xFF KKKKddddKKKK ldi d,m load immidiate Rd K lllllll000 brcs l branch, if C ist set if (C==1) PC PC + k + 1 1/ lllllll000 brlo l branch, if lower if (C==1) PC PC + k + 1 1/ lllllll001 breq l branch, if equal if (Z==1) PC PC + k + 1 1/ lllllll010 brmi l branch, if minus if (N==1) PC PC + k + 1 1/ lllllll011 brvs l branch, if overflow is set if (V==1) PC PC + k + 1 1/ lllllll100 brlt l branch, if less then zero signed if ((N xor V)==1) PC PC + k + 1 1/ lllllll101 brhs l branch, if halfcarry if (H==1) PC PC + k + 1 1/ lllllll110 brts l branch, if T is set if (T==1) PC PC + k + 1 1/ lllllll111 brie l branch, if interrupt enabled if (I==1) PC PC + k + 1 1/ lllllllsss brbs s,l branch, if status flag set if (SREG(s)==1) PC PC + k + 1 1/ lllllll000 brsh l branch, if same or higher if (C==0) PC PC + k + 1 1/ lllllll000 brcc l branch, if carry cleared if (C==0) PC PC + k + 1 1/ lllllll001 brne l branch, if not equal if (Z==0) PC PC + k + 1 1/ lllllll010 brpl l branch, if plus if (N==0) PC PC + k + 1 1/ lllllll011 brvc l branch, if overflow is clear if (V==0) PC PC + k + 1 1/ lllllll100 brge l branch, if geater oder equal, signed if ((N xor V) ==0) PC PC + k + 1 1/ lllllll101 brhc l branch, if halfcarry clear if (H==0) PC PC + k + 1 1/ lllllll110 brtc l branch, if T claer if (T==0) PC PC + k + 1 1/ lllllll111 brid l branch, if interrupt disabled if (I==0) PC PC + k + 1 1/ 2 Seite 4
5 111101lllllllsss brbc s,l branch, if status flag clear if (SREG(s)==0) PC PC + k + 1 1/ ddddd0sss bld r,s bit load from T to register Rd(s) T ddddd0sss bst r,s bit store from register to T T Rd(s) rrrrr0sss sbrc r,s skip, if bit in reg. Is clear If R(b) ==0 PC PC+ 2, 3 1/2/ rrrrr0sss sbrs r,s skip, if bit in reg. Is set If R(b) ==1 PC PC+ 2, 3 1/2/ eijmp Legend: r any register d `ldi' register (r16-r31) v `movw' even register (r0, r2,..., r28, r30) a `fmul' register (r16-r23) w `adiw' register (r24,r26,r28,r30) e pointer registers (X,Y,Z) b base pointer register and displacement ([YZ]+disp) z Z pointer register (for [e]lpm Rd,Z[+]) M immediate value from 0 to 255 n immediate value from 0 to 255 ( n = ~M ). s immediate value from 0 to 7 P Port address value from 0 to 63. (in, out) p Port address value from 0 to??? (cbi, sbi, sbic, sbis) K immediate value from 0 to 63 (used in `adiw', `sbiw') i immediate value l signed pc relative offset from -64 to 63 L signed pc relative offset from to 2047 h absolute code address (call, jmp) S immediate value from 0 to 7 (S = s << 4)? use this opcode entry if no parameters, else use next opcode entry Seite 5
6 Zusammengestellt aus: Manual Atmega8, instruction summery A. Beck, 2010 Atmega8 Maschinenbefehle A. Beck, 04/2010 Seite 6
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8 T ist ein Bitspeicher für 1 Bit Seite 8
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