Instruction Set. Microcontroller Instruction Set. Instructions that Affect Flag Settings (1) The Instruction Set and Addressing Modes

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1 Microcontroller For interrupt response time information, refer to the hardware description chapter. Instructions that ffect Flag Settings (1) Instruction Flag Instruction Flag C OV C C OV C DD X X X CLR C O DDC X X X CPL C X SUBB X X X NL C,bit X MUL O X NL C,/bit X DIV O X C,bit X D X C,/bit X RRC X C,bit X RLC X CJNE X SETB C 1 Note: 1. Operations on SFR byte address 208 or bit addresses (that is, the PSW or bits in the PSW) also affect flag settings. The and ddressing Modes R n i #data #data 16 addr 16 addr 11 rel bit Register R7-R0 of the currently selected Register Bank. 8-bit internal data location s address. This could be an Internal Data RM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. ( )]. 8-bit internal data RM location (0-255) addressed indirectly through register R1or R0. 8-bit constant included in instruction. 16-bit constant included in instruction. 16-bit destination address. Used by LCLL and LJMP. branch can be anywhere within the 64K byte Program Memory address space. 11-bit destination address. Used by CLL and JMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction. Signed (two s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. Direct ddressed bit in Internal Data RM or Special Function Register. 0509B-B 12/

2 Summary NOP JBC bit,rel [3B, 2C] JB bit, rel [3B, 2C] JNB bit, rel [3B, 2C] JC rel JNC rel JZ rel JNZ rel 1 JMP (P0) CLL (P0) JMP (P1) CLL (P1) JMP (P2) CLL (P2) JMP (P3) CLL (P3) 2 LJMP addr16 [3B, 2C] LCLL addr16 [3B, 2C] RET [2C] RETI [2C] dir, NL dir, XRL dir, a C, bit 3 RR RRC RL RLC dir, #data [3B, 2C] NL dir, #data [3B, 2C] XRL dir, #data [3B, 2C] + DPTR [2C] 4 INC DEC DD, #data DDC, #data, #data NL, #data XRL, #data, #data 5 INC dir DEC dir DD, dir DDC, dir, dir NL, dir XRL, dir dir, #data [3B, 2C] 6 DDC, 7 DDC, @R1, #data 8 INC R0 DEC R0 DD, R0 DDC, R0, R0 NL, R0 XRL, R0 R0, #data 9 INC R1 DEC R1 DD, R1 DDC, R1, R1 NL, R1 XRL, R1 R1, #data INC R2 DEC R2 DD, R2 DDC, R2, R2 NL, R2 XRL, R2 R2, #data B INC R3 DEC R3 DD, R3 DDC, R3, R3 NL, R3 XRL, R3 R3, #data C INC R4 DEC R4 DD, R4 DDC, R4, R4 NL, R4 XRL, R4 R4, #data D INC R5 DEC R5 DD, R5 DDC, R5, R5 NL, R5 XRL, R5 R5, #data E INC R6 DEC R6 DD, R6 DDC, R6, R6 NL, R6 XRL, R6 R6, #data F INC R7 DEC R7 DD, R7 DDC, R7, R7 NL, R7 XRL, R7 R7, #data Note: Key: = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle 2-72

3 Summary (Continued) 8 9 B C D E F 0 SJMP REL DPTR,# data 16 [3B, 2C] C, /bit NL C, /bit PUSH dir POP dir [2C] [2C] 1 JMP (P4) CLL (P4) JMP (P5) CLL (P5) JMP (P6) CLL (P6) JMP (P7) CLL (P7) 2 NL C, bit bit, C C, bit CPL bit CLR bit SETB bit [2C] X wr0, [2C] 3 + PC [2C] + DPTR [2C] INC DPTR [2C] CPL C CLR C SETB C [2C] [2C] 4 DIV B [2B, 4C] SUBB, #data MUL B [4C] CJNE, #data, rel [3B, 2C] SWP D CLR CPL 5 dir, dir [3B, 2C] SUBB, dir CJNE, dir, rel [3B, 2C] XCH, dir DJNZ dir, rel [3B, 2C], dir dir, 6 SUBB, dir #data, rel [3B, 2C] 7 SUBB, dir #data, rel [3B, 2C] 8 dir, R0 SUBB, R0 R0, dir CJNE R0, #data, rel [3B, 2C] XCH, R0 DJNZ R0, rel, R0 R0, 9 dir, R1 SUBB, R1 R1, dir CJNE R1, #data, rel [3B, 2C] XCH, R1 DJNZ R1, rel, R1 R1, dir, R2 SUBB, R2 R2, dir CJNE R2, #data, rel [3B, 2C] XCH, R2 DJNZ R2, rel, R2 R2, B dir, R3 SUBB, R3 R3, dir CJNE R3, #data, rel [3B, 2C] XCH, R3 DJNZ R3, rel, R3 R3, C dir, R4 SUBB, R4 R4, dir CJNE R4, #data, rel [3B, 2C] XCH, R4 DJNZ R4, rel, R4 R4, D dir, R5 SUBB, R5 R5, dir CJNE R5, #data, rel [3B, 2C] XCH, R5 DJNZ R5, rel, R5 R5, E dir, R6 SUBB, R6 R6, dir CJNE R6, #data, rel [3B, 2C] XCH, R6 DJNZ R6, rel, R6 R6. F dir, R7 SUBB, R7 R7, dir CJNE R7, #data, rel [3B, 2C] XCH, R7 DJNZ R7, rel, R7 R7, Note: Key: = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle 2-73

4 Table 1. T89 Summary (1) Mnemonic Description Byte Oscillator Period RITHMETIC OPERTIONS Mnemonic Description Byte Oscillator Period LOGICL OPERTIONS DD,R n dd register to ccumulator NL,R n ND Register to ccumulator DD,direct dd direct byte to ccumulator 2 12 NL,direct ND direct byte to ccumulator 2 12 i dd indirect RM to ccumulator i ND indirect RM to ccumulator DD,#data dd immediate data to ccumulator 2 12 NL,#data ND immediate data to ccumulator 2 12 DDC,R n dd register to ccumulator with Carry NL direct, ND ccumulator to direct byte 2 12 DDC,direct dd direct byte to ccumulator with Carry 2 12 NL direct,#data ND immediate data to direct byte 3 24 i dd indirect RM to ccumulator with Carry,R n OR register to ccumulator DDC,#data dd immediate data to cc with Carry 2 12,direct OR direct byte to ccumulator 2 12 SUBB,R n Subtract Register from cc with i OR indirect RM to ccumulator SUBB,direct Subtract direct byte from cc with borrow 2 12,#data OR immediate data to ccumulator 2 12 i Subtract indirect RM from CC with borrow direct, OR ccumulator to direct byte 2 12 SUBB,#data Subtract immediate data from cc with borrow 2 12 direct,#data OR immediate data to direct byte 3 24 INC Increment ccumulator INC R n Increment register INC direct Increment direct byte 2 12 i Increment direct RM DEC Decrement ccumulator DEC R n Decrement Register DEC direct Decrement direct byte 2 12 i Decrement indirect RM INC DPTR Increment Data Pointer 1 24 MUL B Multiply & B 1 48 DIV B Divide by B 1 48 D Decimal djust ccumulator Note: 1. ll mnemonics copyrighted Intel Corp., XRL,R n Exclusive-OR register to ccumulator XRL,direct Exclusive-OR direct byte to ccumulator i Exclusive-OR indirect RM to ccumulator XRL,#data Exclusive-OR immediate data to ccumulator XRL direct, Exclusive-OR ccumulator to direct byte XRL direct,#data Exclusive-OR immediate data to direct byte CLR Clear ccumulator CPL Complement ccumulator RL Rotate ccumulator Left RLC Rotate ccumulator Left through the Carry LOGICL OPERTIONS (continued) 2-74

5 Mnemonic Description Byte Oscillator Period Mnemonic Description Byte Oscillator Period RR Rotate ccumulator Right Move Exernal RM (16- bit addr) to cc 1 24 RRC Rotate ccumulator Right through the Carry i, Move cc to External RM (8-bit addr) 1 24 SWP Swap nibbles within the ccumulator Move cc to External RM (16-bit addr) 1 24 DT TRNSFER,R n Move register to ccumulator,direct Move direct byte to i Move indirect RM to ccumulator,#data Move immediate data to ccumulator R n, Move ccumulator to register R n,direct Move direct byte to register R n,#data Move immediate data to register PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH,R n Exchange register with ccumulator XCH,direct Exchange direct byte with ccumulator i Exchange indirect RM with ccumulator i Exchange low-order Digit indirect RM with cc BOOLEN VRIBLE MNIPULTION CLR C Clear Carry direct, Move ccumulator to direct byte direct,r n Move register to direct byte direct,direct Move direct byte to direct 3 24 i Move indirect RM to direct byte direct,#data Move immediate data to direct i, Move ccumulator to indirect i,direct Move direct byte to indirect i,#data Move immediate data to indirect RM DPTR,#data16 Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to cc Move Code byte relative to PC to cc i Move External RM (8- bit addr) to cc DT TRNSFER (continued) CLR bit Clear direct bit 2 12 SETB C Set Carry SETB bit Set direct bit 2 12 CPL C Complement Carry CPL bit Complement direct bit 2 12 NL C,bit ND direct bit to CRRY 2 24 NL C,/bit ND complement of direct bit to Carry 2 24 C,bit OR direct bit to Carry 2 24 C,/bit OR complement of direct bit to Carry 2 24 C,bit Move direct bit to Carry 2 12 bit,c Move Carry to direct bit 2 24 JC rel Jump if Carry is set 2 24 JNC rel Jump if Carry not set 2 24 JB bit,rel Jump if direct Bit is set 3 24 JNB bit,rel Jump if direct Bit is Not set JBC bit,rel Jump if direct Bit is set & clear bit PROGRM BRNCHING

6 Mnemonic Description Byte Oscillator Period CLL addr11 bsolute Subroutine Call 2 24 LCLL addr16 Long Subroutine Call 3 24 RET Return from Subroutine 1 24 RETI Return from interrupt 1 24 JMP addr11 bsolute Jump 2 24 LJMP addr16 Long Jump 3 24 SJMP rel Short Jump (relative addr) Jump indirect relative to the DPTR JZ rel Jump if ccumulator is Zero JNZ rel Jump if ccumulator is Not Zero CJNE,direct,rel Compare direct byte to cc and Jump if Not Equal CJNE,#data,rel Compare immediate to cc and Jump if Not Equal CJNE R n,#data,rel Compare immediate to register and Jump if Not Equal i,#data,rel Compare immediate to indirect and Jump if Not Equal DJNZ R n,rel Decrement register and Jump if Not Zero DJNZ direct,rel Decrement direct byte and Jump if Not Zero NOP No Operation 2-76

7 Table 2. Instruction Opcodes in Hexadecimal Order Hex Code Number of Bytes 00 1 NOP Mnemonic Operands 01 2 JMP code addr 02 3 LJMP code addr 03 1 RR 04 1 INC 05 2 INC data addr INC R INC R1 0 1 INC R2 0B 1 INC R3 0C 1 INC R4 0D 1 INC R5 0E 1 INC R6 0F 1 INC R JBC bit addr,code addr 11 2 CLL code addr 12 3 LCLL code addr 13 1 RRC 14 1 DEC 15 2 DEC data addr DEC R DEC R1 1 1 DEC R2 1B 1 DEC R3 1C 1 DEC R4 1D 1 DEC R5 1E 1 DEC R6 1F 1 DEC R JB bit addr,code addr 21 2 JMP code addr 22 1 RET 23 1 RL 24 2 DD,#data 25 2 DD,data addr Hex Code Number of Bytes Mnemonic Operands DD,R DD,R1 2 1 DD,R2 2B 1 DD,R3 2C 1 DD,R4 2D 1 DD,R5 2E 1 DD,R6 2F 1 DD,R JNB bit addr,code addr 31 2 CLL code addr 32 1 RETI 33 1 RLC 34 2 DDC,#data 35 2 DDC,data addr DDC,R DDC,R1 3 1 DDC,R2 3B 1 DDC,R3 3C 1 DDC,R4 3D 1 DDC,R5 3E 1 DDC,R6 3F 1 DDC,R JC code addr 41 2 JMP code addr 42 2 data addr, 43 3 data addr,#data 44 2,#data 45 2,data addr ,R0 49 1,R1 4 1,R2 2-77

8 Hex Code Number of Bytes Mnemonic Operands Hex Code Number of Bytes Mnemonic Operands 4B 1,R3 4C 1,R4 4D 1,R5 4E 1,R6 4F 1,R JNC code addr 51 2 CLL code addr 52 2 NL data addr, 53 3 NL data addr,#data 54 2 NL,#data 55 2 NL,data addr NL,R NL,R1 5 1 NL,R2 5B 1 NL,R3 5C 1 NL,R4 5D 1 NL,R5 5E 1 NL,R6 5F 1 NL,R JZ code addr 61 2 JMP code addr 62 2 XRL data addr, 63 3 XRL data addr,#data 64 2 XRL,#data 65 2 XRL,data addr XRL,R XRL,R1 6 1 XRL,R2 6B 1 XRL,R3 6C 1 XRL,R4 6D 1 XRL,R5 6E 1 XRL,R6 6F 1 XRL,R JNZ code addr 71 2 CLL code addr 72 2 C,bit addr ,#data 75 3 data addr,#data R0,#data 79 2 R1,#data 7 2 R2,#data 7B 2 R3,#data 7C 2 R4,#data 7D 2 R5,#data 7E 2 R6,#data 7F 2 R7,#data 80 2 SJMP code addr 81 2 JMP code addr 82 2 NL C,bit addr DIV B 85 3 data addr,data addr 86 2 data 87 2 data 88 2 data addr,r data addr,r1 8 2 data addr,r2 8B 2 data addr,r3 8C 2 data addr,r4 8D 2 data addr,r5 8E 2 data addr,r6 8F 2 data addr,r DPTR,#data 91 2 CLL code addr 92 2 bit addr,c SUBB,#data 95 2 SUBB,data addr

9 Hex Code Number of Bytes Mnemonic Operands Hex Code Number of Bytes Mnemonic Operands SUBB,R SUBB,R1 9 1 SUBB,R2 9B 1 SUBB,R3 9C 1 SUBB,R4 9D 1 SUBB,R5 9E 1 SUBB,R6 9F 1 SUBB,R7 0 2 C,/bit addr 1 2 JMP code addr 2 2 C,bit addr 3 1 INC DPTR 4 1 MUL B BD 3 CJNE R5,#data,code addr BE 3 CJNE R6,#data,code addr BF 3 CJNE R7,#data,code addr C0 2 PUSH data addr C1 2 JMP code addr C2 2 CLR bit addr C3 1 CLR C C4 1 SWP C5 2 XCH,data addr C6 1 C7 1 C8 1 XCH,R0 C9 1 XCH,R1 C 1 XCH,R2 5 reserved CB 1 XCH,R3 6 addr 7 addr 8 2 R0,data addr 9 2 R1,data addr 2 R2,data addr B 2 R3,data addr C 2 R4,data addr D 2 R5,data addr E 2 R6,data addr F 2 R7,data addr B0 2 NL C,/bit addr B1 2 CLL code addr B2 2 CPL bit addr B3 1 CPL C B4 3 CJNE,#data,code addr B5 3 CJNE,data addr,code addr B6 3 addr B7 3 addr B8 3 CJNE R0,#data,code addr B9 3 CJNE R1,#data,code addr B 3 CJNE R2,#data,code addr BB 3 CJNE R3,#data,code addr BC 3 CJNE R4,#data,code addr CC 1 XCH,R4 CD 1 XCH,R5 CE 1 XCH,R6 CF 1 XCH,R7 D0 2 POP data addr D1 2 CLL code addr D2 2 SETB bit addr D3 1 SETB C D4 1 D D5 3 DJNZ data addr,code addr D6 1 D7 1 D8 2 DJNZ R0,code addr D9 2 DJNZ R1,code addr D 2 DJNZ R2,code addr DB 2 DJNZ R3,code addr DC 2 DJNZ R4,code addr DD 2 DJNZ R5,code addr DE 2 DJNZ R6,code addr DF 2 DJNZ R7,code addr E0 1 E1 2 JMP code addr E

10 Hex Code Number of Bytes Mnemonic Operands E3 1 E4 1 CLR E5 2,data addr E6 E7 E8 1,R0 E9 1,R1 E 1,R2 EB 1,R3 EC 1,R4 ED 1,R5 EE 1,R6 EF 1,R7 F0 1 F1 2 CLL code addr F2 1 F3 1 F4 1 CPL F5 2 data addr, F6 F7 F8 1 R0, F9 1 R1, F 1 R2, FB 1 R3, FC 1 R4, FD 1 R5, FE 1 R6, FF 1 R7, 2-80

11 Instruction Definitions CLL addr11 Function: bsolute Call Description: CLL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction. The subroutine called must therefore start within the same 2 K block of the program memory as the first byte of the instruction following CLL. No flags are affected. Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345 H. fter executing the following instruction, CLL SUBRTN at location 0123H, SP contains 09H, internal RM locations 08H and 09H will contain 25H and 01H, respectively, and the PC contains 0345H. Encoding: a10 a9 a a7 a6 a5 a4 a3 a2 a1 a0 Operation: CLL (PC) (PC) + 2 (SP) (SP) + 1 ((SP)) (PC 7-0 ) (SP) (SP) + 1 ((SP)) (PC 15-8 ) (PC 10-0 ) page address 2-81

12 DD,R n i DD,<src-byte> Function: dd Description: DD adds the byte variable indicated to the ccumulator, leaving the result in the ccumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The ccumulator holds 0C3H ( lB), and register 0 holds 0H ( B). The following instruction, DD,R0 leaves 6DH ( B) in the ccumulator with the C flag cleared and both the carry flag and OV set to 1. DD,direct Encoding: r r r Operation: DD () () + (R n ) Encoding: direct address Operation: DD () () + (direct) DD,#data Encoding: i Operation: DD () () + ((R i )) Encoding: immediate data Operation: DD () () + #data 2-82

13 DDC,R n DDC, <src-byte> Function: dd with Carry Description: DDC simultaneously adds the byte variable indicated, the carry flag and the ccumulator contents, leaving the result in the ccumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate. Example: The ccumulator holds 0C3H ( B) and register 0 holds 0H ( B) with the carry flag set. The following instruction, DDC,R0 leaves 6EH ( B) in the ccumulator with C cleared and both the Carry flag and OV set to 1. DDC,direct i DDC,#data Encoding: r r r Operation: DDC () () + (C) + (R n ) Encoding: direct address Operation: DDC () () + (C) + (direct) Encoding: i Operation: DDC () () + (C) + ((R i )) Encoding: immediate data Operation: DDC () () + (C) + #data 2-83

14 NL,R n JMP addr11 Function: bsolute Jump Description: JMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following JMP. Example: The label JMPDR is at program memory location 0123H. The following instruction, JMP JMPDR is at location 0345H and loads the PC with 0123H. Encoding: a10 a9 a a7 a6 a5 a4 a3 a2 a1 a0 Operation: JMP (PC) (PC) + 2 (PC 10-0 ) page address NL <dest-byte>,<src-byte> Function: Logical-ND for byte variables Description: NL performs the bitwise logical-nd operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the ccumulator, the source can use register, direct, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the ccumulator or immediate data. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: If the ccumulator holds 0C3H ( lB), and register 0 holds 55H ( B), then the following instruction, NL,R0 leaves 41H ( B) in the ccumulator. When the destination is a directly addressed byte, this instruction clears combinations of bits in any RM location or hardware register. The mask byte determining the pattern of bits to be cleared would either be a constant contained in the instruction or a value computed in the ccumulator at run-time. The following instruction, NL P1,# B clears bits 7, 3, and 2 of output port 1. Encoding: r r r Operation: NL () () (R n ) 2-84

15 NL NL NL NL NL,direct Encoding: direct address Operation: NL () () i Encoding: i Operation: NL () () ((R i )),#data Encoding: immediate data Operation: NL () () #data direct, Encoding: direct address Operation: NL (direct) (direct) () direct,#data Bytes: 3 Encoding: direct address immediate data Operation: NL (direct) (direct) #data 2-85

16 NL NL NL C,<src-bit> Function: Logical-ND for bit variables Description: If the Boolean value of the source bit is a logical 0, then NL C clears the carry flag; otherwise, this instruction leaves the carry flag in its current state. slash ( / ) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. Only direct addressing is allowed for the source operand. Example: Set the carry flag if, and only if, P1.0 = 1, CC.7 = 1, and OV = 0: C,bit C,P1.0 ;LOD CRRY WITH INPUT PIN STTE NL C,CC.7 ;ND CRRY WITH CCUM. BIT 7 NL C,/OV ;ND WITH INVERSE OF OVERFLOW FLG Encoding: bit address Operation: NL (C) (C) (bit) C,/bit Encoding: bit address Operation: NL (C) (C) (bit) 2-86

17 CJNE <dest-byte>,<src-byte>, rel Function: Compare and Jump if Not Equal. Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected. CJNE,direct,rel The first two operands allow four addressing mode combinations: the ccumulator may be compared with any directly addressed byte or immediate data, and any indirect RM location or working register can be compared with an immediate constant. Example: The ccumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence, Bytes: 3 CJNE R7, # 60H, NOT_EQ ; ;R7 = 60H. NOT_EQ: JC REQ_LOW ;IF R7 < 60H. ; ;R7 > 60H. sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to Port 1 is also 34H, then the following instruction, WIT: CJNE, P1,WIT clears the carry flag and continues with the next instruction in sequence, since the ccumulator does equal the data read from P1. (If some other value was being input on P1, the program loops at this point until the P1 data changes to 34H.) Encoding: direct address rel. address Operation: (PC) (PC) + 3 IF () < > (direct) THEN (PC) (PC) + relative offset IF () < (direct) THEN (C) 1 ELSE (C)

18 CJNE,#data,rel Bytes: 3 Encoding: immediate data rel. address Operation: (PC) (PC) + 3 IF () < > data THEN (PC) (PC) + relative offset IF () < data THEN (C) 1 ELSE (C) 0 CJNE R n,#data,rel Bytes: 3 Encoding: r r r immediate data rel. address Operation: (PC) (PC) + 3 IF (R n ) < > data THEN (PC) (PC) + relative offset IF (R n ) < data THEN (C) 1 ELSE (C) 0 i,data,rel Bytes: 3 Encoding: i immediate data rel. address Operation: (PC) (PC) + 3 IF ((R i )) < > data THEN (PC) (PC) + relative offset IF ((R i )) < data THEN (C) 1 ELSE (C)

19 CLR CLR CLR CLR Function: Clear ccumulator Description: CLR clears the ccumulator (all bits set to 0). No flags are affected Example: The ccumulator contains 5CH ( B). The following instruction,clr leaves the ccumulator set to 00H ( B). bit Encoding: Operation: CLR () 0 Function: Clear bit Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. C Example: Port 1 has previously been written with 5DH ( B). The following instruction,clr P1.2 leaves the port set to 59H ( B). Encoding: Operation: CLR (C) 0 bit Encoding: bit address Operation: CLR (bit)

20 CPL CPL CPL Function: Complement ccumulator Description: CPL logically complements each bit of the ccumulator (one s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected. Example: The ccumulator contains 5CH ( B). The following instruction, bit CPL leaves the ccumulator set to 03H ( B). Encoding: Operation: CPL () () Function: Complement bit Description: CPL bit complements the bit variable specified. bit that had been a 1 is changed to 0 and vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit. C Note: When this instruction is used to modify an output pin, the value used as the original data is read from the output data latch, not the input pin. Example: Port 1 has previously been written with 5BH ( B). The following instruction sequence,cpl P1.1CPL P1.2 leaves the port set to 5BH ( B). Encoding: Operation: CPL (C) (C) CPL bit Encoding: bit address Operation: CPL (bit) (bit) 2-90

21 D Function: Decimal-adjust ccumulator for ddition Description: D adjusts the eight-bit value in the ccumulator resulting from the earlier addition of two variables (each in packed-bcd format), producing two four-bit digits. ny DD or DDC instruction may have been used to perform the addition. If ccumulator bits 3 through 0 are greater than nine (xxxx1010-xxxx1111), or if the C flag is one, six is added to the ccumulator producing the proper BCD digit in the low-order nibble. This internal addition sets the carry flag if a carry-out of the low-order four-bit field propagates through all high-order bits, but it does not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. gain, this sets the carry flag if there is a carry-out of the high-order bits, but does not clear the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than 100, allowing multiple precision decimal addition. OV is not affected. ll of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal conversion by adding 00H, 06H, 60H, or 66H to the ccumulator, depending on initial ccumulator and PSW conditions. Note: D cannot simply convert a hexadecimal number in the ccumulator to BCD notation, nor does D apply to decimal subtraction. Example: The ccumulator holds the value 56H ( B), representing the packed BCD digits of the decimal number 56. Register 3 contains the value 67H ( B), representing the packed BCD digits of the decimal number 67. The carry flag is set. The following instruction sequence DDC D,R3 first performs a standard two s-complement binary addition, resulting in the value 0BEH ( ) in the ccumulator. The carry and auxiliary carry flags are cleared. The Decimal djust instruction then alters the ccumulator to the value 24H ( B), indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag is set by the Decimal djust instruction, indicating that a decimal overflow occurred. The true sum of 56, 67, and 1 is 124. BCD variables can be incremented or decremented by adding 01H or 99H. If the ccumulator initially holds 30H (representing the digits of 30 decimal), then the following instruction sequence, DD D, # 99H leaves the carry set and 29H in the ccumulator, since = 129. The low-order byte of the sum can be interpreted to mean 30-1 = 29. Encoding: Operation: D -contents of ccumulator are BCD IF [[( 3-0 ) > 9] [(C) = 1]] THEN ( 3-0 ) ( 3-0 ) + 6 ND IF [[( 7-4 ) > 9] [(C) = 1]] THEN ( 7-4 ) ( 7-4 )

22 DEC R n i DEC DEC byte Function: Decrement Description: DEC byte decrements the variable indicated by 1. n original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7FH ( B). Internal RM locations 7EH and 7FH contain 00H and 40H, respectively. The following instruction sequence, DEC DEC leaves register 0 set to 7EH and internal RM locations 7EH and 7FH set to 0FFH and 3FH. Encoding: Operation: DEC () () - 1 Encoding: r r r DEC Operation: DEC (R n ) (R n ) - 1 direct Encoding: direct address Operation: DEC (direct) (direct) - 1 Encoding: i Operation: DEC ((R i )) ((R i ))

23 DIV B Function: Divide Description: DIV B divides the unsigned eight-bit integer in the ccumulator by the unsigned eight-bit integer in register B. The ccumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the ccumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case. Example: The ccumulator contains 251 (0FBH or B) and B contains 18 (12H or B). The following instruction, Cycles: 4 DIV B leaves 13 in the ccumulator (0DH or B) and the value 17 (11H or B) in B, since 251 = (13 x 18) Carry and OV are both cleared. Encoding: Operation: DIV () 15-8 ()/(B) (B)

24 DJNZ DJNZ R n,rel <byte>,<rel-addr> Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. n original value of 00H underflows to 0FFH. No flags are affected. The branch destination is computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Internal RM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H, respectively. The following instruction sequence, DJNZ direct,rel DJNZ DJNZ DJNZ 40H,LBEL_1 50H,LBEL_2 60H,LBEL_3 causes a jump to the instruction at label LBEL_2 with the values 00H, 6FH, and 15H in the three RM locations. The first jump was not taken because the result was zero. This instruction provides a simple way to execute a program loop a given number of times or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The following instruction sequence, R2, # 8 TOGGLE: CPL P1.7 DJNZ R2,TOGGLE toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse lasts three machine cycles; two for DJNZ and one to alter the pin. Encoding: r r r rel. address Operation: DJNZ (PC) (PC) + 2 (R n ) (R n ) - 1 IF (R n ) > 0 or (R n ) < 0 THEN (PC) (PC) + rel Bytes: 3 Encoding: direct address rel. address Operation: DJNZ (PC) (PC) + 2 (direct) (direct) - 1 IF (direct) > 0 or (direct) < 0 THEN (PC) (PC) + rel 2-94

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