measurement electronics platform idflex

Transcription

1 measurement electronics platform

2 What is? is a electronics library for quick and performant instrument development Devices Power and low noise sources Analog <-> Digital Extra high bandwith data aqcuisition various FPGA Modules on Board RAM (DDR2) Features Scalable Pin Count Scalable Functionality Compact Form Factor Standard firmware updates Custom firmware Applications Image Sensor Tester Mixed Signal Tester Machine Vision Cameras Evaluation Systems Custom Specific Solutions 1/2014, Page 2

3 Product Range The modular nature of realizes your different applications Custom modules extend your systems Individual Module: ADC 8Ch;14bit; 50MS/s idsmart Camera: Imager Module + FPGA idmod Tester: 512Ch; 8 sites 1/2014, Page 3

4 1/2014, Page 4 Instrument Range

5 1/2014, Page 5 Key Features Flexible Architecture Signal conditioning close to DUT µcontroller per module permits independent operation Multi site solutions (e.g. 8 sides x 3 slots = 24 slot system) In system programming High Data Bandwidth Up to 600Mbit/s with single LVDS channel Up to 10Gbit/s link between and host PC Signal sample depth (up to 10Gbit/s into host RAM, above 10Gbit/s into internal RAM) Modular Power Concept Multiple channels Cost effective internal power supplies Interfaces to high end third party power supplies

6 1/2014, Page 6 Configure your Instruments Library of Modules Custom Configuration Solution

7 Scaleable Pin Count Slots Signals Powers /2014, Page 7

8 Functionality 1/2014, Page 8 Scaleable Features CTU

9 From Lab to Fab Project Challenges Cost Complexity Time to Market Quality Chip Design Wafer Fab Characterization Wafer Level Tests Chip Assembly Chip Level Tests Chip Production Production Wafer Test Chip Assembly Chip Final Test Eval/Demo Qualification Application Assembly Application Final Test Application 1 Application 2 Pre Test Device Stress Customer Service is Solution should be Application Adaptable by modular configuration Reliable by standard instruments Future Compatible by module extension Performance by architecture Post Test 1/2014, Page 9

10 measurement electronics platform Library Details

11 1/2014, Page 11 Form Factor

12 1/2014, Page 12 Slot Configuration PWR Bus 9 power channels DGND and AGND can be separated Signal Bus 64 signals (analog or digital) pptional 60Ch +2 differential clocks for synchronization Control Bus 2pol serial communication interface 4 control pins (low voltage TTL) JTAG interface (in system programming)

13 ADC 8Ch, 14bit, 50MS/s 1/2014, Page 13 Module Types Fixed but adjustable features reconfigurable module (FPGA based) e.g. Xilinx Virtex II FPGA

14 Available Modules Digital Modules Single Ended Differential Module RAM IO [Count] Speed [Mbit/s] IO [Count] Speed [Mbit/s] Mbit Speed [Gbit/s] 1Slot_FPGA_# Slot_FPGA_# Slot_FPGA_# Slot_FPGA_# Pin Electronic Ch Speed Driver Range Module Interface [Count] [MS/s] Comperator [V] Control DUT 2Slot_PINE_# yes 0,5..12 FPGA Module Direct Analog Modules Ch Speed Resolution Mode Module Interface [Count] [Sample/s] [bit] (Range) Control DUT 1Slot_ADC_#1 8 50M 14 MV (2Vpp) FPGA Module Direct or SigCon 1Slot_DAC_#1 32 static 12 FV (0..4V) internal Direct or SigCon 1Slot_CTU_#1 Mux 64x1 1K 12 FV/FI/MV internal Direct or SigCon 2Slot_SMU_#1* 16 10k 16 FV/FI/MV/MI internal Direct or SigCon Signal Range Module Interface Description Conditioning Control DUT 1Slot_Buffer 8Ch High Impedance Module for ADC Module -2,5V..2,5 [V] ADC Module Direct 1Slot_RefU/I 32 Signal Conditiong Module for DAC Module 0..4[V]/0..5[mA] DAC Module Direct Power Modules Ch Max. Current Resolution Range Module Interface [Count] [A] [bit] [V] Control DUT 1Slot_PWR_#2 2 1,3 3 5 internal Direct 1Slot_PWR_#3 4 0, internal Direct 1Slot_PWR_#4 2 0, internal Direct 1Slot_DPS_#1* 2 0, internal Direct * current design activities, design targets ** without interface modules *** speed parameters depend upon module combinations and applications 1/2014, Page 14

15 Systembus0 and 1 (Top and Bottom) Databus1 Top Databus0 Top 25Ch I/O 5V 24Ch I/O 16Ch Data I/O 6Ch I/O 16Ch CTRL 17ch Addr. 6Ch I/O Databus1 Bottom Databus0 Bottom 1/2014, Page 15 1Slot FPGA #2 (+ Utility) FPGA Xilinx Spartan 6 XC6SLX16-CSG324 64Ch DDR LVDS I/O speed up to 600Mbit/s Block RAM 570kBit Multicomp 40pol Top DDR2 RAM 667Mbit/s RAM Clock DDR2 SDRAM (667Mbit/s; 1Gbit) XCF32P Flash PROM 64Ch I/O 64Ch I/O 32Mbit capacity Micro SD Card Slot 4Ch Trigger 2Ch RS-232 Xilinx Spartan 6 FPGA 6Ch I/O Flash PROM up to 32 GByte USB 2.0 Controller FT 2232H All powers upon module JTAG Connector PWR Connector EEPROM USB Connector USB Controller µc Micro SD Card Slot 12V Voltage Regulator 1,2V / 1,8V / 3,3V / adj DUT Power

16 Systembus0 (Top and Bottom) 6Ch I/O 6Ch I/O Databus0 Top 25Ch I/O 16Ch Data I/O 16Ch CTRL 17ch Addr. Databus0 Bottom 1Slot FPGA #3 FPGA Xilinx Spartan 6 XC6SLX16-CSG324 DDR LVDS I/O speed up to 600Mbit/s Block RAM 570kBit RAM DDR2 SDRAM (667Mbit/s; 1Gbit) XCF32P Flash PROM 32Mbit capacity µcontroller Atmel ATmega 16L Micro SD Card Slot Multicomp 40pol Top 64Ch I/O 4Ch Trigger 2Ch RS-232 JTAG Clock DDR2 RAM 667Mbit/s Xilinx Spartan 6 FPGA 64Ch I/O 6Ch I/O Flash PROM up to 32 GByte Voltage 12V 1,2V / Regulator µc Micro SD Card Slot 1,8V / 3,3V 1/2014, Page 16

17 2Slot FPGA #2 FPGA Xilinx Virtex II Pro XC2VP20-676FG DDR LVDS I/O speed up to 800Mbit/s Block RAM 1,5MBit Embedded 300+ MHz Harvard Architecture Block (PowerPC) High-performance clock management circuitry Select I/O -Ultra technology Selectable IO voltage (solder jumper) JTAG programmable XCF32P Flash PROM 32Mbit capacity Endurance of program/erase cycles JTAG programmable µcontroller Atmel ATmega 16L 1/2014, Page 17

18 USW.. 1/2014, Page 18