Data Storage Servers Networking Telecommunications

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1 This on board power system controller provides a flexible, cost effective, and high performance solution for controlling, monitoring, and sequencing multiple Point of Load (PoL) converters on a system board. The controller uses a digital signal processor (DSP) engine and Bel s firmware to implement a portfolio of board level control features typically required in a multiple voltage power system. This solution can monitor and control (with active trim) up to four PoL converters and monitor up to two additional analog inputs. Digital Signal Processor (DSP) Based with Bel Firmware Provides Power Up and Power Down Sequencing Logic Stand Alone or Command Based Fault Detection and Reporting 44-Pin 10 mm x 10 mm TQFP package I2C, SMBus, or PMBus compatible serial interface options Configurable through serial interface, Customizable through software 3V3 logic levels Voltage set point control and Margining via Closed Loop Trim Analog Input Monitoring Programmed parameters saved in non-volatile memory Intelligent configuration capability Power-down data log for identifying fault conditions Boot loader for in-system upgrading GUI for defining board configuration parameters and board monitoring Data Storage Servers Networking Telecommunications This part is one in a family of the Bel Power System Controllers. Refer to Bel for additional controllers with different capabilities. PART NUMBER NUMBER OF PINS NUMBER OF TRIMMED RAILS NUMBER OF ADDITIONAL MONITORED RAILS NUMBER OF POWER ZONES TRKF-44D42SR

2 2 TRKF-44D42SR Figure 1 provides a Functional Block Diagram of the Power System Controller. Digital Inputs (from System CPU) Enable Reset In Mfg Mode Margin High Margin Low Digital Outputs (to System CPU) Power Good Warning Reset Output A Reset Output B /2 External Reference (+/-) Analog Voltage Monitoring /2 Monitor Vin Monitor Analog Voltages (A-B) Digital I/O Control /4 Monitor PoL Vout (1-4) Voltage Attenuation Resistors (if required) PMBus/I2C Communications (with System CPU) Clock Data PMBus / I2C Engine Internal Flash (board configuration data, fault log) Main Engine Power System Controller Active Trim Control Sequence Up/Down Control Trim PoL PWM Output /4 PWM Trim Circuit Enable PoL (1-4) /4 Enable Analog (A-B) /2 PoL Input Power Enable Trim PoL Converters 1 of 4 Enable Vin GND Vout Figure 1. Functional Block Diagram A Configuration GUI is used to define the various board specific parameters (such as turn on and turn off input voltage thresholds, output voltage set points and limits, digital I/O logic polarity, and sequencing requirements). See Section 2, Configurable Parameters for a complete list. These parameters are sent to the part and saved in its non-volatile on-board flash memory during the board development or manufacturing processes. tech.support@psbel.com

3 TRKF-44D42SR 3 While in operation, the controller manages the voltage rails as follows: A. Sequence Up Operation The controller performs the power up sequence when the monitored input voltage is greater than the configured turn-on threshold and the enable input is asserted. It goes through each sequence step and enables the desired outputs and delays for the desired amount of time. It then checks that the enabled outputs are within their configured power good limits. If they are, it continues to the next sequence step. If not, it sequences down from this step back to the first. After the sequence up operation completes, it then delays for the configured power good delay value and then asserts the power good output signal. B. Active Trim The part performs an active trim of the PoLs by comparing the measured PoL output voltages with the desired set points and then adjusts the duty cycle of the trim PWMs. This provides for an accurate set point over time and temperature requiring only one precision voltage reference for the entire power system. If margin testing is desired, the set points are set to the configured margin high or low values and the output is trimmed to that value. C. Fault Detection Upper and lower warning and power good limits are defined for each voltage and warning and power good masks are used to indicate which rails cause warning conditions or power good faults. Fault logs containing the running time, voltages, and status flags are stored in non-volatile memory for board diagnosis. D. Sequence Down Operation The controller performs the power down sequence when the monitored input voltage is less than the configured turn-off threshold, the enable input is de-asserted, or if there is a power good fault. It goes through each sequence step from last to the first and disables the outputs. The Bel Configurator is a PC-based graphical user interface application that is used to define the various board parameters. This application is used to program the board settings into the part and may also be used interface with the part for board development or diagnosis. CATEGORY Operating Settings PoL and Analog Voltage Monitor Delay and Sequences Power Good and Warning Reset Outputs Digital Inputs Digital Outputs PARAMETERS I2C slave address ADC external reference voltage Warning output behavior (latching, non-latching) Trim PWM frequency Input voltage monitor attenuation resistor values Turn-on voltage threshold Turn-off voltage threshold Input over voltage threshold Voltage monitor attenuation resistor values Voltage set points Margin percentages (low/high) Warning limit percentages (low/high) Power good limit percentages (low/high) Default PWM duty cycle PoL trim logic Sequence enable masks (6 steps) Sequence delays (7 values) Power good mask Power good delay Warning mask Warning delay Reset A mask Reset A delay Reset B mask Reset B delay Input polarity (active high/low) Output polarity (active high/low) Output open drain option Asia-Pacific Europe, Middle East North America Bel Power Solutions & Protection BCD.00841_AA

4 4 TRKF-44D42SR I/O TYPE QUANTITY SIGNALS Analog Input 7 Monitor PoLs (4), Monitor Analogs (2), Monitor Vin Digital Input 5 Enable, Mfg Mode, Margin High, Margin Low, Reset In Digital Output 13 Enable PoLs (4), Enable Analogs (2), Input Power Enable/OVP Trip, Reset Outputs (2), Power Good, Warning, Spare (2) External Reference 2 VREF-, VREF+ I2C Communications 1 2 I2C Clock, I2C Data Power 8 VDD, VSS, AVDD, AVSS, VCAP/VDDCORE Programming 2 3 /MCLR, ICSP Data, ICSP Clock PWM Trim 4 Trim PoLs (4) Notes: 1. The I2C communication signals (I2C Clock, I2C Data, VDD, and VSS) must be brought to an interface header to initially load the board specific configuration data and optionally communicate with the device during board development. These signals may also be connected to a host microprocessor for system integration. 2. It is suggested that the /MCLR, VDD, VSS, ICSP Data, and ICSP Clock signals be brought to a programming header on the board in case it becomes necessary to reprogram the part using an in-circuit serial programmer. PIN NO. SIGNAL DESCRIPTION I/O TYPE OR FUNCTION 5V TOLERANT 1 I2C Data I2C Communications Y 2 Enable PoL 4 Digital Output Y 3 Enable PoL 3 Digital Output Y 4 Enable PoL 2 Digital Output Y 5 Enable PoL 1 Digital Output Y 6 VSS Power N 7 VCAP/VDDCORE Power N 8 Input Power Enable / OVP Trip Digital Output Y 9 Reset Output A Digital Output Y 10 Trim PoL 4 PWM Trim N 11 Trim PoL 3 PWM Trim N 12 Power Good Digital Output Y 13 Warning Digital Output Y 14 Trim PoL 2 PWM Trim N 15 Trim PoL 1 PWM Trim N 16 AVSS Power N 17 AVDD Power N 18 /MCLR Programming Y 19 VREF+ External Reference N 20 VREF- External Reference N 21 Monitor PoL 1 Analog Input N 22 Monitor PoL 2 Analog Input N 23 Monitor PoL 3 Analog Input N 24 Monitor PoL 4 Analog Input N 25 Monitor Vin Analog Input N 26 Monitor Analog A Analog Input N 27 Monitor Analog B Analog Input N 28 VDD Power N 29 VSS Power N 30 Enable Digital Input N tech.support@psbel.com

5 TRKF-44D42SR 5 PIN NO. SIGNAL DESCRIPTION I/O TYPE OR FUNCTION 5V TOLERANT 31 Mfg Mode Digital Input N 32 Reset Output B Digital Output Y 33 Spare (N/C) Digital Output N 34 Spare (N/C) Digital Output N 35 Enable Analog B Digital Output Y 36 Enable Analog A Digital Output Y 37 Margin High Digital Input Y 38 Margin Low Digital Input Y 39 VSS Power N 40 VDD Power N 41 ICSP Data Programming Y 42 ICSP Clock Programming Y 43 Reset Input Digital Input Y 44 I2C Clock I2C Communications Y The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification defined in the Electrical Specifications. SIGNAL TYPE DEFINITION AVDD Power Positive supply (filtered VDD) for powering the ICs analog circuitry. See Section 6, Powering the Controller. AVSS Power Analog ground reference. See Section 6, Powering the Controller. Enable Digital Input When asserted and if the input voltage is above the turn on threshold, the board is sequenced up. When de-asserted, the board is sequenced down. This function can be overridden as defined in the separate interface document. Enable Analog (A-B) Digital Output Optional enable signals if Analog A and B are controlled converters, such as LDOs, VRMs, or PoLs that do not require active trim or margining. Asserted during sequence up and deasserted during sequence down. Enable PoL (1-4) Digital Output Enable signal for the PoL converters. Asserted during sequence up and de-asserted during sequence down. I2C Clock I2C Communications Synchronous serial clock input/output for I2C communication. Since this is an I2C slave device, the master drives the clock. Clock stretching may occur if necessary according to the I2C specification. I2C Data I2C Communications Synchronous serial bi-directional data line for I2C communication. ICSP Clock Programming Clock input pin for in-circuit serial programming. ICSP Data Programming Data I/O pin for in-circuit serial programming. Input Power Enable / OVP Trip Digital Output If this pin is configured as an Input Power Enable, it is the enable signal for an optional power input circuit for powering the PoLs. Asserted during sequence up and de-asserted during sequence down. If an OVP fault is detected (any monitored output voltage is greater than the power good upper limit), the Input Power Enable output is de-asserted first at power down. If no OVP fault occurs, the Input Power Enable output is de-asserted last at power down. If this pin is configured as an OVP Trip output, it is asserted when an OVP fault is detected (any monitored output voltage is greater than the power good upper limit). Margin High Digital Input When asserted (and if the Mfg Mode input is asserted), then the PoLs will be margined to their configured high margin values. Margin Low Digital Input When asserted (and if the Mfg Mode input is asserted), then the PoLs will be margined to their configured low margin values. /MCLR Programming Master Clear (Reset) input. This pin is an active-low reset to the device. This signal must be pulled-up to VDD with a 10k resistor. Mfg Mode Digital Input Enable signal for the hardware margin signals. When asserted, the margin high/low inputs will cause the PoLs to be margined to their configured high/low margin values. Monitor Analog (A-B) Analog Input Voltage monitor of Analog A-B inputs (must be scaled using attenuating resistors if voltage exceeds reference voltage). Monitor PoL (1-4) Analog Input PoL output voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Monitor Vin Analog Input System input voltage monitor (must be scaled using attenuating resistors if voltage exceeds reference voltage). Asia-Pacific Europe, Middle East North America Bel Power Solutions & Protection BCD.00841_AA

6 6 TRKF-44D42SR Power Good Digital Output Asserted after the configured power good delay after all of the outputs have been sequenced up and are operating within their configured power good limits. De-asserted prior to sequencing down due to a fault or commanded to do so. Reset Input Digital Input When asserted, causes Reset outputs to assert. Reset Outputs (A, B) Digital Output Asserted when Reset In is asserted. De-asserted when any outputs in configured reset masks are outside of power good limits. Reset outputs can also be controlled by PMBus commands. Spare (N/C) Digital Output Reserved for future use. Trim PoL (1-4) PWM Trim PWM outputs for actively trimming the analog PoLs to their desired set points. See Section 7, Using the PWM Trim Outputs. VCAP/VDDCORE Power Core decoupling capacitor. See Section 6, Powering the Controller. VDD Power Positive supply (3.3V) for peripheral logic and I/O pins. See Section 6, Powering the Controller. VREF- External Reference ADC voltage reference (low) input. VREF+ External Reference ADC voltage reference (high) input. VSS Power Ground reference for logic and I/O pins. See Section 6, Powering the Controller. Warning Digital Output This output is asserted when any of the monitored output voltages are less than their configured warning lower limit or greater than their configured warning upper limit. Any unused digital inputs should be pulled to ground (VSS) with a 10k resistor. Figure 2. Power Interface Figure 2 is a schematic of the typical 3.3V VDD interface to the Power System Controller IC using a Microchip LDO, P/N MCP1702T- 3302I/MB. This device is in a SOT89 package and in most applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V source. Capacitor C7 (0.1uF ceramic) is one of the decoupling capacitors and should be located directly across each pair of VDD and VSS pins on the IC. The part has a VCAP/VDD CORE pin which is used to decouple the internally generated core voltage. Capacitor C8 is the decoupling capacitor for the core. This decoupling capacitor should be a low ESR ceramic or tantalum capacitor with a value of 4.7 to 10uF. Capacitor C6 is the decoupling capacitor for the analog VDD (AVDD) and it should be located directly across the AVDD and AVSS pins on the IC. Resistor R2 in combination with C6 provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS. Capacitor C2 is the input decoupling capacitor for the LDO and it should be connected directly across the LDO s input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage to the LDO and maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. The Schottky diode D1 prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect D1 during the inrush event associated with the application of the +12Vin. The single pulse peak current rating for a typical BAT54 diode tech.support@psbel.com

7 TRKF-44D42SR 7 is approximately 600mA. If the rise time of the +12V source is slow enough to limit the peak charging current into C1 it is possible to eliminate R1. Assuming a 40mA current draw, C1 will provide approximately 188us of hold up time per uf of capacitance. The 3.0V reference IC provides an accurate external voltage reference for the analog-to-digital converter. The diagrams in Figure 3 show the three most common trim methods used in PoL converters. In all of these schemes a power conversion stage contains a PWM device that receives a control voltage from an error amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value. The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference (Figures 3B and 3C). +Sense +V in Ry Z f TRIM Rx Rz Z i - E/A PWM +V out + Reference Figure 3A +Sense +V in Z f Z i - + E/A PWM +V out TRIM Rx Ry Reference Figure 3B +Sense +V in Z f Z i - E/A Reference + PWM +V out TRIM ucontroller or Equivalent Figure 3C Asia-Pacific Europe, Middle East North America Bel Power Solutions & Protection BCD.00841_AA

8 8 TRKF-44D42SR The most common trim method is shown in Figure 3A. The popularity of this method stems from the fact that most highly integrated PWM control IC s have an internal reference that is not accessible and cannot be controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin through a resistor. Either of these two approaches will move the output voltage to a new value. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease. Some PoL converters incorporate the trim scheme shown in Figure 3B. With this method the feedback ratio is kept constant and the reference value is modified to move the output voltage. The common characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and a larger voltage superimposed on the trim pin will cause Vout to increase. The method shown in Figure 3C is occasionally used. This is similar to the method in Figure 3B except the modification of the reference is mapped through a device such as a microcontroller. This is the least common of the three methods and requires the vendor s data sheet to determine the trim characteristic because the microcontroller can map the reference in many different ways. The power controller has the ability to do independent closed loop trim and closed loop margining of the output voltage for each PoL controlled by the device. Each PoL s output voltage is monitored and by an analog to digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared against the desired value and the PoL s output is adjusted by delivering a trim value to the corresponding PoL s trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital PWM is labeled <Trim PoL n > where n indicates a specific converter which corresponds to the monitoring channel labeled with the same n value. The external low pass filter creates a DC value from the PWM signal which is then delivered to each PoL converter through a range limiting resistor. Figure 4 shows a typical circuit used to interface the controller s trim PWM signals to PoL converters. In this circuit, Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The effective trim voltage is equal to the PWM duty cycle multiplied by VDD (3.3V) and is controllable in 1024 steps from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim voltage ripple. Typical values for Ra and Ca are 1k for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the control range and should be selected based on the desired control range and the trim equation for the PoL. This trim equation is usually available from the PoL manufactures data sheet. The trim direction or logic is configurable for each PoL. The accuracy of the active trim is a function of the ADC accuracy which is mostly controlled by the accuracy of the applied reference to the Vref pins. The Trim PoL PWMs are set to the configured default values before power up begins so that the trim voltage is stable before the PoLs are enabled. Figure 4 The internal ADC channels are converted as 12-bit results with full scale equal to a chosen reference. The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC reference or to use an externally provided reference. Closed loop margining and set point adjustments always use the entire 12-bit result to trim the output voltages to configured values. Monitored voltages are reported via I2C communication using PMBus data formats as defined in the separate communication manual. The voltage range reported is determined by the entered set points. Any of the monitored voltages that are greater than the ADC reference or that can be margined above this reference are required to have a voltage divider to limit the maximum input to the corresponding ADC channel to a value less than or equal to the ADC reference. Monitored voltages below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to filter the ADC results. In most cases this will eliminate the need for external filtering. The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value less than the maximum value of the ADC reference. tech.support@psbel.com

9 TRKF-44D42SR 9 The three primary control interface signals to the attached PoL converters are an enable signal, a voltage monitoring signal, and trim control signal. The enable signals are labeled <Enable PoL n >, the Monitoring signals are labeled <Monitor PoL n >, and the trim signals are labeled <Trim PoL n >. Each n th PoL converter is required to use the corresponding enable, monitor, and trim signals. For example the first PoL converter attached to the controller is PoL 1. PoL 1 should use Enable PoL 1, Monitor PoL 1, and Trim PoL 1. The firmware assumes that the connections are made this way when controlling the system. Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus command set and is defined in a separate communications manual. The communications manual also defines the protocol for device programming via embedded boot loader software. The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus page mode as described in the communications manual. The page assignment is defined in Figure 5. Page 0 I2C Bus I2C Address (configurable) Communication Engine Page Control Not Used Page 1 PoL1 Set Point Scaling Margin Limits PGD/Warning Limits Voltage Reads Page 2 PoL 2 Set Point Scaling Margin Limits PGD/Warning Limits Voltage Reads Page3 PoL 3 Set Point Scaling Margin Limits PGD/Warning Limits Voltage Reads Page 4 PoL 4 Set Point Scaling Margin Limits PGD/Warning Limits Voltage Reads Page 5 Analog A No Set Point Control Scaling PGD/Warning Limits Voltage Reads Page 6 Analog B No Set Point Control Scaling PGD/Warning Limits Voltage Reads Figure 5. Page Assignment Asia-Pacific Europe, Middle East North America Bel Power Solutions & Protection BCD.00841_AA

10 10 TRKF-44D42SR PARAMETER MIN TYP MAX UNITS Ambient temperature under bias C Storage temperature C Voltage on VDD with respect to VSS V Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 VDD+0.3 V Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V V Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V V Voltage on VDDCORE with respect to VSS V Maximum current out of VSS pin 300 ma Maximum current into VDD pin 250 ma Maximum output current sunk by any I/O pin 4 ma Maximum output current sourced by any I/O pin 4 ma Maximum current sunk by all ports 200 ma Maximum current sourced by all ports 200 ma PARAMETER SYMBOL NOTES MIN TYP MAX UNITS Input Voltage Range VDD VDC Input Current IDD Typical is at 3.3V, 25C, 20 MIPS. Max is at 3.3V, 85C, 20 MIPS ma Logic Low Input Level VIL VSS 0.2*VDD VDC Logic High Input Level VIH Non 5V tolerant pins VDD 0.7*VDD 5V tolerant pins 5.5 Logic Low Output Level VOL VDD = 3.3V 0.4 VDC Logic High Output Level VOH VDD = 3.3V, IOH = -3.0mA 2.4 VDC VDD Rise Rate SVDD 0 to 3V in 100ms 0.03 V/ms Capacitance I/O Pin to GND CIO 50 pf I2C Bus Capacitance CB SCL and SDA 400 pf PWM Series Resistor RPWM External Series Resistor 1 k Margin PWM Frequency FPWM 15 khz Reference Input VREF AVSS AVDD VDC Flash Memory Cell Endurance EP 10,000 E/W cycles VDC tech.support@psbel.com

11 TRKF-44D42SR 11 Figure 6. Bel 44-pin 10x10x1mm TQFP Controller 44-LEAD PLASTIC THIN-QUAD FLATPACK, 10 x 10 x 1 MM BODY DIMENSION MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A Molded Package Thickness A Standoff A Foot Length L Footprint L REF Foot Angle Overall Width E BSC Overall Length D BSC Molded Package Width E BSC Molded Package Length D BSC Lead Thickness c Lead Width b Mold Draft Angle Top Mold Draft Angle Bottom Notes: All dimensional units are in millimeters unless otherwise specified. 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Champers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Asia-Pacific Europe, Middle East North America Bel Power Solutions & Protection BCD.00841_AA

12 12 TRKF-44D42SR DATE REVISION CHANGE DETAIL AA First release. Refer to the errata document for additional information specific to each code release. NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice. tech.support@psbel.com