A Ring Architecture Strategy for BIST Test Pattern Generation

Transcription

1 JOURNAL OF ELECTRONIC TESTING: Theory and Applications 19, , 2003 c 2003 Kluwer Academic Publishers. Manufactured in The Netherlands. A Ring Architecture Strategy for BIST Test Pattern Generation C. FAGOT, O. GASCUEL, P. GIRARD AND C. LANDRAULT Laboratoire d Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506 Université Montpellier II/CNRS, 161, rue Ada, Montpellier Cedex 05, France fagot@lirmm.fr gascuel@lirmm.fr girard@lirmm.fr landrault@lirmm.fr Received December 6, 2000; Revised December 3, 2002 Editor: V.K. Agarwal Abstract. This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1]. Keywords: logic BIST, deterministic BIST, pseudo-random testing 1. Introduction BIST for random logic is becoming an attractive alternative in IC testing. Although research on logic BIST has been a hot topic already for over 30 years, the actual use of logic BIST in industry is still limited. However, recent advances in deep-submicron IC process technology and core-based IC design technology will certainly lead to more widespread use of logic BIST since external testing is becoming more and more difficult and costly [2]. This is confirmed by the ITRS (International Technology Roadmap for Semiconductors) statement that by 2014 it may cost more to test a transistor than to manufacture a transistor unless techniques like logic BIST are employed [3]. Modern system chips integrate digital, analog, and memory modules into a single IC. Testing such heterogeneous ICs requires either the use of multiple, dedicated testers or a single, complex tester for testing the digital, analog, and memory parts. The use of logic BIST for the digital modules, analog BIST for the analog modules, and memory BIST for the memory modules, provides that a single, low-cost external tester is sufficient.

2 224 Fagot et al. In order to minimize the cost of BIST, logic BIST is often based on pseudo-random testing. Pseudo-random test stimuli are generated by a simple and low cost LFSR, and the test responses are compressed by a multiple-input signature analyzer (MISR). Unfortunately, pseudo-random patterns cannot guarantee complete fault coverage as the CUT may contain random pattern resistant faults [4]. The fault coverage can be improved by using an enhanced BIST scheme and/or by applying additional external test patterns. Commercial logic BIST tools currently offer to insert test points into the CUT in order to improve its pseudo-random testability [5, 6]. Test point insertion however implies modifications of the CUT. This requires additional silicon area and it may also have a negative impact on the timing behavior if test points are inserted in critical paths. Timing verification after test point insertion is therefore required as an additional task in the design process, and further design iterations may be required to solve timing violations. Furthermore, even test point insertion cannot guarantee complete fault coverage [7]. A straightforward approach to achieve complete fault coverage is to apply additional external patterns which have been generated by ATPG tools to the CUT. However, this approach still requires a considerable amount of external testing. In [8], it has been reported that detecting the last 10% of undetected faults typically requires 70% or more of the test patterns in an ATPG test set. Complete fault coverage without CUT modifications and external test patterns can be achieved by using a BIST scheme containing a more sophisticated pattern generator. Examples of this approach are weighted random pattern generators [9, 10], pseudo-exhaustive pattern generators [11], pseudo-random pattern generators based on reseeding [12, 13], pseudo-random pattern generators using ROMs or counters [14 16], and deterministic pattern generators [17 25]. However, the price for obtaining complete fault coverage usually is a relatively large amount of additional silicon area for the sophisticated pattern generator. This paper presents a new deterministic logic BIST scheme which is highly efficient in terms of silicon area. The basic principle of this BIST scheme is that the sequence of pseudo-random test patterns is modified by embedding deterministic patterns into the sequence to detect random pattern resistant faults missed by the pseudo-random patterns. The pattern generator consists of an LFSR and a small combinational logic, called mapping logic. The mapping logic modifies the pseudo-random patterns provided by the LFSR at certain bit positions through the use of a set of masks configured as a ring. These pattern modifications provide that additional deterministic patterns are generated and complete fault coverage can be guaranteed. During on-chip test pattern generation, each mask is alternatively used to transform the original pattern set. The ring of masks is obtained from a greedy algorithm that uses deterministic test cubes provided by an ATPG tool, together with an intensive use of fault simulation. The ring is first composed of hollow masks in which all the bits are unspecified, and is successively modified until 100% of detectable stuck-at faults are detected by the transformed test sequence. The goal in designing the ring of masks is to determine a limited set of masks with the minimum number of fixed bits needed for the deterministic test cubes to appear in the transformed test sequence. By minimizing the number of fixed bits, the amount of area overhead is minimized. The rest of the paper is organized as follows. In the next section, we give some preliminaries about the ring of masks used in the proposed BIST scheme. The algorithm used to determine the ring of masks is described in Section 3. The complete BIST structure is presented in Section 4. Experiments performed on ISCAS benchmark circuits are presented and discussed in Section Architecture of the Ring of Masks 2.1. Definition of a Mask A mask is a combination of n variables, where n is the number of primary inputs to the CUT. A mask is represented by a vector of {0, 1, x} n where 0 (respectively 1) indicates that the variable has the value 0 (respectively 1) in the mask, and x indicates that the variable has an unspecified value in the mask. The main difference between a test cube, which is a well-known concept in the test domain, and a mask is that a mask acts as a pattern transformer, while a test cube represents a pattern structure from which several patterns can be generated. For example, the two patterns 010 and 000 can be generated from (are contained in) the test cube c = 0x0. Test cubes are usually provided by ATPG tools to target some given stuck-at faults. On the other side, a mask has only to map an

3 A Ring Architecture Strategy for BIST Test Pattern Generation 225 initial test pattern into a new transformed test pattern by modifying (or fixing) the logic value at certain bit positions. For example, the mask m = xx0 applied to the test pattern p = 001 provides the transformed test pattern 000. To complete our example, it can be said that the mask m combined with the pattern p allows the generation of a new test pattern contained in the cube c The Ring Architecture From a general point of view, the ring architecture transforms a sequence of patterns generated by a pseudo-random pattern generator (e.g., an LFSR) into a new test sequence that provides 100% stuck-at fault coverage. More specifically, the ring architecture is composed by a set of masks that are cyclically used to transform patterns of the original pseudo-random test sequence. In the following, S refers to the original pseudo-random test sequence, and S i denotes the ith pattern of S. The ring of masks is denoted as R, and R p represents the pth mask of R. l is the size of R, i.e. the number of masks belonging to R. The cyclic use of R consists in the modification of S 1 by R 1, S 2 by R 2,...,S l by R l, S l+1 by R 1 again, S l+2 by R 2 and so on until the end of S. More formally, each test pattern S i of S is transformed by the mask R i(mod l) of R (the exact mathematical expression would be R (i 1 mod l)+1, but has been simplified for the reader s convenience). By using such a ring of masks, a fixed bit (0 or 1) in R i(mod l) changes the corresponding bit in S i. The transformed pattern sequence is denoted as T and the ith pattern in T is denoted as T i. An example of ring architecture is given in Fig. 1. The size of the ring R is l = 3 and the number of bits in each R i is n = 4. The transformed test pattern T 2 = 0101 is obtained by applying the mask R 2 = 0xx1 on the original test pattern S 2 = 1101, T 4 = 1111 is obtained by applying R 1 = x1xx on S 4 = 1011,.. and so on. Note that in this example, the third and sixth patterns of the original test sequence are let unmodified in the final test sequence simply because mask R 3 is a fully hollow mask. Fig. 1. Example of a ring architecture. An important feature of the ring architecture is that the set S Ri S of test patterns modified by the mask R i can easily be determined. Hence, after a change in mask R i, it is possible to calculate the fault coverage of the transformed test sequence without simulating the complete test sequence. In this case, only patterns in S Ri are needed to be simulated. 3. Algorithm for Determining the Ring of Masks Given a pseudo-random pattern generator, e.g., an LFSR, a test length and a set of test cubes provided by an ATPG tool, an algorithm is described in this section for finding a ring of masks that covers the same set of faults F than that of an ATPG test sequence, i.e., usually 100% of detectable stuck-at faults of the CUT Overview of the Algorithm The steps in the algorithm can be summarized as follows: 1. Choose the seed of the LFSR. 2. Generate the original pattern sequence and evaluate its fault coverage. 3. Set l = Construct a ring composed of l masks Start with a ring composed of l hollow masks Determine the set of the most promising changes Simulate the fault coverage of the ring for each change separately Choose the best change; if the fault coverage is 100% or if it is not increased then stop, else go to step If the fault coverage is 100%, then stop, else l = l + 1 and go to step Construction of a l-ring of Masks The method described in this section to construct a ring composed of l masks, called a l-ring, utilizes a pseudorandom test sequence S and a set C of deterministic test cubes obtained from an ATPG. This method is based on a greedy algorithm, which starts from a ring composed of l hollow masks (all the bits in the masks are unspecified), and successively refines these masks by fixing some bit values in such a way that the fault coverage

4 226 Fagot et al. Fig. 2. Refinement of a 3-ring of masks. of the transformed pattern sequence T is increased. At each step of the refinement process, only one mask is modified. Each change in the ring is denoted as R(p, b), with p being the position of the mask which is modified in R, and b representing the bits modified in mask R p. T t denotes the transformed pattern sequence produced at step t of the iterative process, and F t is the set of faults in F that are not detected by T t. For example, let us consider the 3-ring shown in Fig. 2, and assume an original pattern sequence S that achieves 89% stuck-at fault coverage. At the beginning of the refinement process (step 1 in Fig. 2), the ring is composed of hollow masks and the transformed pattern sequence T is equal to S. During the next step of the process, several assignments (0 or 1) are made on each mask and are evaluated separately. After a number of iterations, the first bit of R 2 is fixed to 0, thus allowing the transformed pattern sequence to reach 93% stuck-at fault coverage (step 2 in Fig. 2). This process continues until all the faults in F are covered by the final transformed pattern sequence (step 4 in Fig. 2). Two comments can be made about the refinement of R in this example. The first one is that the second change in mask R 2, which is performed at step 4 in Fig. 2, is compatible with the first change performed at step 2 in the sense that: (i) it does not modify the bit fixing carried out at step 2, (ii) the deterministic test cubes that appeared in the transformed pattern sequence after the first change still appear after the second one. The second comment is that a mask is modified only if the change provides an increase of the fault coverage Refinement of a l-ring of Masks The basic idea for refining a l-ring of masks is as follows. At step t, the test cube c C that detects the hardest-to-detect faults among those of F t is first selected. The hardest-to-detect faults are determined according to the method described in Section 3.4. Next, we search in T t the pattern that exhibits the smallest bit difference with c. Let Ti t be this pattern, with i p mod l. So, it follows that the easiest mask to modify for c to appear in the next transformed pattern sequence T t+1 is in position p. Therefore, the change in R p will consist in fixing the bit positions that have different values in c and Ti t, provided that this change is compatible with the changes previously made in R p. Moreover: 1. It may happen that more than one test cube detect the hardest-to-detect faults of F t. Therefore, during the refinement process, the ring can be modified by a set of test cubes C t C, and not only by a single test cube c. 2. For each test cube c C t, several patterns in T t may have the same bit difference with c, thus allowing several possible modifications in R for c to appear in T t+1. From the above description of the refinement procedure, it follows that most of the time one can select the change to apply in R among a set of candidates. Each of these candidates guarantees that the next transformed pattern sequence will detect a given number of new hard-to-detect faults, and that bits previously fixed in R will not be modified. However, an important side effect is that when a mask R p of R has been modified, the set of faults detected by T t+1 and not by T t is never the same than the set of faults detected by the test cube c used to modify R p. This is due to the fact that not only Ti t is modified in the transformed pattern sequence, but also all the patterns in position j p mod l. The set of faults detected by T t+1 and not by T t always contains the faults detected by c, but may also contain some other faults detected by patterns in position p other than Ti t. Therefore, the fault coverage achieved by T t+1 may increase, decrease or remain the same than that obtained with T t. Determining the best candidate for a change R is therefore performed resorting to fault simulation of all the patterns modified by R p Determining the Hardest-to-Detect Faults A simple method has been used to determine the hardest-to-detect faults in each circuit. This method is presented in the following. Usually, the number of patterns that detect a given stuck-at fault is very different from one fault to another, and it is commonly accepted that the higher is the number of pseudo-random patterns that detect a fault, the easier is the fault to be detected. The way to determine

5 A Ring Architecture Strategy for BIST Test Pattern Generation 227 the hardest-to-detect faults utilized at the beginning of the refinement process consists first in estimating the hardness δ f of each fault f. The hardness of a fault is a measure of the difficulty in detecting this fault with pseudo-random patterns. Let C f be the set of test cubes of C detecting the fault f. Let c be a cube of C f and c be the number of specified bits in c. A simple estimation of the hardness δ f of a fault f can hence be obtained from δ f = min { c, c C f }, which comes from the observation that a cube with a small number of specified bits will be more likely to detect a fault than a cube with a higher number of specified bits. This measure is simple and representative of the difficulty in detecting a fault. The only drawback is that the hardness of a fault can be overestimated by this measure. On the other side, it cannot be underestimated (a hard-to-detect fault cannot be considered as easy-to-detect) simply because it is not possible for a hard-to-detect fault to have a cube c with a small number of specified bits. After the hardness of each fault has been calculated, the set of hardest-to-detect faults can be easily constructed by taking the faults having a value of δ f greater than a given threshold. Similarly, calculating the quality Q c of a test cube c, which represents its capability in detecting a lot of hard-to-detect faults, is obtained by summing the hardness of faults that it detects Finding a Good LFSR Seed From our experiments, we observed that the performance of the method strongly depends on the pseudorandom sequence S used to generate the test sequence T. In our approach, a good sequence S ofagiven test length is a sequence composed of patterns which are very close to the highest quality test cubes of C. To measure the quality of a sequence S at the beginning of the overall process, we use the function (S) = c C [d(s,c)ln(q c)], where d(s,c) is the minimum Hamming distance between c and any pattern of S. A good sequence is a sequence with a high value of the function (S). To find a good sequence, we start from a randomly chosen seed, and we successively consider as candidate seeds the patterns that appear in the sequence generated by the LFSR (from this seed). To efficiently evaluate each candidate sequence (seed), we only consider at each step the disappearance of the seed of the previous sequence and the appearance of a new final pattern (the test length is the same for each candidate sequence). By this way, we tested 100,000 candidate seeds for each circuit. The seed finally selected for each circuit is the one that produces a sequence S with the highest value of the function (S). The highest CPU time (about 15 ) was observed for circuit s641, while small circuits require only few seconds. Note that a recent development of this technique, which is presented in [26], significantly reduces the size of the l-ring of masks. 4. Hardware Implementation After the ring of masks has been determined such that the test length and fault coverage requirements are satisfied, an implementation of the deterministic BIST scheme can be performed. As in any BIST hardware implementation, the main objective is to implement the test generator with a low cost of area overhead. In the proposed BIST scheme, no storage of deterministic patterns, seeds, characteristic polynomials, or weight sets is required. As illustrated in Fig. 3, a purely combinational logic block is added between the test pattern generator and the CUT so as to map the original sequence of patterns into a transformed sequence of patterns that achieves 100% stuck-at fault coverage. The use of such a low-cost mapping logic is allowed because the number of masks required for test pattern generation in each circuit is always very low (see results in Section 5). A key issue in such a BIST scheme is to design the mapping logic so that it requires a minimum number of gates. This is accomplished as explained below. Note that the pattern generator we use in our BIST scheme is a classical primitive polynomial LFSR in which the number of stages is equal to the number of inputs of the CUT. The mapping logic has inputs coming from the pattern generator and outputs connected to the CUT. A mask selecting circuit is also connected to the mapping logic to allow switching from a mask to another during the BIST session. As each mask has to be active Fig. 3. LFSR MappingLogic Circuit Under Test Mask selecting circuit CLK Block diagram of the pattern generating circuit.

6 228 Fagot et al. during one clock cycle only, the mask selecting circuit is simply a looped shift register in which a walking 1 activates each mask one at a time. The number of D flip-flops in the looped shift register is given by the number of masks in the mapping logic, except in the case of a ring composed of two masks where only one D flip-flop working in the toggle mode is needed. Let us now describe with an example the way to implement the mapping logic from a given set of masks. Assume a ring composed of three masks (R 0, R 1, R 2 ) = {(1xxxx), (xx0x1), (0x0xx)} determined according to the process described in the previous section. During the BIST session, each one of them is active during one clock cycle only. It is therefore applied on a single pattern provided by the LFSR during this clock cycle. When a mask is active, the value 1 is forced at the corresponding output of the mask selecting circuit that feeds the mapping logic. The other outputs remain at 0 until the next clock pulse occurs. In our example, when mask 1 is active, only the first bit of the pseudo-random pattern provided by the LFSR has to be fixed at 1. The other bits remain unspecified. Therefore, only an OR gate on the first output of the LFSR is needed to implement mask 1. When mask 2 is activated in the next clock cycle, two bits have to be fixed at a specified value: the third bit must take the value 0 while a 1 is required on the fifth bit position. This is accomplished by placing a NOR gate with an inverting input on the third output of the LFSR and an OR gate on the fifth output of the LFSR. The inverting input on the NOR gate allows the value provided by the LFSR to be unchanged when mask 2 and mask 3 are inactive. The same reasoning is applied to implement mask 3 in which a 0 has to be fixedonthefirst and third bit positions. The internal structure of the mapping logic for this example is depicted in Fig. 4, highlighting the small number of gates that is needed for the ring implementation. Fig. 4. Design example of the mapping logic. An obvious concern about inserting gates between the pattern generator and the CUT is that the delay through the circuit can be a problem. As in [18], a simple solution to alleviate this problem is to bypass the mapping logic during the normal mode of operation by using multiplexers. Of course in this case the problem would be to test faults in the system path from the multiplexer to the CUT. Providing a solution to this problem is difficult in the context of test-per-clock BIST. But a possible solution would be to adapt the proposed BIST technique to scan-based BIST so that the multiplexing of the LFSR outputs is not necessary. Another concern about using such a mapping logic between the pattern generator and the CUT is that stuck-at faults in this mapping logic have also to be tested. This can be performed very easily by the patterns generated during BIST since the mapping logic is a simple combinational structure with a small number of logic levels. 5. Experimental Results Experimental evaluation of the proposed method was conducted using the standard sets of ISCAS 85 and ISCAS 89 circuits [27, 28]. It was assumed that the flip-flops in the ISCAS 89 circuits were configured as part of the LFSR during testing so that the circuits are tested like combinational circuits. Rings of masks were constructed as described in Section 3. Fault simulations in each circuit were performed using a home fault simulation tool based on the critical path tracing algorithm proposed in [29]. Deterministic test cubes from which a ring of masks is built were generated using the ATPG tool TestGen of Synopsys [30]. In the Table 1, the results obtained from the proposed BIST scheme are compared first with those of a pure pseudo-random BIST scheme using only an LFSR, and next with those of the rectangle mapping method presented in [18]. The first and second columns contain the circuit name and the number of detectable faults (#faults) in each circuit respectively. The next column (LFSR alone) reports the test length required to achieve 100% stuck-at fault coverage with a test sequence generated from a classical LFSR (with a random seed). The three following columns contain the results obtained with our proposed deterministic BIST scheme. Column 4 contains the number of gates required to implement the mapping logic and the shift register (#GE). This number is expressed in terms of gate equivalents (GE), in which (0.5)(n) GE is counted for an n-input

7 A Ring Architecture Strategy for BIST Test Pattern Generation 229 Table 1. Results for the proposed BIST scheme. LFSR + Mapping Logic CIRCUIT LFSR alone and Shift Register Touba & McC. [18] Name #Faults #Patterns #GE #Masks #Patterns #GE c K K 27 c K K 11 c K K 12 c M K 121 c K K 13 c >100 M K 256 s s s s s s K s M K 28 s s s >100 K K s M K 12 s >100 K K s >100 K K s >100 K K s >100 K K s >100 K K s >100 M K s >100 K K s K s K s M K NAND or NOR gate, (0.75)(n) for a n-input AND or OR gate, (0.5) GE for a NOT gate, (2.5)(n 1) GE for a n-input XOR gate and 4 GE for a flip-flop. The next column (#Masks) gives the number of masks in the ring, and corresponds to the number of flip-flops contained in the looped shift register that acts as mask selecting circuit (except for rings composed of two masks that require only one flip-flop). The sixth column in Table 1 lists the number of test patterns needed to achieve 100% fault coverage with the proposed deterministic BIST technique. The last column contains the results of [18] (in terms of GE) for some circuits (the other results are not available), with a test length equal to the test length used in our method and reported in column 6. Note that these results are those reported in [18]. These results indicate that the use of a low cost mapping logic can dramatically reduce the pseudo-random pattern test length compared with a pure pseudorandom BIST scheme. One of the most significant example of this reduction has been obtained on circuit s713, for which only 13 GEs are needed to reduce the test sequence length from more than 100 millions to no more than 10 K. In many cases, the results are even better since no additional hardware is required to reduce the pseudo-random pattern test length. In these cases, the reduction comes from an adequate selection of the LFSR seed. Note that the results in Table 1 can be

8 230 Fagot et al. further improved by using the seed selection heuristic presented in [26]. By using this heuristic, some circuits no more need additional hardware (e.g. c1908) and the area overhead is reduced by 20% on average for all benchmark circuits. Another advantage of the proposed approach is that it is very easy to trade-off between test length (test time) and area overhead. For example, it is reported in Table 1 that the maximum fault coverage for circuit s820 can be achieved with 5 K patterns using only 8.5 GE. With a test sequence length of 10 K, the number of gate equivalents for this circuit can be divided by 4 for the same target fault coverage (100%). Finally, Table 1 shows that results obtained with the ring architecture are as good as those obtained by the rectangle mapping method described in [18]. By looking at the results available in [18], our architecture provides better results for three benchmark circuits, worst results for two of them, and equivalent results for three of them. There is no comparison for other circuits because we were unable to efficiently implement the rectangle mapping method and reproduce the available results. The main advantage of our method compared with that of [18] is that it does not need any logic synthesis tool to create an efficient low cost BIST architecture. Thus, the area of the ring architecture does not depend on the quality of such tool. 6. Conclusion In this paper, we presented a new deterministic logic BIST scheme. The basic principle of this BIST scheme is that a sequence of pseudo-random test patterns is modified by embedding deterministic test cubes into the sequence to detect random pattern resistant faults missed by the pseudo-random patterns. The pattern generator consists of an LFSR and a small combinational logic, called mapping logic. The mapping logic modifies the pseudo-random patterns provided by the LFSR at certain bit positions through the use of a set of masks configured as a ring. These pattern modifications provide that additional deterministic patterns are generated and complete fault coverage can be guaranteed. To construct the ring architecture, a simple and effective algorithm has been proposed, and experimental results given at the end of the paper demonstrate the effectiveness of this algorithm in terms of silicon area and test quality. One way to improve the results presented in this paper could be to use a biased ring architecture that combines the advantages of the proposed technique with those of weighted-random and reseeding techniques. Another possible extension of this work could be to target detection of faults other than stuck-at faults, e.g. delay faults or bridging faults. For related work that has appeared since the completion of the research reported in this paper, we refer the reader to the paper by Wang [31]. Acknowledgments The authors would like to thank L. Brehelin and G. Caraux from the LIRMM for their help on the implementation of the method and for constructive discussions about the ring architecture strategy. References 1. C. Fagot, O. Gascuel, P. Girard, and C. Landrault, A Ring Architecture Strategy for BIST Test Pattern Generation, IEEE Asian Test Symposium, pp , Y. Zorian, Testing the Monster Chip, IEEE Spectrum, pp , July Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 1999 edition. 4. E.B. Eichelberger and E. Lindbloom, Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test, IBM Journal of Research and Development, vol. 27, no. 3, pp , J.P. Hayes and A.D. Friedman, Test Point Placement to Simplify Fault Detection, IEEE Trans. on Computers, vol. C-33, pp , July N. Tamarapalli and J. Rajski, Constructive Multi-Phase Test Point Insertion for Scan-Based BIST, in IEEE International Test Conference, 1996, pp G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, and J. Rajski, Logic BIST for Large Industrial Designs: Real Issues and Case Studies, in IEEE International Test Conference, 1999, pp R.W. Bassett et al., Low Cost Testing of High Density Logic Components, in IEEE International Test Conference, 1989, pp H.J. Wunderlich, Self Test Using Unequiprobable Random Patterns, in IEEE International Symposium on Fault-Tolerant Computing, 1987, pp F. Brglez et al., Hardware-Based Weighted Random Pattern Generation for Boundary-Scan, in IEEE International Test Conference, 1989, pp S. Hellebrand, H.J. Wunderlich, and O.F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing, in IEEE International Test Conference, 1990, pp B. Koenemann, LFSR-Coded Test Patterns for Scan Designs, IEEE European Test Conference, 1991, pp S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns Through Reseeding of Multiple-Polynomial

9 A Ring Architecture Strategy for BIST Test Pattern Generation 231 Linear Feedback Shift Registers, in IEEE International Test Conference, 1992, pp G. Edirisooriya and J.P. Robinson, Design of Low Cost ROM Based Test Generators, in IEEE VLSI Test Symposium, 1992, pp C. Dufaza, H. Viallon, and C. Chevalier, BIST Hardware Generator for Mixed Testing Scheme, in IEEE European Design & Test Conference, 1995, pp D. Kangaris and S. Tragoudas, Generating Deterministic Unordered Test Patterns with Counter, in IEEE VLSI Test Symposium, 1996, pp M. Chatterjee and D.K. Pradhan, A Novel Pattern Generator for Near-Perfect Fault Coverage, in IEEE VLSI Test Symposium, 1995, pp N.A. Touba and E.J. McCluskey, Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST, in IEEE International Test Conference, 1995, pp S. Hellebrand, B. Reeb, S. Tarnick, and H.J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, in IEEE International Conference on Computer-Aided Design, 1995, pp N.A. Touba and E.J. McCluskey, Altering a Pseudo-Random Bit Sequence for Scan-Based BIST, in IEEE International Test Conference, 1996, pp H.J. Wunderlich and G. Kiefer, Bit-Flipping BIST, in IEEE International Conference on Computer-Aided Design, 1996, pp C. Fagot, P. Girard, and C. Landrault, On Using Machine Learning for Logic BIST, in IEEE International Test Conference, 1997, pp G. Kiefer and H.J. Wunderlich, Deterministic BIST with Multiple Scan Chains, in IEEE International Test Conference, 1998, pp G. Kiefer and H.J. Wunderlich, Deterministic BIST with Partial Scan, IEEE European Test Workshop, pp , G. Kiefer, H. Vranken, E.J. Marinissen, and H.J. Wunderlich, Application of Deterministic Logic BIST on Industrials Circuits, in IEEE International Test Conference, 2000, pp C. Fagot, O. Gascuel, P. Girard, and C. Landrault, On Calculating Efficient LFSR Seeds for Built-In Self Test, IEEE European Test Workshop, pp. 7 14, F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran, in IEEE International Symposium on Circuits and Systems, 1985, pp F. Brglez, D. Bryant, and K. Kozminski, Combinational Profiles of Sequential Benchmark Circuits, in IEEE International Symposium on Circuits and Systems, 1989, pp M. Abramovici, P.R. Menon, and D.T. Miller, Critical Path Tracing: An Alternative to Fault Simulation, in IEEE Design & Test of Computers, vol. 1, no. 1, Feb TestGen, version Tg4.1, User Guide, Synopsys Inc., S. Wang, Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST, in IEEE International Test Conference, 2001, pp Christophe Fagot obtained the Ph.D. degree in Computer Science from the University of Montpellier in January During his Ph.D., he worked under the supervision of Olivier Gascuel and Patrick Girard. His research subject was on the design of efficient algorithms to generate and improve test sequences for BIST. This involves both the work presented in this paper, and the search for efficient seeds for pseudo-random testing. He is now working in the research department of ST Microelectronics, Grenoble, France. Olivier Gascuel is presently Research Director at CNRS and co-head of the Computer Science Department at LIRMM. He is computer scientist and statistician. His main domains of interest are data analysis, machine learning, classification and algorithmic. He is the head of the Methods and Algorithms for Sequence Analysis team at LIRMM. Most of the applications dealt with by this team are related to sequences. These are mainly genetic sequences, but also textual data and test sequences for VLSI circuits. Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics et Microelectronics of Montpellier-France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing, and low power testing. He has authored and co-authored more than 90 papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European research projects (Esprit ATSEC, Eureka MEDEA, MEDEA + ASSOCIATE, IST MARLOW). Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in Christian Landrault was born in Orléans (France) on December 8, He has held a degree in aeronautical engineering from Ecole Nationale d Ingénieurs de Constructions Aéronautiques, Toulouse in From 1970 to 1980, he worked at Laboratoire d Automatique et d Analyse des Systèmes (LAAS, Toulouse) on self checking circuits, dependability architecture and dependability evaluation of digital systems. In 1980, he joined the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM). He is presently Research Director at CNRS and co-director of the LIRMM. He works mainly in testing. He has held the Docteur- Ingénieur degree in 1973 and the Docteur d Etat degree in 1977 both from the LAAS in Toulouse. He has published over 100 papers in journals and conference, he has participated to 25 research contracts and has managed 18 of them. He serves on the Editorial Board of JETTA.