TDA8921TH class-d audio amplifier 2 x 50W single chip

Transcription

1 file: /user/nybuiten/n760/specificatie/tds89nf.fm mei 09, 00 Tentative specification class-d audio amplifier x 50W single chip. General description The TDA89 is an high efficiency class-d audio power amplifier system. Typical output power is x 50 W and it operates with high efficiency and very low dissipation. The devices comes in a HSOP4 power package with a small internal heatsink. No external heatsink is required, or depending on supply voltage and load a very small one. The system operates over a wide supply voltage range from +5 up to =+30 V and consumes a very low quiescent current.. Features - High efficiency (>90%) - Operating voltage from +5 V to + 30V - Very low quiescent current - Low distortion - Fixed gain of 30 db in Single Ended and 36 db in BTL - High output power - Good ripple rejection - Internal switching frequency can be overruled by an external clock - No switch-on or switch-off plop noise - Short-circuit proof across the load - Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied Load (BTL) - Electrostatic discharge protection (pin to pin) - Thermally protected 3. Applications - Television sets - Home-sound sets - Multimedia systems - All mains fed audio systems - Car audio (boosters) 4. Quick reference data SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General, V p = + 5V V p operating supply voltage V I q(tot) total quiescent current ma η efficiency P o =30W % Stereo single-ended configuration P o output power, R LOAD = 8 ohm THD = 0%, Vp= + 5 V W P o output power, R LOAD = 4 ohm THD = 0%, Vp= + V W G v closed loop voltage gain db Z i input impedance kω V n(o) noise output voltage µv SVRR supply voltage ripple rejection db α cs channel separation db Vo DC output offset voltage 0 50 mv Tentative specification

2 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Mono Bridge-Tied load configuration P o output power, R LOAD = 8 ohm THD = 0%, Vp= + V W G v closed loop voltage gain db Z i input impedance kω V n(o) noise output voltage µv SVRR supply voltage ripple rejection - 44 db Vo DC output offset voltage 0 00 mv 5. Ordering information TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION HSOP4 heatsink small outline package; 4 leads SOT566BBC Tentative specification

3 6. Block diagram digital power stage VDDA VDDA VDDP VDDP BOOT IN+ 9 + IN- 8 ANALOG - DIGITAL 6 OUT SGND PROT 3 PROTECTION STABILIZER 8 STABI VDD BOOT SGND IN- 5 - IN+ 4 ANALOG + DIGITAL OUT MODE 6 MODE OSCILLATOR VSSA VSSA OSC VSSD VSSP VSSP SUB Figure Block diagram VSSA 4 VSSD SGND. 3 VDDP VDDA 3 BOOT IN+ 4 OUT IN- 5 0 VSSP MODE OSC SUB STABI IN- 8 7 VSSP IN+ 9 6 OUT VDDA 0 5 BOOT SGND. 4 VDDP VSSA 3 PROT Figure Pin configuration Tentative specification 3

4 7. Pinning SYMBOL PIN DESCRIPTION VSSA Negative analog supply channel SGND Signal ground channel VDDA 3 Positive analog supply channel IN+ 4 Positive audio input channel IN- 5 Negative audio input channel MODE 6 Mode select input (standby/mute/operating) OSC 7 Oscillator frequency adjustment, or tracking input IN- 8 Negative audio input channel IN+ 9 Positive audio input channel VDDA 0 Positive analog supply channel SGND Signal ground channel VSSA Negative analog supply channel PROT 3 Time constant capacitor for protection delay VDDP 4 Positive power supply channel BOOT 5 Bootstrap capacitor channel OUT 6 PWM output channel VSSP 7 Negative power supply channel STABI 8 Decoupling internal stabilizer for logic supply SUB 9 Substrate, must be connected to negative supply VSSP 0 Negative power supply channel OUT PWM output channel BOOT Bootstrap capacitor channel VDDP 3 Positive power supply channel VSSD 4 Negative digital supply Tentative specification 4

5 8. Functional description The is a two channel audio power amplifier system using the class-d technology. In the analog controller part the analog audio input signal is converted into a digital PWM signal. For driving the low pass filter and the loudspeaker load a digital power stage is used. It performs a level shift from the low power digital PWM signal at logic levels to a high power PWM signal switching between the main supply lines. A second order low pass filter converts the PWM signal to an analog audio signal across the loudspeaker. Digital power stage It contains the high power D-MOS switches, the drivers, timing and handshaking between the power switches and some control logic. For protection a temperature sensor and a maximum current detector is on the chip. Analog low power controller For the two audio channels it contains two pulse width modulators (PWM), two analog feedback loops and two differential input stages. Furthermore it contains circuits common to both channels like the oscillator, all reference sources, the mode functionality and a digital timing manager. Using this chip an audio system with two independent amplifier channels with high output power, high efficiency (90%), low distortion and a low quiescent current is obtained. The amplifiers channels can be connected in the following configurations: - Mono bridge-tied load (BTL) amplifier - Stereo single-ended (SE) amplifiers. The amplifier system can be switched in three operating modes with the MODE select pin: - Standby mode, with a very low supply current. - Mute mode, the amplifiers are operational, but the audio signal at the output is suppressed. - Operating mode (amplifier fully operational) with output signal. For suppressing pop noise the amplifier will remain automatically for approx. 0ms in the mute mode before switching to operating. In this time the coupling capacitors at the input are fully charged. See fig. 5 for an example of a switching circuit for driving the mode pin. Pulse Width Modulation (PWM) frequency The output signal of the amplifier is a PWM signal with a carrier frequency of approx. 350 khz. Using a second order LC demodulation filter in the application results in an analog audio signal across the loudspeaker. This switching frequency is fixed by an external resistor R OSC connected between pin OSC and VSS. With the resistor value given in the schematic of the reference design, the carrier frequency is typical 350 khz. The carrier frequency can be calculated using: f osc = 9 x 0 9 / R osc [Hz] If two or more class-d systems are used in the same audio application, it is advised to have all devices working at the same switching frequency. This can Figure 3. Mode select circuit be realized by connecting all OSC pins together and feed them from a external central oscillator. Using an external oscillator it is necessary to force the OSC pin to a DC-level above SGND for switching form internal to external oscillator. In this case the internal oscillator is disabled and the PWM will be switching on the external frequency.the frequency range of the external oscillator must be in the range as specified in the switching characteristics. Application in a practical circuit: Internal oscillator: R osc connected from OSC pin to V SS external oscillator: connect oscillator signal between OSC pin and SGND pin; delete R osc +5V standby/ mute R R mute/on MODE pin SGND Tentative specification 5

6 Protections Temperature-, supply voltage- and short circuit protections sensors are included on the chip. In case of exceeding the maximum current or maximum temperature the system shuts down. The protection is activated in case of:. Over-temperature If the junction temperature (Tj) exceeds 50 C, then the power stage shuts down immediately. The power stage starts switching again if the temperature is dropped to approx. 30 o C, so there is a hysteresis of approx. 0 C.. Short-circuit across the loudspeaker terminals: When the loudspeaker terminals are short-circuited it will be detected by the current protection. If the output current exceeds the maximum output current of 5 Amp, then the power stage shuts down within less thanµs and the high current is switched off. In this state the dissipation is very low. Every 0ms the system tries to restart again. If there is still a short across the loudspeaker load, the system is switched off again as soon as the maximum current is exceeded.the average dissipation will be low because of this low duty cycle. 3. Start-up safety test During the start-up sequence, when the mode pin is switched from standby to mute, the condition at the output terminals of the power stage are checked. In case of a short of one of the output terminals to V DD or V SS the start-up procedure is interrupted and the systems waits for un-shorted outputs. Because the test is done before enabling the power stages, no large currents can be flowing in case of a short circuit. This system protects for shorts at both sides of the output filter to both supply lines. When there is a short from the power PWM output of the power stage to one of the supply lines - so before the demodulation filter - it will also be detected by the start-up safety test. Practical use from this test feature can be found in detection of shorts on the pcb. Remark: this test is only operational prior or during the start-up sequence, so not during normal operation. 4. Supply voltage alarm If the supply voltage goes below the value of +.5V the under voltage protection is activated and system shuts down correctly and silently without plopnoises. When the supply voltage comes above the threshold the system is restarted again after 0ms. If the supply voltage exceeds + 3V the overvoltage protection is activated and the power stages shuts down. They are enabled again as soon as the supply voltage drops down the threshold. Additional there is balance protection which compares the positive (Vdd) and the negative (Vss) supply voltages and triggers if the voltage difference between them exceeds a certain level. This level is dependent on the sum of both supply voltages. Example: the protection is triggered if Vdd = +5V and Vss = -30V. Differential audio inputs For a high common mode rejection and a maximum of flexibility of application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the channels is inverted, so that a load can be connected between the two output filters. In this case the system operates as a mono BTL amplifier and with the same loudspeaker impedance a four times higher output power can be obtained. For more information see the application information. Also in the stereo single ended configuration it is recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies. Vin IN+ IN+ OUT Sgnd IN- IN- OUT power stage Figure 4 Mono BTL application Tentative specification 6

7 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 34). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V p supply voltage +30 V V ms mode select switch voltage with respect to 5.5 V SGND V sc short circuit voltage of output pins +30 V I ORM repetitive peak current in output pin 5 A T stg storage temperature C T amb operating ambient temperature C T vj virtual junction temperature 50 C 0. Thermal characteristics SYMBOL PARAMETER CONDITIONS VALUE UNIT R th(j-a) thermal resistance from junction to ambient in free air 40 K/W R th(j-c thermal resistance from junction to case *) K/W *) Under investigation Tentative specification 7

8 V th V th+ V th V th+ MGR66 Philips Semiconductors. Static characteristics V p = +5 V; T amb =5 C; measured in Fig. 8; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply V p supply voltage range () V I q quiescent current no load connected ma I stb standby current µa Mode select pin; see Fig. 5 V ms input voltage range () V I ms input current V ms = 5.5 V µa V th+ threshold voltage standby mute; () V V th threshold voltage mute standby; () V V ms H hysteresis (V th+ ) (V th ) mv V th+ threshold voltage mute on; () V V th threshold voltage on mute; () V V ms H hysteresis (V th+ ) (V th ) mv Audio input pins V in DC DC input level () 0 V Amplifier outputs V OO output offset voltage on and mute () mv V OO delta output offset voltage on mute () mv Stabilizer V V stabi Stabilizer output voltage mute and operating (3) 3 5 V I stabi max Stabilizer max. output current mute and operating 0 ma Notes. The circuit is DC adjusted at V p = +5 to +30 V.. With respect to SGND (0 V). 3. With respect to V SS pagewidth on mute standby V msh V msh Vms Fig. 5 Mode select pin Tentative specification 8

9 . Switching characteristics V p = +5 V; T amb =5 C; measured in Fig. 8; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Switching frequency f osctyp typical oscillator frequency R OSC = 30.0 kohm khz f osctyp typical oscillator frequency R OSC = 7 kohm, see 360 khz reference design f osc oscillator frequency range Note khz V OSC maximum voltage at OSC pin frequency tracking SGND+ V V OSC_trip Triplevel at OSC pin for tracking frequency tracking - SGND+ - V.5 f track frequency range for tracking frequency tracking khz V OSC EXT Amplitude at OSC pin for tracking Note tbf - tbf V PWM output t r rise time output voltage ns t f fall time output voltage ns t blank blanking time ns t min minimal pulse width note ns R ds_on R DS_ON output transistors ohm Note : frequency set with Rosc, according to formula in functional description Note : for tracking the external oscillator has to switch around (SGND+.5V) with a minimum amplitude of V OSC EXT Note 3: The effective minimal pulse width during clipping is t min / For the practical useable minimal and maximal duty cycle which determines the maximum output power: (t min. f osc / ). 00% < duty cycle < ( - (t min. f osc ) / ). 00% Using the typical values: 3.5% < duty cycle < 96.5% /f OSC PWM out Vdd time 0V Vss tr tf t blank Fig. 6 Timing diagram PWM output Tentative specification 9

10 3. Dynamic AC characteristics Single ended application V p = +5 V; R L =8Ω; f i = khz; T amb =5 C; measured in Fig. 9; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT P o output power, R LOAD = 8 ohm V p = +5 V; THD = 0.5% 5 *) 30 - W V p = +5 V; THD = 0% 30 *) 37 - W output power, R LOAD = 4 ohm V p = + V; THD = 0.5% 30 *) 40 - W V p = + V; THD = 0%; 40 *) 50 - W output power, R LOAD = 8 ohm V p = +30 V; THD = 0.5%; W V p = +30 V; THD = 0%; W THD total harmonic distortion P o = W; note f i = khz % f i = 0 khz % G v closed loop voltage gain db η efficiency P o = 30 W; f i = khz; note % SVRR supply voltage ripple rejection on; f i = 00 Hz; note db on; f i = khz; note db mute; f i = 00 Hz; note db standby; f i =00 Hz; note db Z i input impedance kω V n(o) noise output voltage on; R s =0Ω; note µv on; R s =0kΩ; note µv mute; note µv α cs channel separation note db G v channel unbalance - - db V o output signal in mute note µv CMRR common mode rejection ratio V i(cm)(rms) =V db Note *) indirect measurement based on Rds_on measurement Notes. Total Harmonic Distortion is measured in a bandwidth of Hz to khz. When distortion is measured using a lower order lowpass filter a significant higher value will be found, due to the switching frequency outside the audio band.. Output power measured across the loudspeaker load. 3. V ripple =V ripple(max) = V (p-p); f i = 00 Hz; R s =0Ω. 4. V ripple =V ripple(max) = V (p-p); f i = khz; R s =0Ω. 5. B = Hz to khz; R s =0Ω. 6. B = Hz to khz; R s =0kΩ. 7. B = Hz to khz; independent of R s. 8. P o = tbf W; R s =0Ω. 9. V i =V i(max) = V (RMS). Tentative specification 0

11 Mono BTL application V p = + V; f i = khz; T amb =5 C; measured in Fig. tbf; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT P o output power, R LOAD = 8 ohm V p = + V; THD = 0.5% 70 *) 80 - W V p = + V; THD = 0% 80 *) 00 - W THD total harmonic distortion P o = W; note f i = khz % f i = 0 khz % G v closed loop voltage gain db SVRR supply voltage ripple rejection on; f i = 00 Hz; note db on; f i = khz; note db mute; f i = 00 Hz; note db standby; f i =00 Hz; note db Z i input impedance 34 kω V n(o) noise output voltage on; R s =0Ω; note µv on; R s =0kΩ; note µv mute; note µv V o output signal in mute note µv CMRR common mode rejection ratio V i(cm)(rms) =V db Notes. Total Harmonic Distortion is measured in a bandwidth of Hz to khz. When distortion is measured using a low order lowpass filter a significant higher value will be found, due to the switching frequency outside the audio band.. Output power measured across the loudspeaker load. 3. V ripple =V ripple(max) = V (p-p); f i = 00 Hz; R s =0Ω. 4. V ripple =V ripple(max) = V (p-p); f i = khz; R s =0Ω. 5. B = Hz to khz; R s =0Ω. 6. B = Hz to khz; R s =0kΩ. 7. B = Hz to khz; independent of R s. 8. V i =V i(max) = V (RMS). *) indirect measured, based on Rds_on measurement Tentative specification

12 audio switching Vmode 4V operating V 0V(SGND) standby mute 0ms > 0ms time When switching from standby to mute there is a delay of 0ms before the output starts switching. Audio signal is available after the mode pin has been set to operating, but not earlier than 0ms after switching to mute. audio switching Vmode 4V operating When switching from standby to operating there is a first delay of 0ms before the outputs starts switching. After a second delay of 0ms the audio signal is available 0V(SGND) standby 0ms 0ms time Figure 7. Mode pin timing Tentative specification

13 4. Test information To be finished VDDA VDDA VDDP VDDP BOOT IN+ 9 + IN- 8 ANALOG - DIGITAL 6 OUT SGND PROT 3 PROTECTION STABILIZER 8 STABI VDD BOOT SGND IN- 5 - IN+ 4 ANALOG + DIGITAL OUT MODE 6 MODE OSCILLATOR VSSA VSSA OSC VSSD VSSP VSSP SUB Figure 8. Test circuti Tentative specification 3

14 5. Application information Reference design One chip class D application PCB Version Power supply VddA Mode select See note 4 C 47µF/35V + C3 C6 C7 GND C 47µF/35V + C4 C8 Qgnd +5V VDD GND 3-5V VSS Qgnd C40 nf C4 nf See note 5 Qgnd R9 0k R0 9k VddP BEAD L5 BEAD L6 VssP BEAD L8 BEAD L7 VddA GND VssA DZ 5V6 Qgnd GND C5 470nF R5 0k R 39k On Mute Off In R6 0k C9 nf R VssA (pin ) C6 470nF J VSS 39k S See note 6 See note 8 J GND J6 J5 C7 470nF J3 C C R3 7k C3 330pF C4 330pF In Inputs VddA Clock Sgnd C8 470nF R7 0k C0 nf Vmode Sgnd J4 R8 0k Qgnd C5 U TDA890TH TDA89TH HSOP4 9 V C9 VssA 8 3 VssA C 5nF Boot VddP C3 VssP Boot C9 5nF C0 560pF C30 560pF VddP C4 C 560pF R 5R6 Out Out VddP R4 5R6 C3 560pF of at least 63V VssP C5 C6 R5 5R6 in a BTL application R3 5R6 Sumida 33µH CDRH7-330 VssP + C8 500µF/35V C33 470nF Notes C34 C35. SMD capacitors between Vdd, GND and/or Vss supply range 3. C7 and C8 low ESR electrolytic capacitors 4. Mode circuit : R <= (Vdd,min - 5V6) / 00µA L VddP VssP C39 nf Outputs Out+ Out+ Qgnd 8 Ohm BTL Out- Out- Out+ 6. BTL: Remove In, R5, R6, C5, C6 and C3 in BTL and close J5 and J6 8. Inputs floating or inputs referred to Qgnd (close J and J4) or referred to VSS (close J and J3) + Sumida 33µH CDRH7-330 L C3 470nF C7 500µF/35V R6 4 R7 4 C36 nf C37 nf C38 nf. C5, C6, C7 and C8 should be MKT, C9 and C0 are optional 5. R9 and R0 only necessary with an asymmetrical supply 7. Demodulation coils L and L should be matched in BTL Qgnd Qgnd Qgnd Out - GND 4 or 8 Ohm SE 4 or 8 Ohm SE Fig.9 Application circuit for stereo single-ended application Tentative specification 4

15 BTL application For using the system in mono BTL application (for more output power), the inputs of both channels must be connected in parallel. The phase of one the inputs must be inverted. In principle the loudspeaker can be connected between the outputs of the two single-ended demodulation filters. MODE pin For correct operation the switching voltage at the mode pin should be de-bounced. If the mode pin is driven by a mechanical switch an appropriate debouncing low pass filter should be used. If the mode pin is driven by an electronic circuit or micro controller then it should remain for at least 00ms at the mute voltage level (V th+ ) before switching back to the standby voltage level. External clock See Fig. 0 for a external clock oscillator circuit. 5k Fig.0 External oscillator circuit Output power The output power in several applications can be estimated using: for single ended: Pout_% = ( R LOAD. Vp ( - t. min f osc ) ) R LOAD + R DS_ON + R s. R Load the maximum current : Iout^ = Vp ( - t min. f osc ) R LOAD + R DS_ON + R S should not exceed 5 Amp for BTL : Pout_% = ( R LOAD. Vp ( - t. min f osc ) ) R LOAD + (R DS_ON + R s ) the maximum current : Iout^ =. R Load Vp ( - t. min f osc ) R LOAD + (R DS_ON + R S ) should not exceed 5 Amp While: R LOAD =Load impedance Rs =Serie resistance of filter coil Pout_% =Output power just at clipping Pout_0% = Output power at THD = 0% Pout_0% =.5 x Pout_% Tentative specification 5

16 6. Package outline Tentative specification 6