Jitter effects on Analog to Digital and Digital to Analog Converters

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1 Jitter effects on Analog to Digital an Digital to Analog Converters Jitter effects copyright 1999, 2000 Troisi Design Limite

2 Jitter One of the significant problems in igital auio is clock jitter an its impact on a signal integrity in auio chain. While many believe that clock jitter impacts all igital auio signals, it is my contention that clock jitter affects the signal only uring the conversion process. Analog to igital an igital to analog converters are susceptible to clock jitter an can exhibit egrae performance with even small amounts of jitter. eyon this realm the funamental tenants of igital clocking rener small variations in clock transition times relatively harmless, that is until they begin to fall outsie clock-ata setup an hol times. How much is too much jitter? or a 24 bit quantize signal jitter greater than 3 5 pico-secons can measurably egrae the performance of a converter. While this seems like a very small amount (it is) many of toay s proucts provie systems with clock jitter approaching this range. Another point to consier is that most 24-bit converters actually operate in the theoretical bit range thus relaxing, by a small amount, the nee for increasingly smaller jitter amplitues. What Is Clock Jitter? Digital circuits operate from a master clock that is use to erive sequencing an control the work or computations they are esigne for. In igital auio these clocks are part of the analog to igital (ADC) an igital to analog (DAC) conversion process. These clocks are typically not perfect with respect to their V u 4.5u 5u 5.5u sec igure 1 Transition eges showing jitter transitions an will isplay minute variations over time. igure 1 shows a graph of multiple clock transitions superimpose over time (calle an eye pattern). Note how the transition eges o not all coincie with each other but cause a fairly wie ban at each transition point. This is (one form of) jitter, a relatively large amount of jitter, cause by noise in the oscillator circuitry of an inexpensive function generator. The analog to igital process relies upon a sample clock to inicate when a sample or snap shot of the analog signal will be taken. In orer to accurately represent the analog ata the sample clock must be evenly space in time. Any eviation will result in a istortion of the igitization process. Note too that the sensitivity to variations in the sampling interval is greatest uring the times when the analog signal has the greatest change in voltage with respect to time. or example, in figure 2, assume the vertical lines, space at 2uec intervals are the sample times. A small eviation of the sample clock at the negative peak (re line) of the sine wave will yiel a smaller error signal or ifference in the sample value than a similar variation at the rising or falling ege of the sine wave. The ifference between the two sample points at the rising ege of the sine wave yiels a significantly ifferent value in the sample ata. We can conclue that a given amount of clock jitter has a greater effect as the signal amplitue an frequency increase since in both cases the change in unit time of the signal is greater with high level, high frequency signals. Therefor jitter has less effect on low level, low frequency signals, an more affect on high level, high frequency signals. Jitter effects copyright 1999, 2000 Troisi Design Limite

3 It s important to note that jitter in the sample clock is etrimental since once an analog signal is converte it s virtually impossible recreate the small timing variations in such a way as to reassemble the igital signal back to analog in its original form. If one ha a perfect ADC an a perfect DAC an use the same clock to rive both units, then, (an ignoring certain other factors), there woul be no impact on the signal from jitter. In a real worl system a igitize signal travels through multiple processors, usually parks itself on a isk or piece of tape for a while an then goes through more processing before conversion back to analog. Thus, the clock pulses use to convert the signal have long since gone an are replace with newer ones with their own subtle variations. V m 500m 250m 0-250m -500m -750m u 40u 60u 80u 100u sec igure 2 sample intervals rom the perspective of converting analog signals to igital or igital signals to analog, there are two basic clock sources we shoul consier. One, the internal clock, present in most ADCs, is usually erive from a crystal oscillator. The secon is an external clock source, in the form of a wor clock, AE or /PDI signal that is use to synchronize multiple evices to one clock or to carry clocking an igital ata for conversion back to analog. Internal clocks are usually very stable with respect to frequency an jitter an unless the circuits are noisy or poorly esigne, jitter on the orer of 3 to 10p is possible. An analog to igital converter using such an internal clock will usually yiel the best performance with respect to jitter effects. External clocking moes require a converter to regenerate its internal clocks from an external clock. ince the converter is likely to nee several frequency multiples of the external wor clock a phase locke loop is use to generate these clocks. The new clocks will be multiples of the external clock an will be use to rive the actual conversion process. This regeneration process can introuce jitter into the sample clock in several ways an great care must be taken in the phase locke loop esign to manage intrinsic phase noise an control the amount of interference from other circuitry in the system. The bottom line is that although many goo converters will exhibit very low jitter in their phase locke loops, the internal clock source will often provie slightly better performance with respect to jitter. or igital to analog conversion the sample clock is usually erive from an AE or /PDIf bit stream. An like the analog to igital converter, this regeneration process can introuce jitter into the sample clock in the same ways. There are schemes use to reuce jitter in regenerate clocks an some are very goo. In the long run it comes own to goo circuit esign practices to maintain performance as close to theoretical as possible. To a a bit of complexity to our thinking, jitter can have ifferent probability istributions epening on the source. We ll look at three an show what their effects are on sample signals. ine an square wave inuce jitter is common an results from the pickup of the analog signals to be converte, the igital Jitter effects copyright 1999, 2000 Troisi Design Limite

4 representation of the analog signal following conversion an from irect an inirect effects of the conversion sample clocks. Less easy to etect is jitter cause by wie ban noise that generates a ranom istribution an manifests as increase noise an istortion in the auio signal. o, the sources of the jitter have an effect on its istribution an in turn an effect on the isturbance to the auio signal. Effects of Clock Jitter igure 3 shows an T of a 15k sine wave being converte from the analog omain to the igital omain. There is little or no jitter present an the signal presents a pure spike at the signal frequency. igure 3 Low jitter ADC T igure 4 1 nec broaban jitter Using test equipment esigne to generate jitter one can see the effects of injecting 1 nano-secon jitter with a ranom istribution in figure 4. The jitter affects the entire auio spectrum an has its greatest affect on the noise floor. One can see an approximate increase in the T noise floor of 20. This may be the least obnoxious jitter since its affect is generally istribute over the entire auio range an is therefore less likely to be notice as anything more than noise. When the jitter is cause by coherent noise in the system, the results are often more noticeable. or example, figure 5 shows the effect of a 1k jitter signal at 1nec. Here one can see sie lobes off the main signal that fall 1k from the signal being converte. These sie lobes actually represent energy taken from the funamental frequency an reistribute in the frequency omain. Aurally the effects of this type of jitter can be quite harsh even though the sie lobe amplitues are approximately 120 below the full-scale signal. ince they will have no musical relationship to the signal they will typically be auible as long as other masking agents o not interfere. Taking things a step further, if the generation of clock jitter is inuce by a square wave the resultant effect will inclue harmonic multiples of the jitter frequency in the auio signal. igure 6 shows the effect of square wave jitter causing multiple sie lobes, harmonically relate to the clock isturbance, but issonant to the content of the auio signal. Jitter effects copyright 1999, 2000 Troisi Design Limite

5 ie lobes resulting from 1k jitter igure 5 1 nec ine jitter 1k igure 6 1 nec square wave jitter 1k These T s show how the various jitter types manifest in an analog to igital converter. The effects inicate an increase in the noise floor when wie-ban jitter is introuce an the presence of coherent tones space at intervals of the jitter frequency when narrow ban noise is introuce. It shoul be note that jitter is present only when a signal is present an that the anomalies shown above are not there in the absence of an input signal. This is ue to the fact that the attenant noises an sie lobes cause by jitter are erive from the input signal itself an obtain energy from those signals. urther, the effects of jitter are magnifie as the input signal increases in both frequency an amplitue. 1 nano-secon of jitter will have a far greater impact on a full-scale signal than a 100 full-scale signal. To intuitively grasp the relationship between jitter, frequency an amplitue refer to our iscussion aroun figure 2. What this all means from a listening perspective epens on the musical signal being converte an the type of jitter in the system. As we saw earlier, jitter cause by coherent signals will result in nonharmonically relate noise in the system an may be reaily perceive as a harsh, egy soun when listening. Note that while the wie-ban jitter appears to be the least objectionable the measurements shown in figures 7 an 8 illustrate that all jitter increases the amount of measurable THD in the system quare wave jitter Wie ban jitter ine Jitter r A quare wave jitter ine jitter Wie ban jitter k 2k 5k 5k 15k igure 7 ADC THD with various jitter igure 8 DAC THD with various Jitter Jitter effects copyright 1999, 2000 Troisi Design Limite

6 igure 7 shows the effects one might see on THD from ifferent jitter sources in an analog to igital converter. The overall effect is an increase in THD in the high frequencies. ince all three jitter sources have similar results on THD an noise measurements it is instructive to be able to view an T of the signal uner test (preferably a high frequency, high amplitue signal) to see if there are enharmonic noise spikes resulting from the signal input. The graph in figure 8 shows the jitter effects on THD an noise for a igital to analog converter. Here the results are similar to the analog to igital conversion with an attenant rise in high frequency THD. Note that the wie-ban jitter has less effect on the DACs output (than the ADC) ue to the system s ability to filter out this type of jitter. It is possible to configure a test setup using a high quality analog to igital converter after the DAC uner test to provie Ts of the DAC's analog output signal. y injecting jitter into the igital output signal feeing the DAC an requantizing the DAC s analog output, similar anomalies can be viewe in the DAC s T. igure 9 shows the same DAC (in figure 8) with no jitter, figure 10 shows the effect of wie-ban jitter an figures 11 an 12 with sine an square wave jitter applie to the igital input of the DAC. As with analog to igital conversion, similar characteristics are visible in these plots. igure 9 DAC output with no ae jitter igure 10 DAC output with 1 nec wie ban jitter igure 11 DAC output with 1 nec ine Jitter 1k igure 12 DAC output with 1 nec square wave jitter 1k Jitter effects copyright 1999, 2000 Troisi Design Limite

7 Conclusion In conclusion, the following observations are important relative to jitter when working with analog to igital or igital to analog conversions. 1. Analog to igital converters are typically less prone to jitter effects if the internal clock moes are use. 2. Once a signal has unergone a conversion (analog to igital), there is little, if anything, one can o to correct the effects of jitter on the converte signal. 3. Jitter affects the higher frequencies more than lower frequencies an affects higher signal amplitues more than lower signal amplitues. The most susceptible signals are near full-scale, high frequency signals. 4. Jitter can be cause by intrinsic circuit problems as well as external sources an is usually a combination of the two. It is necessary to make certain that external clocks use for synchronizing analog to igital converters or signals carrying ata to igital to analog converters are properly terminate, are not moifie or isturbe by the elivery meium (cable inuctance & capacitance) an are not subject to high noise environments. 5. The effect jitter has on the conversion process is epenant on the nature of the jitter an its amplitue. 50pec of jitter will have less effect on a signal than 500pec. Jitter that has a wie-ban istribution characteristic will usually soun less offensive than jitter that has a efine, coherent istribution. Jitter effects copyright 1999, 2000 Troisi Design Limite

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