LMMS: An 8-bit Microcode Simulation of the Little Man Computer

Transcription

1 LMMS: An 8-bit Microcode Simulation of the Little Man Computer Thad Crews Western Kentucky University 1 Big Red Way (270) thad.crewsii@wku.edu Abstract The Little Man Computer (LMC) is a simplified example of computer architecture containing al l the components of modern computers: memory, a central processing unit (CPU), and input/output capability. The LMC also contains a small instruction set that allows students to write and execute simple programs. This paper describes the Little Man Microcode Simulator (LMMS), a register-transfer-level simulation of the Little Man Computer. LMMS is built on an 8-bit architecture with multiple viewing perspectives (e.g., digital, binary, and mnemonic). LMMS utilizes memory address and memory data registers to demonstrate CPU activity during memory access. LMMS provides detailed microcode implementation of the complete Little Man instruction set. LMMS uses a powerful but intuitive interface, providing an excellent simulation tool for introducing students to computer organization. Introduction The Little Man Computer (LMC) is a simplified example of computer architecture originally presented by Stuart Madnick at MIT in Over 35 years after its introduction, the LMC remains a useful tool for introducing students to computer hardware and software. The LMC contains all the components of modern computers: memory, a central processing unit (CPU), and input/output capability. The LMC also contains a small instruction set that allows students to write and execute simple programs. By writing and executing LMC programs, students gain valuable experience with important ideas including the stored program concept and the fetch-execute cycle.

2 The Original LMC Model There are many perturbations of Madnick s original LMC model, including a 1979 revision by Madnick himself. Madnick s second version of LMC is used in The Architecture of Computer Hardware and Systems Software, 2 nd Edition [Englander, 2000]. A diagram of Englander s LMC appears in Figure 1. Figure 1: Irv Englander s Little Man Computer The LMC model uses common analogies to represent CPU concepts. For example, memory is represented as a series of 100 mailboxes. The ALU is represented as a calculator. I/O activity occurs though an IN basket and an OUT basket. A hand held counter represents the program counter.

3 The LMC model is decimal based. The mailboxes and calculator each contain a three digit decimal number. When a number needs to be interpreted as an instruction, the first digit represents the op code, and the other two digits indicate the appropriate mailbox address associated with that instruction. For example, the instruction 512 would be interpreted as op code 5 (LOAD) and address 12, meaning the value in mailbox 12 would be copied into the calculator. Limitations of the LMC Model The LMC model is valuable as a conceptual tool for introducing students to important computer architecture concepts. However, there are aspects of the model that are problematic from a pedagogic and simulation perspective: 1. The decimal representation creates a problem concerning the number of memory locations. A single digit operand can access only 10 memory locations, which is too few in most cases. A two-digit operand maps to 100 memory locations, far more than necessary to demonstrate the functionality of the LMC model. For a pencil and paper version, the extra memory cells can simply be ignored (see Figure 1). With a simulator each memory location must be visible to the user, and presenting each memory location becomes a challenge. 2. The decimal representation also creates a problem when mapping to a binary equivalent. One digit op codes (10 instructions) and two digit operand (100 memory locations) corresponds to 4 bit op codes (with unused combinations) and 7 bit addresses (with memory addresses 100 to 127 unused). Also, the 11 total required bits is itself an unusual number (one and three-eights bytes).

4 3. The notion of a little man following a strict set of rules is a useful analogy for the control unit of a CPU. However, since there obviously is no real little man inside the PC, students wanting a more accurate understanding of the CPUs internal structure need a depiction that is closer to reality. The LMMS system, discussed in the following section, addresses these problems and provides pedagogical benefits that go beyond the original LMC model. The LMMS system The LMMS (Little Man Microcode Simulator) system is a register-transfer-level simulation of Madnick s LMC model. The LMMS system is built on an 8-bit architecture with multiple viewing perspectives (e.g., digital, binary and mnemonic). LMMS displays memory address and memory data registers to demonstrate CPU behavior when accessing memory. LMMS provides detailed microcode implementation of the complete Little Man instruction set. The LMMS interface is shown in Figure 2.

5 Figure 2: LMMS user interface The LMMS system is built on a binary (8-bit) architecture, although it also allows decimal and mnemonic representations to support multiple student perspectives. Figure 3 shows the binary and decimal representations of an LMC program that inputs two numbers and displays their sum. Notice how the first three bits make up the decimal op code and the last five bits make up the decimal operand. Details of the program itself are discussed later.

6 Figure 3: Multiple representations of an LMC program. LMMS Fetch-Execute Cycle With the LMC model, the behavior of the Little Man (e.g., control unit) is described at a high level for each instruction in the instruction set. For example, Englander explains the fetch-execute activities of the LOAD instruction this way: The Little Man walks over to the mailbox address specified in the instruction. He reads the three-digit number located in that mailbox, and then walks over to the calculator and punches that number into the calculator. The three-digit number in the mailbox is left unchanged, but of course the original number in the calculator is replaced by the new number. [Englander, 2000, p. 149] The above description is sufficient to carry out the desired behavior using pencil and paper. However since the little man is clearly fictitious it does not provide an accurate understanding of the LOAD operation with respect to the internals of the CPU. LMMS addresses this problem by presenting the instruction set at a microcode level. The fetch-execute cycle for each instruction is described as a series of register transactions. LMMS microcode uses the following five registers: The program counter (PC) contains the address of the next instruction.

7 The instruction register (IR) holds the current instruction being executed by the computer. This register is not identified in the traditional LMC model but is essential to the LMMS system as you will see. The memory address register (MAR) holds the address of a memory location. The memory data register (MDR) is a read/write connection to the data stored in memory at the address identified by the MAR. The accumulator (A) is a general purpose register. The fetch microcode is the same for all instructions: access to the memory location holding the next instruction. auto-increment the program counter copy the instruction from memory to the instruction register After the fetch is complete, the instruction is decoded, and the appropriate execute microcode occurs. LMMS Instruction Set LOAD instruction 1xx Loads the contents of mailbox xx into the calculator. IR[add] MAR access the xx memory location MDR A copy the data from memory to the accumulator STORE instruction 2xx Stores the calculator value into mailbox xx. IR[add] MAR access the xx memory location A MDR copy the data in the accumulator to memory

8 ADD instruction 3xx Adds the contents of mailbox xx to the calculator. IR[add] MAR access the xx memory location A + MDR A increase the value in the accumulator by the data in memory SUBTRACT instruction 4xx Subtracts the contents of mailbox xx from the calculator. IR[add] MAR access the xx memory location A MDR A reduce the value in the accumulator by the data in memory BRANCH instruction 5xx Change the program counter to xx. IR[add] PC change the program counter to xx BRANCH IF POSITIVE instruction 6xx If the calculator value is positive (including zero), then change the program counter to xx. If A >= 0 then IR[add] PC change the program counter if A is positive BRANCH IF ZERO instruction 7xx If the calculator value is Zero, then change the program counter to xx. IF A = 0 then IR[add] PC change the program counter if A is zero INPUT instruction 001 Accept a number from the Input stream and put it in the calculator. I/O Stream A store I/O stream to accumulator

9 OUTPUT instruction 002 Display the number in the calculator. A I/O Stream put accumulator value on the I/O stream HALT instruction 003 Stops the program - the Little Man rests. {end program} terminate the program simulation Creating an LMMS Program Consider a simple program that inputs two numbers and displays their sum. This program can be accomplished with the following instructions: Input read the first value, placing it into the calculator Store 20 store the value in mailbox 20 Input read the second value, placing it into the calculator Add 20 add the first value to the second value in the calculator Output display the sum from the calculator LMC instructions are selected from the pull-down list as shown in Figure 4. Figure 4: Selecting an LMC instruction

10 Selected instructions are copied to specified memory locations. Selected instructions in memory may be edited by choosing a new instruction from the pull down list. Selected instructions may also be moved using the floating Up, Down, and Delete command buttons as shown in Figure 5. Figure 5: Floating edit commands for manipulating memory. Running an LMMS Program Figure 5 shows the memory contents when the Add Two Numbers program has been loaded. Programs are executed by selecting the Run Machine Instruction button or the Run Without Pause button under the register trace grid, or pressing F8 or F9 as a shortcut (see Figure 6). Figure 6: The Register Trace Grid

11 Figure 7 shows LMMS behavior when executing the first instruction (INPUT) of the Add Two Numbers program. The Fetch microcode (; ; ) has been executed. The Execute microcode (I/O Stream A) is waiting for the user to enter a value through the Input dialog box. After the user presses OK, the input value will be stored in the Accumulator and the instruction will be complete. Note that the Program Counter has the value of the address of the next instruction to Fetch. Figure 7: Accepting data during INPUT Figure 8 shows the contents of the register trace grid after completing the INPUT instruction. Notice that the input value 7 is successfully stored in the Accumulator register. Also notice how the register trace grid uses the color red to indicate when a register value has changed during the execution of a microinstruction.

12 Figure 8: Register Values after INPUT Figure 9 shows the LMMS interface after executing the second instruction (STORE 20). Like the register trace grid, the memory grid uses the color red to indicate data has been assigned to a memory location. Blue color indicates an executed instruction. Figure 9: LMMS interface after executing two instructions

13 By selecting Run Without Pause, the program executes Fetch Execute cycles for each instruction in sequence until the Halt instruction is executed. The only pause is for I/O Stream activity, such as accepting the second value and displaying the result of the addition as shown in Figures 10 and 11. Figure 10: Second Input Value Figure 11: LMMS displays the result

14 Other LMMS Programs The Add Two Numbers program is a good first program for beginning students. Other programs that may be more challenging include: Biggest of 3: Write a program that will prompt the user to input three values. The output should be the largest of the three input values. Countdown: Write a program that uses a loop to display the values 10 down to 1. Positive Difference: Write a program that will prompt the user to enter two values. The output should be the positive difference of the two values. For example, if the input is 5 and 7, the output should be 2. If the input values are reversed, the output should still be 2. Largest in a Series: Write a program that will prompt the user to enter a series of values. The program will continue to accept values until the sentinel value of zero is entered. The program should then display the largest value in the series. Solutions to each of these problems are stored in the LMMS folder. The programs may be loaded and executed to provide additional experimentation with the LMMS system. Conclusion The Little Man Computer is a valuable model for introducing student to key ideas in computer architecture, including memory, the central processing unit (CPU), and input/output capability. The LMC also contains a small instruction set that allows students to write and execute simple programs. By writing and executing LMC

15 programs, students gain valuable experience with important ideas including the stored program concept and the fetch-execute cycle. LMMS is a simulator that supports the Little Man model while also providing additional pedagogical benefits. LMMS supports decimal, binary, and mnemonic perspectives of data and instructions. LMMS illustrates CPU/memory behavior through memory address and memory data registers. LMMS provides detailed microcode implementation for the complete LMC instruction set. During simulation, the fetch/execute cycle for each instruction is presented as a trace of register-transfer activities. LMMS uses a powerful but intuitive interface, providing an excellent simulation tool for introducing students to computer organization. References Englander, I. (2000). The Architecture of Computer Hardware and Systems Software 2/e. New York: Wiley.