Logic Expansion Card. (KPI-0045A) User Guide. ARM DUI 0074A Open Access

Transcription

1 Logic Expansion Card (KPI-0045A) User Guide ARM DUI 0074A

2 Logic Expansion Card User Guide Change log Date Issue Change July 1998 A First release Proprietary notice ARM is a registered trademark of ARMLimited. EmbeddedICE and Multi-ICE are trademarks of ARM Limited. XILINX, XC4013XL, XC4062XL, XChecker and Xilinx M1 are all registered trademarks of Xilinx Inc. Adobe and Acrobat are registered trademarks of Adobe Systems Incorporated. Exemplar is a registered trademark of Exampler Logic Incorporated. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality and information status This document is: Final No restriction on distribution Complete information on a developed product ii Copyright ARM Limited All rights reserved. ARM DUI 0074A

3 Preface Logic Expansion Card About this document This document describes the Logic Expansion Card (KPI-0045A) which is used with the ARM Development Board to allow you to prototype peripherals around an ARM core. Intended audience This document has been written for experienced engineers who have knowledge of the bus architecture (AMBA), coprocessor interfaces, and the ARM core they are working with. How to use this document This document is split into the following four sections: Chapter 1 Overview. This gives a brief description of the Logic Expansion Card, its main features and how to connect it to the ARM Development Board. Chapter 2 Hardware Description. This gives a description of the main areas of the Logic Expansion Card. ARM DUI 0074A Copyright ARM Limited All rights reserved. iii

4 Preface Typographical conventions Chapter 3 Configuring the Logic Expansion Card. This gives details of the jumpers and links on the Logic Expansion Card that you have to set. Appendix A Schematics. This comprises the circuit diagram, layout diagram, and connector diagrams of the Logic Expansion Card. The following typographical conventions are used in this document: bold italic highlights signal names within text highlights important notes, ARM-specific terminology, cross references, and references to other publications Abbreviations The following abbreviations are used in this document: AMBA FPGA PLD PLL Advanced Microcontroller Bus Architecture. This specification defines an on-chip communications standard for designing high performance 32-bit and 16-bit embedded microcontrollers. Field Programmable Gate Array. This is a type of programmable logic device. Programmable Logic Device. A Phase Locked Loop. This usually comprises: a voltage controlled oscillator a programmable divider a phase comparator an integrator. These components allow a programmable clock to be generated. This clock is locked and stabilized by a reference clock input. VHDL Test chip ICE This is a Hardware Description Language suitable for the simulation and synthesis of logic circuits. A test chip is an implementation of the ARM core without peripherals, manufactured primarily to validate the porting of the ARM core to a new process. For further details on test chip documentation refer to Related publications. An In-Circuit Emulator. iv Copyright ARM Limited All rights reserved. ARM DUI 0074A

5 Preface EmbeddedICE This is a debugging system used to provide many functions of an ICE, consisting of: an on-chip macrocell an interface unit software. Related publications Feedback on this document The following ARM documents may be useful: The ARM Target Development System User Guide (ARM DUI 0061) The AMBA Specification (ARM IHI 0001) In addition, you may find it useful to refer to the ARM Datasheet, ARM Test Chip Appendix, and header card documents appropriate to the processor you are using. For details on which documents are available please contact ARM Limited, or refer to ARM s website at If you have any comments or suggestions about this document, please contact your supplier giving: the document title the document number the page number(s) to which your comments refer a concise explanation of your comments. ARM DUI 0074A Copyright ARM Limited All rights reserved. v

6 Preface vi Copyright ARM Limited All rights reserved. ARM DUI 0074A

7 Contents Contents Logic Expansion Card Preface Chapter 1 Chapter 2 Chapter 3 Appendix A Overview 1.1 Introduction System requirements Features of the Logic Expansion Card Connecting the Logic Expansion Card Using the Logic Expansion Card Hardware Description 2.1 Header card connectors Power supply Clock generation FPGA configuration Expansion connector Status LEDs BERROR BLAST Configuring the Logic Expansion Card 3.1 Locating jumpers and links Summary of jumper and link settings Selecting and setting FCLK Schematics A.1 Component layout...a-2 A.2 Top level schematic...a-3 A.3 Amba FPGA schematic and pin layout...a-4 A.4 Coprocessor interface FPGA schematic and pin layout...a-6 A.5 Clock generation schematic...a-8 A.6 Status LEDs schematic...a-9 A.7 Header connectors schematics...a-10 A.8 Expansion connector pin location, schematic and pinout...a-12 ARM DUI 0074A Copyright ARM Limited All rights reserved. vii

8 Contents viii Copyright ARM Limited All rights reserved. ARM DUI 0074A

9 Chapter 1 Overview 1.1 Introduction The ARM Development Board helps you to develop ASICs based on embedded ARM processors, and provides a convenient means of evaluating ARM s family of RISC processors. The Logic Expansion Card is a useful addition to the ARM Development Board. It provides a large amount of programmable, uncommitted logic in the form of two large FPGAs. This allows you to evaluate the proposed logic of an ASIC s design. You can synthesize either AMBA or coprocessor-based peripherals into these FPGAs, allowing you to develop and test device drivers for the peripherals in an ASIC early in your design cycle. The hardware and software described in this document can be used with any ARM test chip that can be fitted to the ARM Development Board. ARM DUI 0074A Copyright ARM Limited All rights reserved. 1-1

10 Overview 1.2 System requirements To use the Logic Expansion Card you will need the following: ARM Development Board (HBI-0011B). An ARM Processor Header Card. At the time of printing the Logic Expansion Card supports the following Processor Header Cards: ARM710T header card (HHI-0033) ARM720T header card (HHI-0031) ARM740T header card (HHI-0038) ARM7TDMI header card (HHI-0016) ARM940T header card (HHI-0032) ARM9TDMI header card (HHI-0045) If you have a Processor Header Card not listed above, please contact ARM Limited to check compatibility. ARM Debugger, such as: Mulit-ICE (recommended) EmbeddedICE Angel A synthesis tool, such as Exemplar. Xilinx tools (M1.4 or greater) are required to place and route the design. 1.3 Features of the Logic Expansion Card The main features of the Logic Expansion Card are: Two FPGAs. These allow peripherals that are based on AMBA or coprocessor interfaces to be synthesized into uncommitted logic. A programmable PLL. This generates the fast processor clock, FCLK, and is programmed via jumpers on the Logic Expansion Card. A 50ohm mini-coax connector. This allows you to input an external clock signal. A general purpose input/output connector. This is an expansion connector which allows you to expand the board, or debug using non-arm tools. The ability to separate core and pad power supplies. This allows you to measure the power requirements of just the ARM processor core. 1-2 Copyright ARM Limited All rights reserved. ARM DUI 0074A

11 Overview 1.4 Connecting the Logic Expansion Card The Logic Expansion Card is fitted between the ARM Development Board and the Processor Header Card (see Figure 1-1 Connecting the Logic Expansion Card). This allows the signals between the ARM Development Board and the Processor Header Card to be intercepted if necessary. When fitted, the Logic Expansion Card protrudes over the edge of the ARM Development Board and Processor Header Card, so that you can access the jumpers without having to remove the header card. Figure 1-1 Connecting the Logic Expansion Card ARM DUI 0074A Copyright ARM Limited All rights reserved. 1-3

12 Overview 1.5 Using the Logic Expansion Card The floppy disc supplied with the Logic Expansion Card contains guidance and an example designed to help you use the Logic Expansion Card. The file Readme.pdf on the disc contains: an example of a simple memory-mapped peripheral for the Logic Expansion Card a procedure on how to use the example guidelines on how to implement your own design a list of associated files contained on the disc. Readme.pdf can be viewed using Adobe Acrobat Reader version 3.0 you can download a copy of this free of charge from the Documentation area on ARM s website ( 1-4 Copyright ARM Limited All rights reserved. ARM DUI 0074A

13 Chapter 2 Hardware Description This chapter describes the following areas of the Logic Expansion Card: Header Card connectors (page 2-2) Power supply (page 2-2) Clock generation (page 2-3) FPGA configuration (page 2-4) General purpose input/output connection (expansion connector) (page2-6) Status LEDs (page 2-7). The circuit diagram, layout diagram and connector diagrams are detailed in AppendixA. ARM DUI 0074A Copyright ARM Limited All rights reserved. 2-1

14 Hardware Description 2.1 Header card connectors 2.2 Power supply The Logic Expansion Card has five 60-way header card connectors (PL1 PL5). Four of the connectors (PL1 PL4) connect to both the ARM Development Board and the Processor Header Card, and the majority of the connections carry signals from the development board straight through to the header card, with a connection to one, or both of the FPGAs. These connectors also carry additional signals from the Logic Expansion Card to the Processor Header Card. These additional signals are: coprocessor signals instruction buses miscellaneous signals. The fifth connector (PL5) connects to the Processor Header Card only, and carries coprocessor signals that are required by certain ARM devices (for example, ARM940T has additional coprocessor signals that are not available on the other connectors (PL1 PL4)). The Logic Expansion Card takes its power from the 3.3V supply on the ARM Development Board. All the supplies are decoupled, and low ESR capacitors are used throughout. The ARM Development Board provides protection from 5V signals, which means the Logic Expansion Card supports ARM processors operating over the range 2.7V 5V. The Logic Expansion Card allows you to measure the core power consumption as the power supply (Vdd) is split into: Core power supply (Vddm) Pad power supply (Vdd). If you want to vary the power supply to the core in order to make current measurements, you must remove the link JP1 and connect an external power supply. Alternatively, you can replace JP1 with a low value resistor (for example a 1ohm resistor) and measure the voltage across it. 2-2 Copyright ARM Limited All rights reserved. ARM DUI 0074A

15 Hardware Description 2.3 Clock generation BCLK The Logic Expansion Card uses two clocks: BCLK FCLK. BCLK is the AMBA bus clock, and is generated on the ARM Development Board. This clock can be set to one of the following frequencies: 4MHz 8MHz 16MHz 20MHz. For details on how to set the frequency of BCLK refer to the ARM Target Development System User Guide (ARM DUI 0061) FCLK FCLK is used to clock the two FPGAs on the Logic Expansion Card. You have the option of using three different sources for FCLK: Generated on the Processor Header Card Input from an external source Generated on the Logic Expansion Card. For details on how to select which source to use refer to Table 3-2 Selecting and setting FCLK on page 3-4. FCLK generated on the Processor Header Card If you are using FCLK generated on the Processor Header Card refer to the User Guide supplied with that card for details on the frequencies available, and how to set them. FCLK input from an external source If you are using an external FCLK, you need to connect it to the 50ohm mini-coax connector SK5. ARM DUI 0074A Copyright ARM Limited All rights reserved. 2-3

16 Hardware Description 2.4 FPGA configuration FCLK generated on the Logic Expansion Card A PLL (AV or W48C55-62) is provided on the Logic Expansion Card which generates a local FCLK. This clock is used to drive the two FPGAs, and can be used to drive FCLK on the Processor Header Card. The reference clock to the on-board PLL is supplied by a crystal which has a frequency of MHz. The on-board PLL has three programmable inputs, and can output one of 12 preset frequencies in the range 4 100MHz. In addition to these 12 preset frequencies you can set the output of the PLL to be the same value as the AMBA bus clock generated by the ARM Development Board. See BCLK on page 2-3. If you set FCLK to equal BCLK then any changes to the BCLK value will result in a change to the FCLK value. For details on the frequencies available and how to set them refer to Table3-2 Selecting and setting FCLK on page 3-4. The Logic Expansion Card has two FPGAs: U9, for connection to the AMBA bus U10, for connection to the coprocessor interface. Both of these are 240-pin PQFP XILINX (3.3V) FPGAs (XC4062XL), which provides enough input/output pins and resources to enable you to prototype most peripherals. A 72-bit bus is provided as a communication channel between the two FPGAs, and you can use this bus to drive the eight general-purpose LEDs. (See 2.6 Status LEDs on page 2-7.) You can load the content of the FPGAs from either: separate serial PROMs via an XChecker cable. Full details are given in the following sections, and and Figure 2-1 shows the position of the PROMs, connectors and link positions associated with configuring the FPGAs. 2-4 Copyright ARM Limited All rights reserved. ARM DUI 0074A

17 Hardware Description Figure 2-1 FPGA PROMs, connectors and link positions Loading from PROM To enable you to load the content of the FPGAs from PROM, the Logic Expansion Card has two pairs of PROM sockets one pair for the AMBA FPGA (U1 and U3) and one for the coprocessor interface FPGA (U5 and U6). Each pair is serially connected, which allows them to be cascaded. Each pair may comprise: a single 1MB PROM (XC1701L) a single 1MB PROM (XC1701L), cascaded with a single 512KB PROM (XC17512L) two 1MB PROMs (XC1701L) cascaded together. To set the Logic Expansion Card to load the AMBA FPGA from PROM you must fit jumper J4. To set the Logic Expansion Card to load the coprocessor interface FPGA from PROM you must fit jumper J6. ARM DUI 0074A Copyright ARM Limited All rights reserved. 2-5

18 Hardware Description Loading via an XChecker cable To enable you to load the content of the FPGAs via an XChecker cable the Logic Expansion Card has two 9-pin connectors one for the AMBA FPGA (J1) and one for the coprocessor interface FPGA (J2). To allow the bit files to be downloaded to the PROMs you have to run the Xilinx Hardware Debugger portion of the Xilinx M1 software. Caution Before using the XChecker cable you must remove the appropriate PROMs (either U1 and U3, or U5 and U6). You must use the 3V adaptor board supplied with the XChecker cable to provide 5V to the XChecker cable. 2.5 Expansion connector To set the Logic Expansion Card to load the AMBA FPGA via an XChecker cable you must remove jumper J4. To set the Logic Expansion Card to load the coprocessor interface FPGA via an XChecker cable you must remove jumper J6. The Logic Expansion Card has a 96-pin expansion connector (J3). This connector provides access to the signal bus which is shared by both the AMBA FPGA and the coprocessor interface FPGA. The internal signals in the FPGA can be routed directly to the expansion connector allowing you to: monitor the signals (logic analyzer probes can easily be attached) use it as a platform to prototype small peripherals develop expansion boards. The signals are divided into the following three buses: 32-bit address bus FA[31:0] 32-bit data bus FD[31:0] 8-bit control bus FC[7:0] The expansion connector also supplies 3.3V power and ground. For details of the pinout refer to Table A-1 Expansion connector Pinout on page A Copyright ARM Limited All rights reserved. ARM DUI 0074A

19 Hardware Description 2.6 Status LEDs 2.7 BERROR 2.8 BLAST The Logic Expansion Card has ten surface mount status LEDs (D1 D10): D1 D8. These yellow LEDs, when enabled, indicate the status of the FPGAs. You can configure these yellow LEDs (via the link LK3) to be: disabled link fitted between A and C permanently enabled link fitted between B andc enabled, where they are buffered under AMBA FPGA control (nleden on pin 233 of the AMBA FPGA) link removed D9 D10. These green LEDs indicate if the FPGAs have loaded their configuration data correctly (D9 for the AMBA FPGA and D10 for the coprocessor interface FPGA). The LEDs are buffered by U8 and light with a logic 0 on the control bus FC[7:0]. If the processor fitted in the Processor Header Card attempts to access a memory map address above 256MB, the ARM Development Board generates a BERROR signal which is passed back to the header card causing the processor to perform a data abort. If you require access to memory map addresses above 256MB you must develop logic for the AMBA FPGA. This logic must allow BERROR to be intercepted and generate a ERROROUT signal only if the higher address value is exceeded. ERROROUT received by the header card will cause the processor to perform a data abort. To enable the interception of BERROR you must remove the link J10. The ARM Development Board generates a BLAST signal to indicate a non-sequential cycle. If the header card receives a combination of BLAST and BERROR signals it causes a retract bus operation. The Logic Expansion Card allows you to configure the card such that BLAST is intercepted by the AMBA FPGA. To enable the interception of BLAST you must remove the link J11. Note It is recommended that you fit the J11, and disable the interception of BLAST. ARM DUI 0074A Copyright ARM Limited All rights reserved. 2-7

20 Hardware Description 2-8 Copyright ARM Limited All rights reserved. ARM DUI 0074A

21 Chapter 3 Configuring the Logic Expansion Card The Logic Expansion Card is configurable via: a wire fitted link (JP1) eleven jumpers (J1, J2, J4 J12) two sets of links (LK1 and LK2) one surface mount link (LK3). Section 3.1 shows the location of the jumpers and links, section 3.2 gives a brief description for each jumper and link, and section 3.3 gives details of how to select and set FCLK using LK1 and LK2. ARM DUI 0074A Copyright ARM Limited All rights reserved. 3-1

22 Configuring the Logic Expansion Card 3.1 Locating jumpers and links Figure 3-1 Location of jumpers and links 3-2 Copyright ARM Limited All rights reserved. ARM DUI 0074A

23 Configuring the Logic Expansion Card 3.2 Summary of jumper and link settings Table 3-1 Jumper and link settings Jumper/link JP1 J1 J2 J4 Description If removed, the core current can be measured. If loading the AMBA FPGA via an XChecker cable, connect the cable to this jumper. If loading the coprocessor interface FPGA via an XChecker cable, connect the cable to this jumper. If fitted, the AMBA FGPA is loaded from PROM. If removed, the AMBA FGPA is loaded via an XChecker cable. J5 Not used. * J6 If fitted the coprocessor interface FGPA is loaded from PROM. If removed the coprocessor interface FGPA is loaded via an XChecker cable. J7 Not used. * J8 Not used. * J9 Not used. * J10 J11 If fitted, the AMBA FPGA does not implement the interception of BERROR. If removed, the AMBA FPGA intercepts BERROR from the ARM Development Board. (For details refer to 2.7 BERROR on page 2-7) If fitted, the AMBA FPGA does not implement the interception of BLAST. If removed, the AMBA FPGA intercepts BLAST from the ARM Development Board. (For details refer to 2.8 BLAST on page 2-7) J12 Not used. * LK1 and LK2 LK3 Used to select the source and frequency of FCLK. For details refer to Table 3-2 Selecting and setting FCLK on page 3-4 Used to control the output buffer used to drive the eight status LEDs (D1 D8). If fitted between A and C, the LEDs are disabled. If fitted between B and C, the LEDs are enabled. If removed, the LEDs are buffered under FGPA control (nleden on pin 233 of the AMBA FPGA). This is the factory default. * The jumpers J5, J7 J9, and J12 may be used to provide access to the spare FGPA inputs/outputs. You may use these as extra monitoring points, or allow the FPGA to read them to provide configuration options. ARM DUI 0074A Copyright ARM Limited All rights reserved. 3-3

24 Configuring the Logic Expansion Card 3.3 Selecting and setting FCLK Table 3-2 Selecting and setting FCLK Source FCLK LK1 LK2 Freq. (MHz) FREQ LINK0 FREQ LINK1 FREQ LINK2 Do not fit MCLK CLK 2XCLK EXTCLK Processor Header Card - OUT OUT OUT - OUT OUT OUT OUT External - OUT/IN OUT/IN OUT/IN - OUT OUT OUT IN ARM Development Board = BCLK OUT/IN OUT/IN OUT/IN - IN OUT OUT OUT On-board PLL 4 OUT OUT OUT - OUT IN OUT OUT 8 OUT OUT OUT - OUT OUT IN OUT 16 IN OUT OUT - OUT OUT IN OUT 20 IN IN OUT - OUT IN OUT OUT 25 OUT OUT IN - OUT IN OUT OUT 32 OUT IN OUT - OUT OUT IN OUT 33 IN OUT IN - OUT IN OUT OUT 40 IN IN OUT - OUT OUT IN OUT 50 OUT OUT IN - OUT OUT IN OUT 66 IN OUT IN - OUT OUT IN OUT 80 OUT IN IN - OUT OUT IN OUT 100 IN IN IN - OUT OUT IN OUT 3-4 Copyright ARM Limited All rights reserved. ARM DUI 0074A

25 Appendix A Schematics This Chapter contains the following illustrations and tables: Figure A-1 Component layout on page A-2. Figure A-2 Top level schematic on page A-3. Figure A-3 AMBA FPGA Schematic on page A-4. Figure A-4 AMBA FPGA Pin layout on page A-5. Figure A-5 Coprocessor interface FPGA Schematic on page A-6. Figure A-6 Coprocessor interface FPGA Pin layout on page A-7. Figure A-7 Clock generation Schematic on page A-8. Figure A-8 Status LEDs Schematic on page A-9. Figure A-9 Lower header connectors Schematic on page A-10. Figure A-10 Upper header connectors Schematic on page A-11. Figure A-11 Expansion connector Pin location on page A-12. Figure A-12 Expansion connector Pinout schematic on page A-12. Table A-1 Expansion connector Pinout on page A-13. ARM DUI 0074A Copyright ARM Limited All rights reserved. A-1

26 Schematics A.1 Component layout Figure A-1 Component layout A-2 Copyright ARM Limited All rights reserved. ARM DUI 0074A

27 Schematics A.2 Top level schematic LK LINK-4 FREQLINK2 FREQLINK1 FREQLINK0 PDLINK nleden EXPANSION AND STATUS LEDS nleden C22 100n GND FREQLINK0 14 U11B HC05 U11C FREQSEL0 R40 10K R43 10K ERROR 1 J10 2 HEADER 2 ERROROUT Note : Insert link only when FPGAs are not programmed or design does not use BERROR FREQLINK1 5 6 FREQSEL1 R1 10K R2 10K R3 10K R4 10K FA[31..0] FD[31..0] FC[7..0] FA[31..0] FD[31..0] FC[7..0] FREQLINK2 PDLINK 74HC05 U11D HC05 U11E FREQSEL2 PD R41 10K R42 10K CLOCKGEN MCLK MCLK FCLK FCLK FREQSEL[2..0] FREQSEL[2..0] PD PD Figs. A8-A12 74HC05 Fig. A7 AMBA TRICKBOX LOWERHEADERS UPPERHEADERS COPROTRICKBOX A[31..0] A[31..0] A[31..0] A[31..0] A[31..0] PD PD D[31..0] PROT[1..0] D[31..0] PROT[1..0] D[31..0] PROT[1..0] D[31..0] PROT[1..0] D[31..0] PROT[1..0] FREQSEL[2..0] FREQSEL[2..0] RES[2..0] RES[2..0] RES[2..0] RES[2..0] RES[2..0] RES0 RES0 TRAN[1..0] TRAN[1..0] TRAN[1..0] TRAN[1..0] TRAN[1..0] SIZE[1..0] SIZE[1..0] SIZE[1..0] SIZE[1..0] SIZE[1..0] ERROR ERROR ERROR ERROROUT ERROROUT WAIT WAIT WAIT WAIT WAIT WRITE WRITE WRITE WRITE WRITE LOCK LOCK LOCK LOCK LOCK DBGACK DBGACK DBGACK LAST LAST LAST LASTOUT LAST EDBGRQ EDBGRQ EDBGRQ MCLK MCLK MCLK MCLK MCLK GNTARM GNTARM GNTARM GNTARM GNTARM REQARM REQARM REQARM REQARM REQARM SPAREIO[3..0] SPAREIO[3..0] REQ001 GNT001 CPA CPB ncpi nopc FASTBUS BIGEND SnA ISYNC DSEL LASTOUT REQ001 GNT001 CPA CPB ncpi nopc FASTBUS BIGEND SnA ISYNC DSEL LASTOUT REQ001 GNT001 BIGEND ISYNC CPA CPB ncpi CPA CPB ncpi REQ001 GNT001 FC[7..0] FASTBUS BIGEND SnA ISYNC DSEL REQ001 PASS GNT001 LATECANCEL CHSD[1..0] FC[7..0] CHSE[1..0] CPA FASTBUS CPB BIGEND ncpi SnA ncpwait ISYNC nopc DSEL CPDIN[31..0] CPDOUT[31..0] ID[27..0] PASS LATECANCEL CHSD[1..0] CHSE[1..0] CPA CPB ncpi ncpwait nopc CPDIN[31..0] CPDOUT[31..0] ID[27..0] PASS LATECANCEL CHSD[1..0] CHSE[1..0] CPA CPB ncpi ncpwait nopc BIGEND CPDIN[31..0] CPDOUT[31..0] ID[27..0] MCLK BIGEND MCLK ERROROUT ERROROUT nfiq nfiq nfiq nfiq nfiq CPCLK CPCLK CPCLK nfiq nfiq nirq nirq nirq nirq nirq CPINMREQ CPINMREQ CPINMREQ nirq nirq FCLK FCLK FCLK FCLK CPTBIT CPTBIT CPTBIT ECLK ECLK ECLK ECLK ECLK ECLK ncptrans ncptrans ncptrans FCLK FCLK DEWPT IEBKPT DEWPT IEBKPT DEWPT IEBKPT DEWPT IEBKPT SPAREIO[3..0] SPAREIO[3..0] FA[31..0] FD[31..0] FA[31..0] FD[31..0] nicerst nicerst nicerst FC[7..0] FC[7..0] FA[31..0] FA[31..0] nleden nleden ntrst ntrst ntrst FD[31..0] FD[31..0] EXTERN[1..0] EXTERN[1..0] EXTERN[1..0] FC[7..0] FC[7..0] EXTERN[1..0] EXTERN[1..0] COMMTX COMMTX COMMTX COMMRX COMMRX COMMRX Fig. A3-A4 Fig. A9 Fig. A10 Fig. A5-A6 Figure A-2 Top level schematic ARM DUI 0074A Copyright ARM Limited All rights reserved. A-3

28 Schematics A.3 Amba FPGA schematic and pin layout DIN CCLK nprog DONE DONE DOWNLOAD CABLE CONNECTOR J1 U1 DATA CLK OE CE CON9 Cut pin 3 CCLK DIN LASTOUT LAST DSEL VCC VPP CEO GND XC17256L-PD8C U11A J4 SPAREIO6 SPAREIO7 SPAREIO9 SPAREIO HC05 CON2 J CON2 J8 1 2 DIN CCLK nprog nceo ndone CON2 J5 1 2 CON2 J7 1 2 CON2 R5 4K DO NOT FIT AMBA FPGA OK 3 R8 4K7 U3 R6 4K7 REQ001 GNT001 CPA CPB ncpi nopc DEWPT EXTERN[1..0] IEBKPT DATA CLK OE CE XC17256L-PD8C D9 LED R10 2 VCC VPP CEO GND GREEN R7 4K7 R9 DONE nprog INIT 0R 0R REQ001 GNT001 MODE0 MODE1 MODE2 CPA CPB ncpi nopc R38 220R DEWPT EXTERN[1..0] IEBKPT AMBA Signals A[31..0] ERROR WAIT WRITE LOCK LAST LASTOUT MCLK GNTARM REQARM ERROROUT DSEL Misc. Signals nfiq nirq BIGEND FCLK ECLK SnA D[31..0] PROT[1..0] RES[2..0] TRAN[1..0] SIZE[1..0] ISYNC FASTBUS SPAREIO[3..0] FA[31..0] FD[31..0] FC[7..0] nleden Clock gen control signals FREQSEL[2..0] PD SPAREIO12 SPAREIO13 J A[31..0] D[31..0] PROT[1..0] RES[2..0] TRAN[1..0] SIZE[1..0] ERROR WAIT WRITE LOCK LAST LASTOUT MCLK GNTARM REQARM ERROROUT DSEL CON2 nfiq nirq BIGEND FCLK ECLK SnA ISYNC FASTBUS SPAREIO[3..0] FA[31..0] FD[31..0] FC[7..0] nleden FREQSEL[2..0] PD C1 10u C2 100n C3 100n C4 100n C5 100n GND Figure A-3 AMBA FPGA Schematic A-4 Copyright ARM Limited All rights reserved. ARM DUI 0074A

29 Schematics ARM DUI 0074A Copyright ARM Limited All rights reserved. A-5 Figure A-4 AMBA FPGA Pin layout DO NOT FIT DONE FA22 SPAREIO9 ERROROUT FA1 D27 FA14 nfiq RES2 FD6 DEWPT SIZE1 ERROR MODE2 A26 FD28 D7 D1 D31 SPAREIO8 D2 A30 SPAREIO0 FD4 D4 FA12 A11 D23 ncpi SnA PROT1 FA18 D9 FA0 D20 D29 D25 FD27 ECLK D13 A8 FC7 FREQSEL1 FA24 FA25 FD1 FREQSEL0 A1 FD24 A17 FD13 ISYNC FA5 D30 A24 FA26 D28 FA9 FA10 FA15 D11 EXTERN0 FD9 FD10 A0 FD22 nopc CPB FA3 FA28 FA21 D24 TRAN1 FA19 A7 FA13 FC1 FD15 FA30 D14 EXTERN1 FA11 CCLK A29 A5 SPAREIO12 MODE0 D5 GNT001 FD23 RES0 REQARM SPAREIO1 REQ001 FC2 SPAREIO2 FD7 D6 FA27 GNTARM FD19 FA6 FD18 D15 A28 SPAREIO3 A13 A14 A3 A4 A2 TRAN0 nprog A27 A12 D12 A15 FD17 FA23 D17 D8 FA8 SPAREIO13 A22 FA16 FD8 FD29 WRITE SPAREIO6 FD31 D16 FD2 D26 MODE1 WAIT D22 PD FC5 IEBKPT FC3 FD16 FC6 A9 FD14 A23 RES1 A19 A16 A10 LOCK LASTOUT SIZE0 D19 D3 CPA FD11 A6 FC4 A20 INIT FD26 MCLK FA20 BIGEND nirq FA29 D0 FD5 SPAREIO11 FA2 DSEL FA7 FD3 A18 FD21 nleden FA17 DIN D21 FA31 D10 FD25 FASTBUS FC0 A31 FD12 FD30 LAST FD0 FREQSEL2 D18 FD20 A25 FCLK A21 FA4 SPAREIO7 PROT0 R33 33R R34 220R U9 XC4013LPQ240-1PC M2 62 GND 1 P63 63 P HDC 64 A16 2 P65 65 P P66 66 A17 3 P67 67 A LDC 68 P4 4 P69 69 A P70 70 P5 5 P71 71 VCC 240 VCC 61 P72 72 P6 6 P73 73 D2 159 P74 74 P7 7 GND 75 P P76 76 P8 8 P77 77 VCC 161 P78 78 P9 9 P79 79 P VCC 80 P10 10 P81 81 D4 148 P11 11 P82 82 TDO 181 NC 83 P12 12 P84 84 GND 182 P85 85 P13 13 P86 86 A0/WS 183 P87 87 GND 14 P88 88 A1 184 INIT 89 P15 15 VCC 90 P GND 91 P16 16 P92 92 P P93 93 P17 17 P94 94 A2/CS1 187 P95 95 P18 18 P96 96 A3 188 P97 97 VCC 19 NC 98 P P99 99 P20 20 P NC 195 VCC 101 P21 21 P GND 196 P P23 23 P P P P24 24 GND 106 VCC 201 P P25 25 P A4 202 P P26 26 P A5 203 P P27 27 P NC 204 P P28 28 P P P GND 29 P P P VCC 30 P A6 209 GND 119 P31 31 DONE 120 A7 210 P32 32 GND 211 P33 33 VCC 212 P34 34 A8 213 P35 35 A9 214 P36 36 P P38 38 NC 219 P39 39 A VCC 40 A P41 41 VCC 222 P42 42 P P43 43 GND 227 P44 44 P GND 45 P P46 46 A P47 47 A P48 48 P P49 49 VCC 150 P50 50 GND 166 P51 51 P P52 52 P P53 53 P P54 54 P P55 55 P P56 56 P P57 57 D1 173 M1 58 RCLK 174 GND 59 P M0 60 P P D0/DIN 177 DOUT 178 CCLK 179 VCC 180 P P P P P GND 151 D3 152 RS 153 P VCC 121 PROG 122 D7 123 P P P P P P P D6 129 P P P P P P P P P P P P P P P P P P D5 141 CSO 142 NC 143 P P P P P NC 158 P P P P GND 135 P P P P VCC 140 NC 22 NC 37 XC4013XLPQ240-1PC Or XC4067XLPQ240-3PC XC4013XLPQ240-1PC Or XC4062XLPQ240-3PC

30 Schematics A.4 Coprocessor interface FPGA schematic and pin layout Figure A-5 Coprocessor interface FPGA Schematic A-6 Copyright ARM Limited All rights reserved. ARM DUI 0074A

31 Schematics XC4013XLPQ240-1PC Or XC4062XLPQ240-3PC Figure A-6 Coprocessor interface FPGA Pin layout ARM DUI 0074A Copyright ARM Limited All rights reserved. A-7

32 Schematics A.5 Clock generation schematic Figure A-7 Clock generation Schematic A-8 Copyright ARM Limited All rights reserved. ARM DUI 0074A

33 Schematics A.6 Status LEDs schematic Figure A-8 Status LEDs Schematic ARM DUI 0074A Copyright ARM Limited All rights reserved. A-9

34 Schematics A.7 Header connectors schematics Figure A-9 Lower header connectors Schematic A-10 Copyright ARM Limited All rights reserved. ARM DUI 0074A

35 Schematics PL1 1 A0 A1 3 2 PL4 1 A2 COMMTX FC A3 ID1 A A5 ID A6 TRAN0 A A8 ID5 FC A9 ID7 A A A12 ID8 A A14 ID10 FC A15 ncpi A A17 CPA A18 A A20 ERROROUT A21 MCLK A A23 ISYNC A24 nirq A A A27 ID12 A A29 ID A30 ID16 A WRITE ID18 DSEL SIZE0 ID20 SIZE PROT1 ID LOCK ID23 PROT ID SnA ID26 FCLK FASTBUS ncptrans M REQARM GNTARM REQ001 GNT001 ntrst TDO TMS TDI CPDOUT8 CPDOUT10 EXTERN1 CPDOUT12 CPDOUT14 CPDOUT17 CPDOUT19 CPDOUT21 CPDOUT23 CPDOUT26 CPDOUT28 CPDOUT30 M CON60AP PL2 1 SPAREIO0 3 2 SPAREIO2 5 4 DEWPT D FC D D FC D D FC D D FC D D FC D D CPCLK M CON60AP PL CON60AP SPAREIO1 SPAREIO3 IEBKPT D0 D2 D3 D5 D6 D8 D9 D11 D12 D14 D15 D17 D18 D20 D21 D23 D24 D26 D27 D29 D30 ncpwait nopc EDBGRQ DBGACK CPDOUT0 CPDOUT1 CPDOUT2 CPDOUT3 CPDOUT4 CPDOUT5 CPDOUT6 CPDOUT7 TCK CPDOUT9 CPDOUT11 EXTERN0 CPDOUT13 CPDOUT15 CPDOUT16 CPDOUT18 CPDOUT20 CPDOUT22 CPDOUT24 CPDOUT25 CPDOUT27 CPDOUT29 M CPDOUT31 ECLK CPDIN1 CPDIN3 CPDIN5 CPDIN7 CPDIN9 CPDIN11 CPDIN13 CPDIN15 CPDIN17 CPDIN19 CPDIN21 CPDIN23 CPDIN25 CPDIN27 CPDIN29 CPDIN31 CHSD0 CHSE0 PASS CON60AP PL C18 10u CON60AP COMMRX ID0 ID2 ID4 TRAN1 ID6 WAIT LAST ID9 ID11 CPB RES0 RES1 RES2 nfiq BIGEND nicerst ID13 ID15 ID17 VCC ID19 ID22 ID25 ID27 CPTBIT CPDIN0 CPDIN2 CPDIN4 CPDIN6 CPDIN8 CPDIN10 CPDIN12 CPDIN14 CPDIN16 CPDIN18 CPDIN20 CPDIN22 CPDIN24 CPDIN26 CPDIN28 CPDIN30 LATECANCEL CHSD1 CHSE1 CPINMREQ 10k DO NOT FIT 1 TESTPIN 1 VCC R30 DO NOT FIT 10k R31 JP1 JUMPER nfiq nirq CPDOUT[31..0] CPDIN[31..0] ID[27..0] PASS LATECANCEL CHSD[1..0] CHSE[1..0] nopc ncpwait CPCLK CPTBIT ncptrans A[31..0] WRITE SIZE[1..0] PROT[1..0] LOCK D[31..0] ncpi CPA CPB RES[2..0] ERROROUT MCLK ISYNC BIGEND nicerst REQARM GNTARM ntrst EXTERN[1..0] M C19 100n COMMRX COMMTX nfiq nirq M1 TESTPIN LINK TO ENABLE CURRENT MEASUREMENTS OF THE CORE 1 CPDOUT[31..0] CPDIN[31..0] ID[27..0] PASS LATECANCEL CHSD[1..0] CHSE[1..0] nopc ncpwait CPCLK CPTBIT ncptrans A[31..0] WRITE SIZE[1..0] PROT[1..0] LOCK D[31..0] ncpi CPA CPB RES[2..0] ERROROUT MCLK ISYNC BIGEND nicerst REQARM GNTARM ntrst EXTERN[1..0] COMMRX COMMTX GND1 TESTPIN 1 FC[7..0] DSEL FCLK SPAREIO[3..0] TRAN[1..0] WAIT LAST FC[7..0] Figure A-10 Upper header connectors Schematic SnA FASTBUS ECLK CPINMREQ EDBGRQ DEWPT IEBKPT DBGACK REQ001 GNT001 GND2 TESTPIN 1 DSEL FCLK SnA FASTBUS ECLK SPAREIO[3..0] CPINMREQ EDBGRQ DEWPT IEBKPT DBGACK TRAN[1..0] WAIT LAST REQ001 GNT001 ARM DUI 0074A Copyright ARM Limited All rights reserved. A-11

36 Schematics A.8 Expansion connector pin location, schematic and pinout Figure A-11 Expansion connector Pin location Figure A-12 Expansion connector Pinout schematic A-12 Copyright ARM Limited All rights reserved. ARM DUI 0074A

37 Schematics Table A-1 Expansion connector Pinout Row A Row B Row C FD0 FC0 FA31 FD1 FC1 FA30 FD2 FC2 FA29 FD3 FC3 FA28 FD4 FC4 FA27 FD5 FC5 FA26 FD6 FC6 FA25 FD7 FC7 FA24 FD8 FA23 FD9 FA22 FD10 FA21 FD11 FA20 FD12 FA19 FD13 FA18 FD14 FA17 FD15 FA16 FD16 FA15 FD17 FA14 FD18 FA13 FD19 FA12 FD20 FA11 FD21 FA10 FD22 FA9 FD23 FA8 FD24 FA7 FD25 FA6 FD26 FA5 FD27 FA4 FD28 FA3 FD29 FA2 FD30 FA1 FD31 FA0 ARM DUI 0074A Copyright ARM Limited All rights reserved. A-13

38 Schematics A-14 Copyright ARM Limited All rights reserved. ARM DUI 0074A