# Real time MATLAB Interface for speed control of Induction motor drive using dspic 30F4011

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2 are the details about the linguistic variables and control rules (iii) Defuzzification: Process of converting fuzzified output into crisp value. The inputs to the FLC are error (e) and change in error (ce). The output is the voltage of the switching signal. The universe of discourse of all the variables, covering the whole region, is expressed in per unit values. All the MFs are asymmetrical because near the origin, the signals require more precision. There are seven MFs for e and ce signal, whereas there are seven MFs for the output. All the MFs are symmetrical for positive and negative values of the variables. Table 1 shows the corresponding rule table for the speed controller. The top row and left column of the matrix indicate the fuzzy sets of the variables e and ce, respectively, and the MFs of the output variable du are shown in the body of the matrix. There may be 7*7 = 49 possible rules in the matrix. Mamdani type controller is chosen for this application and the basic rule of this type of controller is IF ce is PS AND e is NM THEN du is NS. Degree of MF Figure 3 (b). MF for change in speed error Degree of MF Voltage Figure 3 (c). MF for voltage Table 2. Rule base Speed control ce/e NB NM NS Z PS PM PB NB NB NB NB NB NM NS Z NM NB NB NB NM NS Z PS NS NB NB NM NS Z PS PM Z NB NM NS Z PS PM PB PS NM NS Z PS PM PB PB Degree of MF Speed Error Figure 3 (a). MF for speed error PM NS Z PS PM PB PB PB PB Z PS PM PB PB PB PB 4. Space Vector Pulse Width Modulation : The basic power circuit topology of a three-phase voltage source inverter supplying a star connected three-phase load is given in Figure 4. The power circuit contains in general six semiconductor switches such as MOSFETs, IGBTs, BJTs etc with antiparallel diodes for protection. The two power switch of one leg is complimentary in operation with a small dead band between the switching of two devices. Switching operation of the inverter yield in total 8 output vectors with 6 being active or non zero and two zero vectors. The six active vectors are labeled as V 1, V 2, V 3, V 4, V 5,V 6 and the two zero vectors are labeled as V o and V 7. Change in speed error 86

3 PWM1 S1 PWM3 S3 PWM5 S5 a + Vdc - b N c PWM4 S4 PWM6 S6 PWM2 S2 The second equation is termed as equal volt-sec. principle. 2The Figure 4 Power Circuit topology of a three-phase VSI. 1If these 8 voltage vectors are converted to 2 axis, it can be plotted as shown in Figure 5. The tips of the 6 non zero vectors, when cornered form a regular hexagon with the two zero vectors lying at the origin. - axis inverter output voltage V k can assume only eight discrete locations in the complex plane, including the zero voltage vectors. The zero voltage vector will be included in the switching sequence to minimize the commutations in the inverter (Turn ON and Turn OFF losses will be less). 3One can generate any voltage vector laying inside the hexagon whose corners on the six active switching state vectors (V 1 to V 6 ) in space vector modulation strategy, the inverter out net V4(110) V3(010) V b V2(011) Vref av V1(001) V7(111) V0(000) - axis reference vector V ref can be approximated during a sampling time Δt = 1/(2f s ) by a sequence of 3 space voltage vectors V a, V b and V N, where V a and V b are 2 of the adjacent six active vector V 1...V 6 V N is a zero vector V o and V 7 chosen in such a way to minimize the commutations in the inverter f s is the switching frequency. The above time intervals T a, T b and T o during which the switching state vectors V a, V b and V N are applied are derived from the geometry of the hexagon and can be written as the following formulas V5(100) V6(101) Figure - 5 Space voltage vectors of a three-phase VSI. The V ref in α-β plane rotates circularly, so that the output voltage will be sinusoidal. Since the voltage source inverter can have 8 states, Vref can only be synthesized by using 8 voltage vectors. There can be infinite ways to synthesize the input reference but the most simple is by using the two neighboring active vectors and a zero vector. In other words it can be said that the inverter is switched in such a way that the two neighboring output voltage is generated. If the direction of rotation of the reference vector is assumed as anticlockwise then the vector to the right is designated with suffix a and the vector lying on the left of the reference is denoted with suffix b. The inverter switching is done is such a way that one state (say 001) remains for some time (say T a ) and is followed by another state (say 011) for some time (say T b ). The remaining time out of one switching period (T s ) is filled with the application of vector V o for time T 0 /2 and vector V 7 for time T 0 /2. Thus a symmetrical space vector modulation is obtained. If V ref is in 1 st sector, then, where, T a - Switching time for non zero vector (V1) in 1 st sector T b - Switching time for non zero vector (V2) in 1 st sector T 0 - Zero vector switching time (V o,v 7 ) in 1 st sector - Total switching time period T s 4where θ is the angle between V a and V ref, m is the modulation index. This is the generic solution for each sector in the plane, θ always varies in the interval (0-60 ). By varying the modulation index m and θ, the output voltage amplitude and frequency can be varied. Modulation index control the output voltage magnitude and θ controls the frequency of the output voltage. where, m - Modulation index θ - Vector Angle When equations for T a, T b & T o are implemented in digital signal PIC micro controller, the compare registers value corresponding to T a, T b & T o have to be calculated and loaded to generate the 6 PWMs for the three phase voltage source inverter. This results in 3 phase voltage output from a voltage inverter using space vector pulse width modulation. This SVPWM is used in vector control implementation when rotating reference frame operation is considered. 5. dspic MicroController: The dspic30f is a High Performance Digital Signal Controllers with CPU module has a 16-bit (data) modified Harvard architecture with an enhanced Instruction set, including significant support for DSP. The instruction set includes many addressing modes and was designed for optimum C complier efficiency. 87

4 A. Features 1. High performance modified RISC CPU Kbytes on-chip Flash program space (16K Instruction words) 3. 2 Kb of on-chip data RAM and 1 Kb of nonvolatile data EEPROM 4. 4 MHz- 10 MHz oscillator input with PLL active (4x, 8x, 16 as) x 16- bit working register array 6. Timer module with programmable presale 7. 6-bit Capture input and 16- bit Compare/PWM output functions 8. 2 UART modules with FIFO Buffer 9. 6 PWM output channels 10. Analog-to-Digital Converter (A/D) with 4 S/H Inputs For more about features of aspic refer respective data sheet. 6. Pulse Generation Using dspic A. Register Involved: 2010 International Journal of Computer Applications ( ) I/O Port control registers: All I/O ports have three registers directly associated with the operation of the port, where x is a letter that denotes the particular I/O port. TRISx: Data Direction registers, PORTx: I/O Port registers, LATx: I/O Latch registers. Each I/O pin on the device has an associated bit in the TRIS, PORT and LAT Registers. Timers: TMRx: 16-bit timer count register, PRx: 16-bit period register associated with the timer, TxCON: 16-bit control register associated with the timer. Some16-bit timers can be combined to form a 32-bit timer. Input capture and output compare: The Input Capture module has multiple operating modes, which are selected via the ICxCON register. The dspic30f device may have up to eight output compare channels, designated OC1, OC2, OC3, etc., Each output compare channel can use one of two selectable time bases. The time base is selected using the OCTSEL bit (OCxCON<3>). Motor control PWM control registers: The control registers are PTOCN, PTMR, PTPER, PWMCON and PDC. B. Flow chart: 7. Hardware Results: To evaluate the performance of the system, a series of measurements has been accomplished. Figure- 7 SVPWM By using the experimental setup we find the following results. Figure 7 show the Space Vector PWM. Figure. 8 (a, b) as shown speed response of the fuzzy logic controller with a fuzzy tuning rule based on Reference speed of 1000rpm and 1200 rpm. 88

5 Figure-8.a Figure-9.b Figure.10 a as shown step down up speed response for 1400 to1000 RPM of the proposed system Figure.10 b as shown step down speed response for 1000 to500 RPM of the proposed system. Figure-8.b Figure.9 a as shown step up speed response for 500 to1000 RPM of the proposed system. Figure.9 b as shown step up speed response for 1000 to1200 RPM of the proposed system. Figure-10.a Figure-9.a Figure-10.b 8. Conclusion This paper presents implementation of Real time MATLAB Interface for speed control of induction motor drive using dspic 30F4011. The experimental results are analyzed and, it s found that the speed of the induction motor can be controlled in Normal, step up, step down response. ACKNOWLEDGMENT The authors wish to thank the Management, Principal and the Department of Electrical and Electronics Engineering, Sona 89

6 College of Technology, Salem-5, TamilNadu who have given facilities to do this research work successfully. REFERENCE: 1) W. Leonhard, Control of Electrical Drives, Springer-Verlag Berlin Heidelberg, New York, Tokyo, ) Chuen Chien Lee, Fuzzy Logic in Control Systems: Fuzzy Logic controller Part1, IEEE.. 3) R.Arulmozhiyal and K.Baskaran, A Novel Approach to Induction motor speed control using FPGA,International Journal of Applied Engineering Research, ISSN , Volume 4, Number 1 (2009), pp ) R.Arulmozhiyal and K.Baskaran, Space vector pulse width modulation based speed control of Induction motor using Fuzzy PI controller, International Journal of Computer and Electrical Engineering, ISSN , Volume 1, Number 1 (2009), pp ) High Performance Digital Signal Controllers dspic30f Family Reference Manual and data sheet 6) International Journal of Computer Applications ( ) 90

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