ICS AMD - K8 System Clock Chip. Integrated Circuit Systems, Inc.

Transcription

1 Integrated Circuit Systems, Inc. ICS9545 AMD - K8 System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Output Features: 2 - Differential pair push-pull CPU 3.3V 9 - PCICLK (Including free 3.3V 3 - Selectable 3.3V - 3.3V - 3.3V fixed V V, 4.38MHz. Features: Programmable output frequency. Programmable output divider ratios. Programmable output rise/fall time. Programmable output skew. Programmable spread percentage for EMI control. Watchdog timer technology and RESET# output to reset system if system malfunctions. Programmable watch dog safe frequency. Support I 2 C Index read/write and block read/write operations. Uses external 4.38MHz crystal. Supports Hyper Transport Technology (HTTCLK). Functionality FS3 FS2 FS FS CPU HTT PCI MHz MHz MHz Pin Configuration *FS/REF 48 REF/FS* VDDHTT 2 47 GND 3 46 VDDREF REF2/FS2* GND 5 44 Reset# *ModeA/HTTCLK 6 43 VDDA *ModeB/PCICLK8/HTTCLK 7 42 GND PCICLK9/HTTCLK2 8 4 CPUCLK8T VDDPCI 9 4 CPUCLK8C GND 39 GND PCICLK/HTTCLK3 38 VDDCPU PCICLK 2 37 CPUCLK8T PCICLK3 36CPUCLK8C PCICLK4 35VDDCPU GND 5 34 GND VDDPCI 6 33 GND PCICLK27 32PD#* PCICLK MHz/FS3** VDDPCI 9 3 GND GND 2 29 AVDD48 2 PCICLK _48MHz/Sel24_48#* 2 PCICLK GND 2 PCICLK SDATA 2 PCICLK SCLK ICS SSOP * Internal Pull-Up Resistor 2 This Output has 2 Default Drive and can be programmaed lower via IIC

2 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION *FS/REF I/O Frequency select latch input pin / 4.38 MHz reference clock. 2 VDDHTT PWR Supply for HTT clocks, nominal 3.3V. 3 IN Crystal input, Nominally 4.38MHz. 4 2 OUT Crystal output, Nominally 4.38MHz 5 GND PWR Ground pin. 6 *ModeA/HTTCLK I/O Mode selection latch input pin / Hyper Transport output. 7 *ModeB/PCICLK8/HTTCLK I/O Mode selection latch input pin / PCI clock output / Hyper Transport output. 8 PCICLK9/HTTCLK2 OUT PCI clock output / Hyper Transport output. 9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V GND PWR Ground pin. PCICLK/HTTCLK3 I/O PCI clock output / Hyper Transport output. 2 PCICLK OUT PCI clock output. 3 PCICLK OUT PCI clock output. 4 PCICLK OUT PCI clock output. 5 GND PWR Ground pin. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK2 OUT PCI clock output. 8 PCICLK3 OUT PCI clock output. 9 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 2 PCI clock output. This output is 2 drive and can be programmed to lower drive OUT 2PCICLK4 via IIC. 22 PCI clock output. This output is 2 drive and can be programmed to lower drive OUT 2PCICLK5 via IIC. 23 2PCICLK6 OUT PCI clock output. This output is 2 drive and can be programmed to lower drive 24 2PCICLK7 OUT 25 SCLK IN Clock pin of I2C circuitry 5V tolerant 26 SDATA I/O Data pin for I2C circuitry 5V tolerant 27 GND PWR Ground pin. via IIC. PCI clock output. This output is 2 drive and can be programmed to lower drive via IIC _48MHz/Sel24_48#* I/O 24/48MHz clock output / Latched select input for 24/48MHz output. =48MHz, = 24MHz. 29 AVDD48 PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V 3 GND PWR Ground pin. 3 48MHz/FS3** I/O Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin 32 PD#* IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. 33 GND PWR Ground pin. 34 GND PWR Ground pin. 35 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 36 CPUCLK8C OUT Complimentary clock of differential 3.3V push-pull K8 pair. 37 CPUCLK8T OUT True clock of differential 3.3V push-pull K8 pair. 38 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 39 GND PWR Ground pin. 4 CPUCLK8C OUT Complimentary clock of differential 3.3V push-pull K8 pair. 4 CPUCLK8T OUT True clock of differential 3.3V push-pull K8 pair. 42 GND PWR Ground pin. 43 VDDA PWR 3.3V power for the PLL core. 44 Reset# OUT Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 45 REF2/FS2* I/O 4.38 MHz reference clock / Frequency select latch input pin. 46 VDDREF PWR Ref, TAL power supply, nominal 3.3V 47 GND PWR Ground pin. 48 REF/FS* I/O 4.38 MHz reference clock / Frequency select latch input pin. * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~.5 Drive Strength 2

3 General Description The ICS9545 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS9545 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2 C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to.mhz increment. Block Diagram PLL2 48MHz / 2 24_48MHz 2 TAL OSC REF (2:) PLL Spread Spectrum CPU DIVDER CPUCLKC (:) CPUCLKT (:) PD# SDATA Control PCI DIVDER PCICLK (7:, ) SCLK FS (3:) Logic Config. HTT DIVDER PCICLK(,9,8)/HTTCLK (3:) MODE (A,B) SEL24_48# Reg. HTTCLK 3

4 Power Groups Pin Number VDD GND Description 2 5 tal, POR 9 PCICLK, HTTCLK O/p 6,9 5,2 PCICLK Outputs 29 27,3,33 48 MHz, Fix Analog 35,38 34,39 CPU Outputs Analog, CPU PLL, MCLK REF, Digital Core Mode Functionality Tables ModeA ModeB Pin7 Pin8 Pin HTTCLK HTTCLK2 PCICLK HTTCLK HTTCLK2 HTTCLK3 PCICLK8 PCICLK9 PCICLK HTTCLK PCICLK9 PCICLK Table: Frequency Selection Table Bit3 Bit2 Bit Bit CPU HTT PCI FS3 FS2 FS FS MHz MHz MHz

5 General I 2 C serial interface information How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D2 (H) WR WRite Beginning Byte = N RT Repeat start Slave Address D3 (H) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N + - 5

6 I 2 C Table: Frequency Select Register Byte Pin # Name Control Function Type PWD Bit 7 - SS_EN Spread Enable RW OFF ON Bit 6 - SEL24_48MHz Output Select RW 48MHz 24MHz Latch Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved FS3 Freq Select Bit 3 RW Latch FS2 Freq Select Bit 2 RW Latch See Table: Frequency Selection Table Bit - FS Freq Select Bit RW Latch Bit - FS Freq Select Bit RW Latch I 2 C Table: Output Control Register Byte Pin # Name Control Function Type PWD Bit 7 REF Output Control RW Disable Enable Bit 6 6 HTTCLK Output Control RW Disable Enable Bit 5 7 PCICLK8/HTTCLK Output Control RW Disable Enable Bit 4 8 PCICLK9/HTTCLK2 Output Control RW Disable Enable Bit 3 PCICLK/HTTCLK3 Output Control RW Disable Enable Bit 2 2 PCICLK Output Control RW Disable Enable Bit 3 PCICLK Output Control RW Disable Enable Bit 4 PCICLK Output Control RW Disable Enable I 2 C Table: Output Control Register Byte 2 Pin # Name Control Function Type PWD Bit 7 7 PCICLK2 Output Control RW Disable Enable Bit 6 8 PCICLK3 Output Control RW Disable Enable Bit 5 2 PCICLK4 Output Control RW Disable Enable Bit 4 22 PCICLK5 Output Control RW Disable Enable Bit 3 23 PCICLK6 Output Control RW Disable Enable Bit 2 24 PCICLK7 Output Control RW Disable Enable Bit 28 24_48MHz Output Control RW Disable Enable Bit 3 48MHz Output Control RW Disable Enable I 2 C Table: Output Control Register Byte 3 Pin # Name Control Function Type PWD Bit 7 37,36 CPUCLK8T/C_ Output Control RW Disable Enable Bit 6 4,4 CPUCLK8T/C_ Output Control RW Disable Enable Bit 5 45 REF2 Output Control RW Disable Enable Bit 4 48 REF Output Control RW Disable Enable PCI_Str PCI9,8 Strength RW :.5 Drive :.5 Drive PCI_Str Control only RW :. Drive : 2. Drive Bit - PCI_Str PCI Strength Control RW :.5 Drive :.5 Drive Bit - PCI_Str only RW :. Drive : 2. Drive 6

7 I 2 C Table: Output Control Register Byte 4 Pin # Name Control Function Type PWD Bit 7 - PCIStr All other PCICLK RW :.5 Drive :.5 Drive Bit 6 - PCIStr Strength Control RW :. Drive : 2. Drive PCIStr PCICLK (7:6) Strength RW :.5 Drive :.5 Drive PCIStr Control RW :. Drive : 2. Drive PCIStr PCICLK (5) Strength RW :.5 Drive :.5 Drive PCIStr Control RW :. Drive : 2. Drive Bit - PCIStr PCICLK (4) Strength RW :.5 Drive :.5 Drive Bit - PCIStr Control RW :. Drive : 2. Drive I 2 C Table: Reserved Register Byte 5 Pin # Name Control Function Type PWD Bit 7 - Reserved Reserved RW Reserved Reserved Bit 6 - Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Reserved Reserved RW Reserved Reserved Bit - Reserved Reserved RW Reserved Reserved Bit - Reserved Reserved RW Reserved Reserved I 2 C Table: Byte Count Register Byte 6 Pin # Name Control Function Type PWD Bit 7 - BC7 RW Bit 6 - BC6 RW BC5 RW Writing to this register will configure how BC4 Byte Count RW many bytes will be read back, default is BC3 Programming b(7:) RW 6 = 6 bytes. BC2 RW Bit - BC RW Bit - BC RW I 2 C Table: Byte Count and Vendor ID Register Byte 7 Pin # Name Control Function Type PWD Bit 7 - REV_ID3 RW - - Bit 6 - REV_ID2 RW - - Revision ID REV_ID RW - - REV_ID RW - - Vendor_ID3 RW - - Vendor_ID2 RW - - Vendor ID Bit - Vendor_ID RW - - Bit - Vendor_ID RW - - 7

8 I 2 C Table: Skew Control Register Byte 8 Pin # Name Control Function Type PWD Bit 7 - PCI/HTTSkw3 RW : :5 :3 :45 Bit 6 - PCI/HTTSkw2 CPU-PCI/HTT 7 Step RW :N/A :N/A :N/A :6 PCI/HTTSkw Skew Control (ps) RW :N/A :N/A :N/A :75 PCI/HTTSkw RW :N/A :N/A :N/A :9 PCISkw3 RW : :5 :3 :45 PCISkw2 CPU-PCI 7 Step Skew RW :N/A :N/A :N/A :6 Bit - PCISkw Control (ps) RW :N/A :N/A :N/A :75 Bit - PCISkw RW :N/A :N/A :N/A :9 I 2 C Table: WD Time Control & Async Frequency Selection Register Byte 9 Pin # Name Control Function Type PWD Bit 7 - ASEL Async Frequency Select RW 66MHz 75.4MHz Bit 6 - AEN AGP/PCI/ Freq Source Select RW FI PLL CPU PLL Reserved Reserved RW - - Reserved Reserved RW - - Bit 3 - WDTCtrl Watch Dog Time base Control RW 29ms Base 6ms Base WD2 WD Timer Bit 2 RW These bits represent *29ms (or.6s) Bit - WD WD Timer Bit RW the watchdog timer waits before it goes to Bit - WD WD Timer Bit RW alarm mode. Default is 7 29ms = 2s. I 2 C Table: VCO Control Select Bit & WD Timer Control Register Byte Pin # Name Control Function Type PWD Bit 7 - M/NEN M/N Programming Enable RW Disable Enable Bit 6 - WDEN Watchdog Enable RW Disable Enable WDStatus WD Alarm Status R Normal Alarm WD SF4 RW WD SF3 RW Watch Dog Safe Freq Writing to these bit will configure the safe WD SF2 RW Programming bits frequency as Byte bit (4:). Bit - WD SF RW Bit - WD SF RW I 2 C Table: VCO Frequency Control Register Byte Pin # Name Control Function Type PWD Bit 7 - N Div8 N Divider Prog bit 8 RW The decimal representation of N Divider in Bit 6 - N Div9 N Divider Prog bit 9 RW Byte and 2 M Div5 RW The decimal representation of M and N M Div4 RW Divier in Byte and 2 will configure the M Div3 M Divider Programming RW VCO frequency. Default at power up = M Div2 bits (5:) RW latch-in or Byte Rom table. Bit - M Div RW VCO Frequency = 4.38 x [NDiv(9:)+8] Bit - M Div RW / [MDiv(5:)+2] 8

9 I 2 C Table: VCO Frequency Control Register Byte 2 Pin # Name Control Function Type PWD Bit 7 - N Div7 RW Bit 6 - N Div6 RW The decimal representation of M and N N Div5 RW Divier in Byte and 2 will configure the N Div4 N Divider Programming RW VCO frequency. Default at power up = N Div3 bit (7:) RW latch-in or Byte Rom table. N Div2 RW VCO Frequency = 4.38 x [NDiv(9:)+8] Bit - N Div RW / [MDiv(5:)+2] Bit - N Div RW I 2 C Table: Spread Spectrum Control Register Byte 3 Pin # Name Control Function Type PWD Bit 7 - SSP7 RW Bit 6 - SSP6 RW These Spread Spectrum bits in Byte 3 SSP5 RW and 4 will program the spread SSP4 Spread Spectrum RW pecentage. It is recommended to use SSP3 Programming b(7:) RW ICS Spread % table for spread SSP2 RW programming. Bit - SSP RW Bit - SSP RW I 2 C Table: Spread Spectrum Control Register Byte 4 Pin # Name Control Function Type PWD Bit 7 - Reserved Reserved R - - Bit 6 - SSP4 RW SSP3 RW These Spread Spectrum bits in Byte 3 SSP2 RW and 4 will program the spread Spread Spectrum SSP Programming b(4:8) RW pecentage. It is recommended to use SSP RW ICS Spread % table for spread Bit - SSP9 RW programming. Bit - SSP8 RW 9

10 Absolute Maximum Ratings Supply Voltage V Logic Inputs GND.5 V to V DD +3.8 V Ambient Operating Temperature C to +7 C Storage Temperature C to +5 C ESD Protection Input ESD protection usung human body model > KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7 C; Supply Voltage V DD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Input High Voltage V IH 2 V DD +.3 V Input Low Voltage V IL V SS V Input High Current I IH V IN = V DD 5 ma Input Low Current I IL V IN = V; Inputs with no pull-up resistors -5 ma Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 ma Operating Supply Current I DD(op) C L = pf; MHz 8 ma Power Down Supply C I L = pf; With input address to Vdd or DDPD Current GND 4 ma Input frequency F i V DD = 3.3 V; 6 MHz Input Capacitance C IN Logic Inputs 5 pf C IN & 2 pins pf Transition Time T trans To st crossing of target Freq. 3 ms Clk Stabilization T STAB From V DD = 3.3 V to % target Freq. 3 ms Skew T CPU-PCI V T =.5 V.5 4 ns Guaranteed by design, not % tested in production.

11 Electrical Characteristics - K8 Push Pull Differential Pair T A = - 7 C; V DD = 3.3 V +/-5%; C L =AMD64 Processor Test Load PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Rising Edge Rate δv/δt Measured at the AMD64 processor's 2 V/ns Falling Edge Rate δv/δt test load. V +/- 4 mv (differential 2 V/ns Differential Voltage V DIFF V Change in V DIFF_DC V DIFF Magnitude Measured at the AMD64 processor's -5 5 mv Common Mode Voltage V CM test load. (single-ended measurement).5.45 V Change in Common Mode Voltage V CM -2 2 mv Jitter, Cycle to cycle t jcyc-cyc wavefrom. Maximum difference of cycle 2 ps Measurement from differential time between 2 adjacent cycles. Jitter, Accumulated t ja Measured using the JIT2 software package with a Tek 744 scope. TIE (Time Interval Error) measurement technique: -,2,3 Sample resolution = 5 ps, Sample Duration = µs Measurement from differential Duty Cycle d t3 wavefrom % Output Impedance R ON transition. Used for determining series 5 55 Ω Average value during switching termination value. Measurement from differential Group Skew t src-skew wavefrom 25 ps Guaranteed by design and characterization, not % tested in production. 2 All accumulated jitter specifications are guaranteed assuming that REF is at 4.388MHz 3 Spread Spectrum is off

12 Electrical Characteristics - PCICLK T A = - 7 C; V DD = 3.3 V,+/-5%; C L = 3 pf PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH I OH = -8 ma 2. V Output Low Voltage V OL I OL = 9.4 ma.4 V Output High Current I OH V OH = 2. V -22 ma Output Low Current I OL V OL =.8 V 6 57 ma Rise Time t r V OL =.4 V, V OH = 2.4 V 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 5 ps Jitter t jcyc-cyc V T =.5 V 5 ps t jabs V T =.5 V 5 ps Guaranteed by design, not % tested in production. Electrical Characteristics - ZCLK T A = - 7 C; VDD=3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH V OH@MIN =. V, V OH@MA = 3.35 V ma Output Low Current I OL V =.95 V, V =.4 V 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 25 ps Jitter t jcyc-cyc V T =.5 V 3V66 25 ps 2

13 Electrical Characteristics - AGPCLK T A = - 7 C; VDD=3.3V +/-5%; C L = -3 pf (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output Frequency F O MHz Output Impedance R DSP V O = V DD *(.5) 2 55 Ω Output High Voltage V OH I OH = - ma 2.4 V Output Low Voltage V OL I OL = ma.55 V Output High Current I OH V OH@MIN =. V, V OH@MA = 3.35 V ma Output Low Current I OL V =.95 V, V =.4 V 3 38 ma Rise Time t r V OL =.4 V, V OH = 2.4 V.5 2 ns Fall Time t f V OH = 2.4 V, V OL =.4 V.5 2 ns Duty Cycle d t V T =.5 V % Skew t sk V T =.5 V 25 ps Jitter t jcyc-cyc V T =.5 V 3V66 25 ps Electrical Characteristics - REF T A = - 7 C; V DD = 3.3 V, +/-5%; C L = - 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Output High Voltage V OH5 I OH = -2 ma 2.6 V Output Low Voltage V OL5 I OL = 9 ma.4 V Output High Current I OH5 V OH = 2. V -22 ma Output Low Current I OL5 V OL =.8 V 6 ma Rise Time t r5 V OL =.4 V, V OH = 2.4 V 4 ns Fall Time t f5 V OH = 2.4 V, V OL =.4 V 4 ns Duty Cycle d t5 V T =.5 V % Jitter t jcyc-cyc5 V T =.5 V ps t jabs5 V T =.5 V 8 ps 3

14 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9545 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power- On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. Figure shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential. A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig. 4

15 N c INDE AREA e 2 D b E A A E h x 45 -C- - SEATING PLANE. (.4) C L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A b c D SEE VARIATIONS SEE VARIATIONS E E e.635 BASIC.25 BASIC h L N SEE VARIATIONS SEE VARIATIONS α 8 8 VARIATIONS D mm. D (inch) N MIN MA MIN MA Reference Doc.: JEDEC Publication 95, MO-8 3 mil SSOP Package -34 Ordering Information ICS9545yFLF-T Example: ICS y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 5

16 Revision History Rev. Issue Date Description Page #. 4/2/25 Updated Byte /2 M/N programming description 8-9 6