FlowCAD Schweiz AG. Tel. +41 (0) Fax +41 (0) Allegro Designer. OrCAD Standard. OrCAD Professional

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1 LICENSING AND SUPPORT Floating Networked License 12 Months Maintenance Support Included In Purchase Price SCHEMATIC ENTRY + DATA MANAGEMENT Graphical, flat and hierarchical page editor and Picture block hierarchy Marketplace to download apps PSpice AD Lite (up to 75 nodes) Net Groups - Complex bus definition AutoWire 44,000 Schematic symbols Coloured Components / nets Tcl TK scripting support Online design rule check including custom DRC capability and Waive DRC Forward and back-annotation of properties / pin-and-gate swaps Schematic Part and Library editor Cross-probing and cross-placing FPGA design-in / pin import & export Multiple PCB netlist interfaces SI Topology creation Digi-Key (PartLink App) Component Parametric data directly from web Property editor for pins, components, nets SigXplorer SI Intelligent PDF creation Updated in 17.2 Updated in 17.2 Updated in 17.2 Annotation New in 17.2 New in 17.2 New in 17.2 Design Compare (detail and Graphical) New in 17.2 New in 17.2 New in 17.2 Default Demo designs New in 17.2 New in 17.2 New in 17.2 Extended Preferences New in 17.2 New in 17.2 New in 17.2 Export ISCF (Intel Schematic Connectivity Format) New in 17.2 New in 17.2 New in 17.2 Export / Import XML New in 17.2 New in 17.2 New in 17.2 Altium Importer Schematic (PCB also available) Eagle Importer Schematic (PCB also available) PSpice AD Lite (up to 75 nodes) Component Information System Windows ODBC compatible format Interface to relational database and management systems Database query for part selection and parametric properties Schematic and BOM Variants Manager (Parts not Fitted and more). CIS Database Management Interface (access control and more) Part search DIGIKEY, FARNELL, FUTURE, MOUSER, ARROW CIS + CIP E CIS + CIP E CIS + CIP E CIS + CIP E CIP E CIP E PCB Suites Matrix Page 1/6

2 PCB EDITOR Physical, Spacing, Same net, Netclass and Class to Class rules Updated in 17.2 Updated in 17.2 Updated in 17.2 DFM Pad Entry / Exit Rules Updated in 17.2 Updated in 17.2 Updated in 17.2 Dynamic pad suppression / Unused Pad removal Updated in 17.2 Updated in 17.2 Updated in 17.2 Cross Section Editor Updated in 17.2 Updated in 17.2 Updated in 17.2 STEP 3D In/Out Updated in 17.2 Updated in 17.2 Updated in 17.2 Padstack Editor IPC2581 Compliant Updated in 17.2 Updated in 17.2 Updated in 17.2 Interactive Routing using Working Layer (layer selection popup) Multiple placement options, manual, quickplace, auto and room Placement directly from schematic, individually or window select Dynamic Shapes (dynamic copper pours) Plow and Heal Push, Shove and Hug interactive editing Embedded net names Curve Routing Auto Finish (Route Completion Tool) Through Board Transparency (OpenGL) Multi-line routing (Group Routing) Fan-out generators Flip Board Excellon NC Drill File export Gerber 274X, 274D artwork Output IPC2581 Import / Export Mentor ODB++ and universal viewer DFM Checks including soldermask, solderpaste and more Dynamic rat suppression Move with autoroute adjust (Slide) Route cleanup, optimization (Glossing) Impedance Calculator Interactive / Automatic Silkscreen generation Blind Buried Single Click multiple via instantiation Manual Design For Test (DFT) / Test Prep Component Height DRC Aligment x and y for components and modules Associative Dimensioning Split View Snake Routing for Hex pattern ICs STEP 3D viewer for selected item or complete PCB. MCAD/ECAD Incremental design data exchange (IDX) Import Altium PCB (schematic also available) Import EAGLE PCB (schematic also available) Import PADS & PCAD Import IFF RF Shapes Import Export IDF DXF STEP Application Mode (General, Etch, Placement) Application Mode (shape) Scribble Sketch Routing Full Skill Support Group route Bus Route and via patterns New in 17.2 PCB Suites Matrix Page 2/6

3 Line Fattening New in 17.2 New in 17.2 Differential Pair Static Phase Control rules New in 17.2 Differential Pairs Physical rules and routing New in 17.2 Propagation delay rules (Relative) for nets or groups Propagation delay rules (Min/Max) for nets or groups Dynamic Heads-up Display for critical rules Hug Contour routing (Flex) Shape based curve fillet support, tapered traces Placement replication, template based design reuse Constraint Regions, region based rules (Rigid-Flex; BGA Total Etch Length - Max/Min Length Delay Tuning Automatic Design For Test (DFT) / Test Prep Impedance Single Ended Worksheet Net Scheduling, T-Point rules (pin to T-point), T-Point Via array / Shielding - Shape and Trace based Extended (X)net rules Pin Pair rules Segment over void detection New in 17.2 Spread lines between voids New in 17.2 Multi Cross Section support for Rigid Flexi New in 17.2 New in 17.2 Rigid Flexi Zone Management New in 17.2 New in 17.2 Dynamic Zone Placement New in 17.2 New in 17.2 Inter Layer Checks for Rigid Flexi New in 17.2 New in 17.2 Layer set rules New in 17.2 Dynamic Phase Control rules CAD Translators - Import Mentor Boardstation Package Pin Delay (for die-2-die delay) rules New in 17.2 Z-Axis delay feedback New in 17.2 Max Via Count rules Dynamic DFA rules based interactive placement Offset Routing Design planning - Create hierarchical Bundles Design planning - Create, Edit Flows Design planning - Assign Flows to Layers Dynamic Shape based curve fillet support, tapered traces Backdrilling Updated in Plan Spatial Feasibility analysis & feedback - Generate Topological Plan - Convert Topological plan to traces (CLINES) Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push) Auto Interactive Break-out (AiBT) Automatic Delay Tune (AiDT) Automatic Phase Tune (AiPT) Remove Tuning PCB Suites Matrix Page 3/6

4 Timing Vision (Coloured tracks based on constraint adherence) High Speed Via Structures Tabbed Routing Single net Return Paths Vias Electrical Constraint rule set (ECSets) / Topology Apply Electrical rules (Reflection, Timing, Crosstalk) Constraints (formulas, relational) Fabric Weave Effect Zig Zag Auto Interactive Differential Pair Return Path Vias Constraint Manager: HDI rule set Micro-via and associated spacing, stacking and via-in-pad rules Constraint driven HDI design flow HDI micro-via stack editing Manufacturing rule support for embedding components Embed components on inner layers Support for Cavities on inner layers Support for Vertically placed components on inner layers Soldermask for embedded components Support for copy and swp embedded components Dual Side Contact Embedded Components Concurrent Team Design - Layer by Layer Concurrent Team Design - Functional block partitioning Concurrent Team Design - Team design dashboard Concurrent Team Design - Soft boundaries Concurrent Team Design - Constraint Editing and Netclasses per Partition Harmony Team Design New in New in 17.2 HS New in 17.2 HS New in 17.2 HS New in 17.2 Mini New in 17.2 Mini Harmony Team Design PCB Suites Matrix Page 4/6

5 Swap pins on a FPGA (based on FPGA rules) in PCB Editor Reoptimize pins on a FPGA (using FPGA rules) Parameterized RF etch elements Asymmetrical Clearances RF Etch elements editing Bi-Directional interface with Agilent ADS ADS schematics Import Agilent into DE-HDL Layout-driven RF design creation Flexible Shape Editor PSpice SIMULATION FPGA System Planner FPGA System Planner PSpice AD Lite (up to 75 nodes) Bias Point, DC sweep, AC sweep & transient analysis (with PSpice AD PSpice AD PSpice AD Parametric PSpice AD PSpice AD PSpice AD Learning PSpice Free Templates PSpice AD PSpice AD PSpice AD Analog behavioural modelling PSpice AD PSpice AD PSpice AD Stimulus editor PSpice AD PSpice AD PSpice AD Model Editor for device characterization PSpice AD PSpice AD PSpice AD Interactive waveform viewer & analyzer PSpice AD PSpice AD PSpice AD IBIS / DML model support PSpice AD PSpice AD PSpice AD Monte Carlo: Statistical circuit behaviour and yield (Worst Case) PSpice AD PSpice AD PSpice AD Bias point voltages, currents and power display on schematic PSpice AD PSpice AD PSpice AD Sensitivity: Identifies critical circuit components Optimizer: Optimizes key circuit components Monte Carlo: Statistical circuit behaviour and yield multiple measurements Smoke: Detects component stress Parametric Plotter: Examine solution through nested sweeps Optimize Circuits through Curve or Parameter Fit Example Design Simple Circuit 1 Example Design Simple Circuit 2 Example Design Simple Circuit 3 Example Design Simple Circuit 4 Example Design Simple Circuit 5 Example Design Simple Circuit 6 Example Design Simple Circuit 7 PCB Suites Matrix Page 5/6

6 SIGNAL INTEGRITY Pre- & Post-route signal integrity analysis Graphical topology definition and exploration Interactive waveform viewer Macro modelling support (DML) IBIS 5.0 support IBIS ICM model support Spectre-to-DML HSPICE-to-IBIS Lossy transmission lines Coupled (3 net) simulation Differential pair exploration and simulation AUTOROUTER 6 Signal Layers at a time (no board layer limit or pin limit) Shape-based or Gridded routing SMD Fanout Trace Width by Net and Net Classes 45-degree / Memory Pattern Routing Interactive Routing with Shoving and Plowing Interactive Floorplanning Online Design Rule Checking Flip, Rotate, Align, Push, and Move Components Placement Density High-Speed rules based autorouting Min/Max, matched length rules based autorouting Pin-pair rules, Area rules based autorouting Crosstalk controls, parallelism rules based autorouting Differential Pair Autorouting, Automatic net shielding High-speed rules-based autorouting 256 signal layer limit AI DFM rules-based autorouting Automatic trace spreading ATP generation Layer-specific rules-based autorouting PCB Suites Matrix Page 6/6

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