DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK

Transcription

1 DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK Submitted by Dennis Weston for the degree of BSc (Hons) Computer Science 2006

2 DC CIRCUIT ANALYSIS OF INTEGRATED CIRCUITS FOR THE LYRIC PHYSICAL DESIGN FRAMEWORK Submitted by Dennis Weston COPYRIGHT Attention is drawn to the fact that copyright of this dissertation rests with its author. The Intellectual Property Rights of the products produced as part of the project belong to the University of Bath (see This copy of the dissertation has been supplied on condition that anyone who consults it is understood to recognise that its copyright rests with its author and that no quotation from the dissertation and no information derived from it may be published without the prior written consent of the author. Declaration This dissertation is submitted to the University of Bath in accordance with the requirements of the degree of Bachelor of Science in the Department of Computer Science. No portion of the work in this dissertation has been submitted in support of an application for any other degree or qualification of this or any other university or institution of learning. Except where specifically acknowledged, it is the work of the author. Signed...(Dennis Weston) This dissertation may be made available for consultation within the University Library and may be photocopied or lent to other libraries for the purposes of consultation. Signed...(Dennis Weston)

3 Abstract In today s world, integrated circuits, or microchips, are all around us and affect almost everything we do. They are found in all our electrical products from everyday systems like our computers and our washing machines to the important anti-lock brakes in our cars. Engineers who design these microchips need to make sure they are reliable, especially in safety critical systems such as the flight systems of aeroplanes, before they are manufactured. Circuit analysis of microchip designs can highlight areas which may be unreliable due to the problems of IR drop and electromigration, which can then be corrected by the circuit designers. This project concentrates on designing and implementing a DC circuit analysis system to be used with a specific microchip design tool - the Lyric Physical Design Framework - to enable users to provide reliable chip designs before the cost of manufacture and testing is incurred.

4 Acknowledgements Dr Marina De Vos For being my project supervisor and providing advice and guidance Dr Peter Shepherd For proof reading and providing guidance from an electrical engineering standpoint Dr Alwyn Barry For support and advice through some difficult times The staff at Pulsic Limited, especially Jeremy Birch For giving me their time and resources to help me complete this project My family For their ongoing love and support David Taylor and James Steward For always being available to chat and trying to keep my spirits high when I was feeling low i

5 Contents 1 Introduction Integrated Circuits Electronic Design Automation Lyric Physical Design Framework Scope Aims Document Structure Literature Review Chip Reliability Circuit Analysis Circuit Analysis in Lyric Existing Circuit Analysis Systems ECAP II SPICE Other algorithms Kron s Method of Tearing Cholesky Factorisation Hierarchical Analysis Algorithm Random Walk Algorithm Hierarchical Random Walk Algorithms Conclusions Requirements Analysis and Specification Requirements Analysis Type of Circuit Inputs Outputs Speed Accuracy Reliability Platform Versatility Security User Interface Heat Map Requirements Specification ii

6 3.2.1 Functional Requirements Non-functional Requirements Constraints Hardware Constraints Software Constraints Time Constraints Summary Tools and Technologies Programming Languages C C Java Python Conclusion Integrated Development Environments (IDEs) Compilers Debuggers Revision Control Systems Backing Up Files Testing Technologies Summary High Level Design System Structure Initial Circuit Analysis Algorithm Matrix Inversion Algorithms Iterative Circuit Analysis Algorithm Units To Be Used Data Structures GUI Summary Low Level Design and Implementation Code Files Types Data Structures Matrices Circuit Elements Filling the Data Structures Modified Nodal Analysis Algorithm LU Decomposition Algorithm Iterative Circuit Analysis Algorithm Current Calculation GUI implementation Intermediate Testing Results Summary iii

7 7 System Testing Test Strategy System Accuracy Speed of the Iterative Algorithm Multi-platform Ability Reliability Usability Testing Summary Conclusion Meeting Requirements Positive Aspects Things That Could Be Improved Future Work Full Chip Analysis Accommodation of Active Circuit Elements AC Circuit Analysis Heat Maps Beyond Circuit Analysis Bibliography 68 A Example ring and mesh from an IC design in Lyric 72 B Screenshots 73 C Test Plan 76 D Circuit Designs for Testing Purposes 78 D.1 Test Design D.2 Test Design E Test Results 80 E.1 System v PSpice using Test Design E.2 System v PSpice using Test Design E.3 Multiple Platform Testing using Test Design E.4 Multiple Platform Testing using Test Design F Output Files from System Testing 82 F.1 Windows XP Pro using Test Design F.2 Windows XP Pro using Test Design F.3 Solaris 8 using Test Design F.4 Solaris 8 using Test Design F.5 SuSE Linux 9.0 using Test Design F.6 SuSE Linux 9.0 using Test Design F.7 Diff of the Output Files of MNA and Iterative Algorithms G Code Listings 90 iv

8 G.1 input.h G.2 input.c G.3 mna.h G.4 mna.c G.5 iterate.h G.6 iterate.c G.7 current.h G.8 current.c G.9 output.h G.10 output.c G.11 utilities.h G.12 utilities.c G.13 nodalanalysis.h G.14 nodalanalysis.c G.15 mna interface.h G.16 mna interface.c G.17 Segment of code used to interface the system with Lyric v

9 Chapter 1 Introduction 1.1 Integrated Circuits An integrated circuit is a thin chip consisting of at least two connected electronic components, such as resistors, capacitors and, most commonly, transistors. Typical integrated circuits these days are smaller than a squared centimetre in size and can contain millions of interconnected devices. In today s world integrated circuits (IC s) or chips are all around us and affect almost everything we do. We find them in our computers, our washing machines, our mobile phones - in all electrical equipment. The engineers who design such chips want to ensure that they will be reliable, especially when they are involved in such critical processes such as the flying of an aeroplane or the operation of ABS brakes in a car. A chip failure in one of these applications could cause fatalities and expensive lawsuits plus the cost of recalling/repairing the affected chips. In order to avoid failures, it used to be the case that chips were produced and tested to verify their reliability before going into full production, however this is an expensive and time consuming solution. Therefore chip designers prefer a software tool which can check the reliability of a chip design before it even gets put into production. 1.2 Electronic Design Automation Electronic Design Automation (EDA) is a category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to in- 1

10 tegrated circuits [38]. This basically means using computer programs to design, lay out, verify and simulate the performance of electronic circuits on chips and PCBs [9]. Due to the continuous scaling of semiconductor technology as governed by Moore s Law, EDA tools have become increasingly important in the design of microchips; without EDA tools there would be nowhere near the number of electronic devices on the market as there are today. 1.3 Lyric Physical Design Framework The Lyric Physical Design Framework, from here on shortened to Lyric, is an EDA tool produced by a company called Pulsic Limited and is the software which this project seeks to improve. Lyric is defined as: a high performance auto-interactive IC physical design solution for analog, custom, digital, mixed-signal, embedded DRAM/SRAM and system-on-chip (SoC) design - incorporating solutions for ECO placement, routing, timing closure, signal integrity and power routing [17] Lyric is a complicated tool, but in simple terms it allows chip designers to layout the electrical components required for a particular chip and connect all the components together with interconnects in a process called routing in order to produce a complete chip design. To ensure Lyric produces reliable chip designs, it needs to incorporate some software tools that will analyse the design, looking for the issues that can cause chip failure. The results of the analysis should then be reported to the design engineers who can make the necessary corrections. This encapsulates the focus of this project. 1.4 Scope The domain of this project is a large one as the reliability of a microchip can be influenced by many factors including the correctness of the logic of the chip and errors in the chip introduced during the manufacturing process. However, in order to limit the scope to a manageable level, this project will only be concerned with the important errors which are caused by an excess of current (electromigration) or a reduction of voltage (IR drop) across the circuitry. These errors will be described in more detail in Chapter 2, as will the process of circuit analysis which is a technique to find these errors and the basis of the final system. 2

11 This still leaves a large domain however, for instance there are two types of circuit to think about, alternating current (AC) and direct current (DC). The circuit analysis for DC is done in the time domain while AC analysis is done in the frequency domain. For the purposes of limiting the broadness of the project and to ensure the goal are achievable, the project will only be concerned with DC circuits. 1.5 Aims The aim of this project is to design a library of functions that will analyse the circuitry of an integrated circuit design to discover any issues that may cause the chip to become unreliable. This library should be able to be integrated into the Lyric Physical Design Framework software as an analysis tool and be able to show graphically the results of its analysis in the Lyric graphical interface. Another major aim, garnered from preliminary discussions with Pulsic Limited, is to ensure the tools provides the ability to quickly re-analyse a chip design after it has initially been analysed and the design edited. This is important as design engineers quickly want to see the effects of any alterations they make to a design as Lyric is a real-time interactive tool. It is aimed that the analysis tool will produce accurate results and produce said results in a timely fashion comparable to any similar tools on the market. It is also intended that the tool be easy to use for a professional IC design engineer and that the results produced be displayed in a clear and obvious manner. 1.6 Document Structure The next chapter is the literature review which outlines the issues that can cause unreliability in microchip designs and then goes on to investigate the methods of analysing electrical circuits, any current technology that provides similar functionality and existing algorithms which may be useful in the designing of the new tool. Following on from the literature review is the requirements chapter which studies the task at hand in detail and outlines the exact aims of the project. Further on in the document comes the high-level design chapter and then the chapter detailing the detailed design and implementation of the system. Chapter 6 looks at the testing of the produced system to assertain how well the finished product meets up with the requirements. The document closes with an 3

12 evaluation of the project as a whole and provides recommendations for future work. 4

13 Chapter 2 Literature Review 2.1 Chip Reliability As outlined in the scope of the project in Section 1.4 on page 2, this project will be concerned with the important reliability issues caused by IR (voltage) drop and electromigration. Here these issues will be described in detail, looking firstly at IR drop. The voltage supplied to a chip needs to be carried around the chip effectively in order to provide the power for the electronic components to function. IR drop is due to the resistance of the metal lines of the power network [24] resulting in lower voltages reaching parts of the chip than intended. If there is an excessive drop in the value of the voltage at some node on the chip compared to that which was supplied then there is a problem in the design of the chip as the power is being wasted. With the size of chips getting smaller and the amount of voltage being supplied being lowered proportionally, even a small drop in voltage across a chip can be significant [25]. Drop in voltage can lead to delays in the circuit causing slower performance and also cause logic failures and the inability of some components to function properly since they aren t receiving enough power. Traditional methods for detecting this voltage drop cannot handle today s large designs [43] and so are useless for ensuring designs are reliable. An alternative solution is to use electron beam and focused-ion beam studies [43] but the costs involved in these processes can be debilitating in today s market environment. Therefore an effective software tool which can detect voltage drop during the design phase is invaluable. Second, is the problem of electromigration in the interconnects (microscopic aluminium wires) that join up the electrical components on a chip. Electromigration research was pioneered by James R Black. He defined the phenomenon as the 5

14 Figure 2.1: a) A void forming. b) hillocking - short circuits forming [22] transport of mass in metals when the metals are stressed at high current densities [1], where current density is the ratio of current to the cross-sectional area of a conductor. In integrated circuits where the interconnects are now usually less than 130 nanometres in width and carry a relatively high current, the current density is high. Inside the interconnects, atoms of the metal are being bombarded as an electron wind (current - a flow of electons) [1] tries to rush through it. This results in collisions in which electrons pass on their momentum to the atoms and pushes them out of position. If this happens enough over a period of time, a sufficient amount of atoms will be moved far enough to cause the wire to physically snap, creating what is known as a void [37] and breaking the circuit. (See Figure 2.1. a ) Another outcome of electromigration is that atoms of a connecting wire could be forced into piling up and drifting outward from the metal and possibly join up with a nearby interconnect. This is known as hillock failure or whisker failure (short circuit) [37] and is likely to cause the chip to malfunction. (See Figure 2.1. b ) In order for the two outlined possible causes for chip failure to be avoided, the chip designer needs to know the voltage at every node in the circuit and also the current that flows through each of the interconnecting wires. Knowledge of the voltage across the circuit will allow the designer to see where power is being leaked and so amend the chip design accordingly. Knowledge of the currents at all points across the circuit will show where the current is too high and enable the designer to fatten the wires to reduce the current density and so reduce the risk of electromigration. The solution to avoiding these problems is to perform circuit analysis on the electrical circuits in a chip design in order to spot where such problems might occur and alter the design accordingly. 6

15 2.2 Circuit Analysis Circuit analysis is the study of electrical circuits in order to predict the electrical behaviour of physical circuits [7]. Before explaining circuit analysis, here are a few useful definitions: a node is a point in a circuit where three or more wires meet [20], a branch is any path in the circuit that has a node at each end and contains at least one voltage source or resistor but contains no other nodes [20], a loop is where nodes and branches form a ring in a circuit. There are many different forms of circuit analysis, but as detailed in the project proposal, this project has limited its scope to deal with dc circuits only, so only dc circuit analysis will be described in this report. The circuits are assumed to comprise of one or more voltage sources, zero or more current sources and one or more resistors. The resistors are assumed to be the branches (wires) of the circuits themselves. In order to conduct circuit analysis on an electrical circuit, there are some basic electrical laws which need to be used. The most fundamental of these is Ohm s law. Ohm s law states that the voltage across a resistance is directly proportional to the current flowing through it. The resistance, measured in ohms, is the constant of proportionality between the voltage and current [13]. The mathematical relationship of Ohm s law is illustrated by Equation 2.1. V (t) = R I(t), wherer 0 (2.1) which is usually simplified to Equation 2.2. V = I R (2.2) Ohm s law provides the tools for analyzing simple circuits, but for more complicated circuits, such as those you would find in a microchip design, there are two further fundamentals called Kirchhoff s laws. The first law is Kirchhoff s current law (KCL), which states that the algebraic sum of the currents entering any node is zero [13]. For example, applying Kirchhoff s law to the node in Figure 2.2 yields Equation 2.3: i 1 + i 4 i 2 i 3 = 0 (2.3) The second law is Kirchhoff s voltage law (KVL) which states that the algebraic 7

16 Figure 2.2: Four branches connected to a node sum of the voltages around any loop is zero [13]. This means that the sum of the voltage drops through the resistors equals the sum of the voltage rises through the voltage sources [21]. Kirchhoff s laws in conjunction with Ohm s law can be applied to a complex electrical circuit with multiple loops and nodes in order to determine the voltages and currents at all nodes and branches of the circuit. There are two predominant methods of doing this - nodal analysis and mesh (or loop) analysis. In nodal analysis, the variables in the circuit are selected to be the node voltages. One node is selected as the reference node and all other node voltages are defined with respect to that node [13]. This node is called the ground node and is assigned a voltage of zero [19]. The process then continues by iterating through the nodes in the circuit and applying Kirchhoff s current law to each of them. The result is a system of m linear equations in the m unknown voltages (where m is one less than the number of nodes). The equations are of the form: where G 11, G 12,..., G mm and I 1, I 2,..., I m are constants [19]. The equations can be considered a matrix and then solved with Gaussian elimination or some other method giving the voltages for all the nodes. With the node voltages known, the currents along each branch can easily be determined using Ohm s law. In mesh analysis, the unknown parameters are the current values and Kirchhoff s voltage law is used to determine them [13]. The method starts by identifying all the loops in the circuit (see Figure 2.3 for a basic diagram). The loops are then taken one at a time and KVL equations formed for each, 8

17 producing a system of equations of the form: where R 11, R 12,..., R mm and V 1, V 2,..., V m are constants [18]. As with nodal analysis, these equations can then be solved as a matrix and the voltage values determined using Ohm s law. The choice of which method to use is often dependent upon the circuit to be analysed. If the circuit had fewer nodes than loops, then nodal analysis would be preferable as it produces fewer equations to solve. For the same reason, mesh analysis would be preferable if there are fewer loops than nodes. One other consideration to make is that mesh analysis can only be applied to circuits which are planar, i.e circuits which can be drawn in two dimensions [34]. What this means is that wires in a circuit must not jump over one another in order to apply mesh analysis. For this reason nodal analysis is most commonly used in circuit analysis software, since it is always guaranteed to work. 2.3 Circuit Analysis in Lyric Currently, Lyric does not include a mechanism with which to analyse circuits in microchip designs which contain loops. Since the circuits in chip designs are usually very complicated with lots of loops, this is quite a problem. At the moment, Lyric only has a very basic tool with which to analyse only parts of the circuits where no loops occur. According to Jeremy Birch, Chief Technology Officer at Pulsic Limited, Lyric currently employs a basic dendritic method for circuit analysis. It is called dendritic as it follows a simple tree/branching strategy and takes as input nodes at Figure 2.3: Loops in a basic circuit [18] 9

18 Figure 2.4: Simple dendritic analysis strategy for determining branch currents which the current is known and then it is easy to work out the currents that flow through the branches. For example, in Figure 2.4 it is known that 5mA are entering the branch at X and that devices at Y and Z draw 3mA and 2mA respectively, then the value of current which flow through the branches are obvious. As this method only works for the most basic of examples, Lyric is in need of a proper circuit analysis tool, which is the purpose of this project. A key feature for any such tool is that it needs to be interactive - that is, it should quickly show how small changes to the circuit effect how the circuit behaves. This is important so chip designers can create reliable designs. Computer-based circuit analysis tools have been developed since the 1960 s. In order to understand how circuit analysis tools work and the methods and technologies available, a few circuit analysis tools are explored here. 2.4 Existing Circuit Analysis Systems ECAP II ECAP II, Electronic Circuit Analysis Program, is a circuit analysis program that was first devised in It has no graphical user interface and instead features an input language for users to enter the details of a circuit design, with FORTRAN sub-routines [2]. The method by which the program carries out circuit analysis is not by using nodal analysis or mesh analysis but rather by a process called the mixed method. This method utilises the idea that Ohm s law can be expressed in a matrix form involving the admittance matrix for certain branches of the circuit and the impedance matrix for the rest of the branches [3]. Impedance is an ac circuit term which is analogous to resistance in a dc circuit and admittance is analogous to conductance in dc circuits which is the reciprocal of resistance [13]. 10

19 The admittance branches are then analysed with a method called the cutset method and the impedance branches by the mesh method. The two sets of linear equations are then combined into one matrix and solved. The method of solution, rather than using the straight-forward Gaussian elimination, uses implicit integration based on the variable order approach of Gear [10] as modified by Brayton et al [4]. This method approximates a solution and then iterates - converging towards the actual solution. This only takes one or two iterations for a dc problem [2] and is faster than the Gaussian approach. An advantage of ECAP is that it contains a modify feature [3] which is based on Kron s tensorial method as explained later in this paper. The modify feature allows the matrix of solutions for a circuit to be updated in relation to changes in some branch resistances with only trivial computation compared to re-calculating the entire solution from scratch. This is a feature that is needed for a circuit analysis tool for Lyric since it needs to be an interactive design tool and so this method could be adopted. A possible disadvantage of this program is the complex method by which the systems of equations are constructed and solved. It would be much simpler to construct the matrices using nodal analysis and solve them using Gaussian elimination. It s true that ECAP s method is faster but is this increase in complexity worth the time gain? Also, with the speed of modern computers the increase, in speed may be minimal SPICE SPICE, Simulation Program with Integrated Circuit Emphasis, is a circuit simulation program developed in the 1970 s at the University of California, Berkeley. It is a derivative of another circuit analysis program, CANCER, that was also developed at Berkeley [23]. SPICE is the most widely used circuit analysis program in the market place and has many derivatives of its own such as SPICE2, SPICE3 and PSPICE which is the pc version of the software owned by Cadence Design Systems. Like ECAP, SPICE was designed to have no user interface as standard and was used via an input language. Programs were written in the input language, saved and then compiled into an executable [8]. SPICE took as input a netlist file which describes the circuit, which was then fed to the executable to perform the analysis. More recent incarnations of SPICE have a full graphical user interface and circuit designs can be entered into the system by placing circuit components onto a canvas to form a schematic for the circuit. The way SPICE works is shown in the block diagram in Figure 2.5. At the heart 11

20 Figure 2.5: The SPICE flow diagram [8] 12

21 of SPICE is nodal analysis as seen in steps 3 and 4. For linear dc circuits, these are the only stages that are necessary. The inner loop, steps 2-6, iterates to find the solution for non-linear dc circuits, while the outer loop, 7-9, extends the process for ac analysis. As this project s scope is only linear dc circuits, steps 3 and 4 are the important ones. As mentioned above, SPICE s analysis mechanism of choice is nodal analysis. SPICE creates the matrices for the systems of equations in the form with the G matrix being a matrix of the conductances (1/resistance), the I vector being a vector of branch currents and the V vector being the vector of the node voltages. The V vector is where the solutions will appear at the end of the analysis. SPICE uses a shortcut called matrix construction by inspection to create the matrices rather than creating a system of nodal equations using Kirchhoff s current law. This inspection method allows SPICE to create the system matrices as each element is read in from the input file at the start of execution. Matrix construction by inspection builds the system matrices and identifies the location of each element in the matrices as soon as the nodes connected to the element are defined [15] For solving the matrices, SPICE uses a form of Gaussian elimination called LU (or triangular) decomposition. This method of solution is faster than normal Gaussian elimination. Standard Gaussian has a complexity of O(n 3 /3) whereas LU decomposition has a complexity of O(n 3 /3 -n/3) where n is the number of rows in the matrices [14]. Later incarnations of SPICE replaced nodal analysis with an improved system called Modified Nodal Analysis (MNA). MNA was designed to rectify the shortcomings of standard nodal analysis. These drawbacks include the fact that nodal analysis treats voltage sources inefficiently and is incapable of including currentdependent elements. Another issue is the fact that the nodal method does not produce the currents through the independent voltage sources as part of the output [12]. These have to be calculated later using Ohm s law at each of the circuit nodes and so adds to the computation required. 13

22 MNA resolved all of the problems of the nodal approach while preserving its advantages [12]. MNA produces the currents through the voltage sources as well as the node voltages as part of its output while also reducing the complexity of computation. While the order of the matrix equation is increased (the algorithms only overhead), the equations are generally highly sparse and can take advantage of efficient routines to solve sparse matrices. Also MNA indicates the most efficient ordering for the LU decomposition process, speeding up the process of finding the solutions [32]. Results from [12] shows MNA outperforms another common approach to circuit analysis - the tableau method. The advantage of SPICE s mechanism is that it uses algorithms which are reliable and easy to use. The algorithms have been around for decades and are proven to be useful and there is also a lot of supporting literature which would be useful in implementing a SPICE-like system in Lyric. The disadvantages include the fact that an O(n3) algorithm on matrices with thousands of lines may take a fair amount of time to compute. Also, unlike ECAP, SPICE does not allow quick re-analysis when there have been small changes to the circuitry, the analysis has to be restarted from the beginning which takes time. Quick re-analysis is fundamental to any analysis tool to work well with Lyric. It may be useful to use some of SPICE s methodology to create a circuit analysis tool for Lyric but it is not the whole answer. 2.5 Other algorithms Kron s Method of Tearing This method invented by [16] is supposed to make it possible to solve very large physical problems in easy stages. The method involves tearing a large system of equations up into a large number of small subdivisions, solving each subdivision separately and then interconnecting the partial solutions by a set of transformations to obtain the solution of the original system [16]. It is important that the tearing is carried out such that each component part produced is independent of every other part so that each can be solved independently before amalgamating them to form the whole solution. The main advantage of this tearing (or tensorial) technique is that the amount of computation required to solve the system of equations is reduced by a significant amount. For example, taking the system I = YE, where I, Y and E are matrices, and dividing it into n parts, calculating the inverse E = ZI is reduced by a factor 14

23 of 2/n 2 [16]. 1/5000. If n = 100, the calculations are reduced to a fraction of about Other advantages include the fact that if several of the subdivisions are identical, the reduction in computation increases dramatically. Also, if a system is already solved and is then altered in any manner, the solution of the altered system need not be started from scratch. Only the solutions of the altered portions are changed, the rest of the solutions remaining unchanged [16]. In [3], a method is presented by which Kron s method may be used to study the effects of varying a single resistance in a circuit. This method permits the nodal solution matrix to be updated in accordance with changes in one or more branch resistances. This feature would be very good in a circuit analysis system built for Lyric as it would allow quick recalculation of the circuit properties as the engineers make changes to their designs. It is also stated in [3], however, that using this technique to compute a sequence of solutions as a given resistance is varied through several different values may introduce round-off errors that accumulate from one step to the next. This would invalidate the results acquired from the analysis. This implementation of Kron s tensorial method may provide an ideal solution to quickly calculating the affects of small changes made to a circuit by chip designers. It remains to be seen however if the round-off errors can be avoided Cholesky Factorisation Cholesky factorisation is a technique for solving sparse matrices. The method states that if matrix A is positive definite, then there exists a unique lower triangular matrix G with positive diagonal entries such that A = GG T [11]. This method does not require pivoting as in the LU decomposition method for solving matrices and hence its performance is twice as fast [31]. The technique is also fairly easy to implement, however it can only be used on matrices that are symmetric and positive definite Hierarchical Analysis Algorithm This algorithm is based on the well-known strategy of divide and conquer and compromises the following: (1)The power grid is divided up into local and global grids, (2) macromodels are generated for the local grids, (3) the admittance (1/resistance) matrix is sparsified, (4) the global grid is modelled using the local 15

24 grids and finally, (5) simulating the local grids where desired [44]. As with other divide and conquer algorithms, this method benefits from solving many simple problems rather than one large problem. Further improvements in computation are gained by the sparsification of the matrices so that they may be solved quickly using efficient sparse matrix solving algorithms. [44] shows that the hierarchical analysis method is significantly faster than conventional non-hierarchical methods. The disadvantage of this method is that implementation may be difficult due to the complex nature of the algorithm. Also, the algorithm relies on a hierarchical structure in the design of the circuit which often may not be the case Random Walk Algorithm This is a new method for analysing circuits, more specifically power grids, based on the relationship between random walks and electrical networks [27]. The method is inspired by the work of Doyle and Snell [28] which interprets the relationship between resistive networks and probabilities. [27] shows that using Kirchhoff s laws, the voltage at any node in a circuit is a linear function of the voltages at its neighbours. This is analogous to a random walk problem so that for any power grid problem, a mathematically equivalent random walk problem can be constructed i.e characterised by the same set of equations [27]. By finding an approximate solution to the random walk problem, an approximate solution to the circuit problem is also found. The solution is found by conducting a certain number of experiments on the random walk and averaging out the voltages returned to give the approximated solution. If this amount is averaged over a sufficiently large number of walks by playing the game a sufficiently large number of times, by the law of large numbers [42], an acceptably accurate solution can be obtained [27] There is an accuracy-runtime trade off with this algorithm that means the more accurate the solution you want, the longer it will take to compute. The number of walks carried out, and so the accuracy of the solution, is governed by a user specified variable. This algorithm should be capable of an accuracy of above 99% however. The advantages of this algorithm include the speed at which a solution is found. 16

25 The algorithm has linear complexity [27] and so when testing against other methods is found to be much faster. Another plus point is that the algorithm localises computation; it can calculate a single node voltage without having to solve the whole circuit which is a desirable feature in an interactive design and analysis tool. A disadvantage of this method is that the algorithm seems to be fairly complex and so implementation might be difficult. Also the algorithm only produces node voltages so the branch currents would have to be worked out afterwards using Ohm s law, which adds to the computation time. The other disadvantage is that the results are close approximations rather than actual voltages and so there is a small margin of error introduced Hierarchical Random Walk Algorithms The hierarchical random walk algorithms combine the divide and conquer idea of the hierarchical analysis algorithm with the random walk method [28]. This method proves to work roughly three to four times faster than the standard random walk method while also being more robust. While being very fast this algorithm does have the drawback of being more complicated to implement than the two algorithms it is based on. It also has the same problem that the branch currents are not calculated as part of the analysis and so will have to be done separately at the expense of extra computation. 2.6 Conclusions The method as employed by SPICE is the most easy to understand and implement while being the best supported and probably the most reliable. However, as it is not a suitable solution as an analysis tool in an interactive design environment, it cannot be the whole solution for this project. Using the SPICE method as first pass analysis would provide a good base for further analysis. Then Kron s tensorial method or a random walk algorithm or some other similar algorithm could be useful for providing quick re-analysis when small changes are made to the circuit. 17

26 Chapter 3 Requirements Analysis and Specification 3.1 Requirements Analysis This chapter aims to determine all the goals of the system to be created and set them out as a specification for the design stage. The best way to elicit the requirements for a new software system is to enlist the help of the experts in the area. Since this circuit analysis system is to be incorporated into the Lyric Physical Design Framework, it makes sense to talk to the engineers at Pulsic Limited who make the software and therefore know what they want from a new tool. Jeremy Birch is a co-founder of Pulsic and currently works as the Chief Technology Officer. He is widely recognised within the company to be the foremost expert on the software and has been the principal contact within the company for this project. The documentation of the requirements process here comes largely from discussions with Jeremy Birch, with some input from a few other employees Type of Circuit As mentioned in Section 1.4 on page 2, this project is focussing just on the DC aspect of IC circuits and ignoring the AC aspect in order to help set a manageable task. This still leaves a very large scope for the project, so it needs further refining. Electrical circuits can contain active devices and passive devices. Active devices are either sources of energy, driving electrical current around the circuit and hence delivering continuous energy to it [33], or else they have the ability to control the 18

27 flow of electricity. The most common active device is the transistor. Passive devices are those which consume energy rather than produce it, like resistors, inductors and capacitors [33]. Since active devices control the flow of electricity, they are much harder to model than the passive devices which only consume it. To make this project of achievable size, the circuit analysis tool that is to be produced will operate on circuits consisting of passive elements only. Further more, since modern integrated circuits can contain more than ten million components with interconnects in between, this project will concentrate on analysing specific sections of the chip. These sections are known as ring and mesh. They consist of a ring, which is a relatively large power track, and located within it is a mesh, which is a grid of thin wires, the edges of which are connected to the ring. The mesh carries power from the ring to the components situated beneath. Ring and mesh circuits are suitable for this project since they can be easily modelled. The wires are modelled as resistors, the connections between the mesh and the power ring can be modelled as independent voltage sources and the drain of current from the components below the mesh can be modelled as independent current sources Inputs To perform circuit analysis, the system needs to know the architecture of the circuit - that is, how the nodes of the circuit are connected together by the branches (wires), and also where any independent voltage sources and current sources are connected. In a stand-alone library with no graphical user interface, this information can be fed into the system manually. The user could simply enumerate the nodes, branches, voltage sources and current sources and type the details into a command line interface. This is similar to how OrCAD SPICE works, albeit without the graphical user interface. In SPICE, users drop onto a schematic the components to create the circuit they desire before running any analysis. Entering the circuit information via a command line interface might be useful for implementing small circuits for test purposes, but it would be very tedious. If the circuit analysis system is to be integrated into Lyric then it is likely that the circuit information will have to be inputted in the same way that the information is entered into Lyric which is via a netlist file. This is a special file format that contains all the information for the circuitry in a chip design which is read and stored appropriately. 19

28 3.1.3 Outputs As stated in Section 2.1 on page 5, the system created by this project is intended to help chip designers reduce the possibility of electromigration and IR drop occurring. Since electromigration is caused by an excess in the flow of current through a wire, the system needs to be able to calculate and output the value of the current flowing through every branch between the nodes of the circuit. In order to make it easy for a chip designer using the system to see where there is an overflow of current, it would be useful for the system to highlight where there is a current that exceeds acceptable limits. It would be simple then for the user to see the places where the wire should be fattened to reduce the stress. A possible addition to this functionality which would be a bonus to the user would be for the system to highlight areas where the current flow is significantly under the maximum capacity of a wire. With this information, the user could make the wire thinner and thus possibly make the overall design smaller, resulting in a smaller physical chip size. To recap on Section 2.1, IR drop is the phenomenon whereby voltage drops excessively across a circuit, possibly resulting in not enough power reaching certain areas of the chip. Therefore, the system needs to output the voltage at every node across the circuit. To make it easier for the user to see where problems may occur, it would be of benefit if the system could highlight nodes where the voltage is below some predetermined threshold level. An enhancement to this functionality would be for the system to indicate where a node is receiving a large excess in voltage. This might allow the chip designer to reduce the power input into the chip Speed The initial attempt at circuit analysis, when the system first calculates the values for voltage and current across the specified circuit, does not have to be particularly fast. When Lyric s router tool runs and joins up all the components in a chip design with wire tracks, it can take an hour or more, depending on the size of the design. So, relative to this, conducting circuit analysis will be comparatively fast anyway so there is no real need to strive for speed for the first iteration. The focus at this point is simply accuracy and reliability. The results of the first circuit analysis will often show areas of the circuit where currents and voltage fall outside the specified parameters. In a mesh with ten 20

29 thousand nodes, and thus more than ten thousand branches, there maybe hundreds of such errors that need correcting. Fixing the errors highlighted by the circuit analysis is done by either fattening the wires or thinning them. For instance, if there is too much current flowing through a wire then the wire needs fattening to safely accommodate the current flowing through it. However, a single fattening of the wire will not normally fix the problem. By fattening the wire, the resistance of the wire is reduced causing more current to flow through it, which could mean the fattening has little effect. The solution then is to fatten or thin the wire iteratively and re-analyse to see the effects of the action and find the optimum wire width. The wire needs to be fattened enough to safely cope with the current flowing through it but not so much that the amount of current increases enough to negate the fattening. The thinning process is similar to this. The chip designer may chose to do the fattening/thinning of the wires in the design by hand. More likely though, since there may be hundreds of wires in a design that require the iterative fattening/thinning process, there will be an automated fixing tool that does the job. Since there will be a lot of iterations of making changes to the design and then re-analysing of the circuit, it is imperative at this point that the circuit analysis is done very quickly. The automated fixing tool has to wait on the results of the analysis before making its next change and so it cannot have to wait long or the whole process would take an impractical amount of time. The focus therefore during this area of the systems usage is speed, but still with as high accuracy as possible, although some slight trade-off may be acceptable Accuracy Since the circuit analysis is being performed on integrated circuits, the width of the wires is tiny and so the values of the currents and voltages are also very small. The current flowing through any wire in the circuit may range from one amp down to a few nano amps while it also must be possible to detect a drop in voltage of one ten-thousandth of a volt between adjacent nodes. The system will have to be able to manipulate these small numbers accurately and ensure the possibility of round-off errors is avoided 21

30 3.1.6 Reliability The system to be produced by this project is just simply for academic purposes; Pulsic wish to integrate it into their Lyric software. This means that the system will have to live up to the reliability expectations of the business world. Pulsic s customers will expect a high level of reliability since they will have spend a lot of money on the Lyric tool. This implies that the testing performed in this project should be as rigorous as possible to catch any bugs and errors in the system Platform Versatility Pulsic provides versions of its software to run on a wide variety of platforms to suit all customer needs. The range of platforms includes Linux, Solaris, HP-UX and Windows. Further more, Pulsic support different varieties of each of those platforms. For Linux for instance, Lyric is available to work with SuSE 9.0, SuSE 9.1, SuSE 10, RedHat 7.2 and RedHat 8.2. If this system is to be integrated into Lyric, then it too must be able to run on all of these different platforms. This means taking into account things such as variations in the compiler available etc. Thorough testing should be employed to ensure the system runs correctly on all platforms Security It is important that the software Pulsic release is protected so that other companies cannot dissect the code and learn all of the company s design secrets. Therefore, if this system is to be integrated into the Lyric, it is important that it does not violate any security protocols put in place by Pulsic so that the software remains secure User Interface If the system is to be integrated into the Lyric software, it will have to use Lyric s graphical user interface rather than having one of its own. This will probably involve adding a menu and some toolbar buttons to the GUI for controlling the circuit analysis tool s functionality. The circuitry for circuit analysis to be performed on will probably be chosen by selecting sections of a chip design displayed 22

31 in the Lyric GUI. The output of the system will also have to be displayed in the Lyric graphical user interface, in some appropriate fashion. The changes made to the Lyric GUI will have to be made in such a way to keep it consistent, so as not to confuse users. The additions for the new system should be clear and compact to ensure ease of use Heat Map As the number of components on a chip continues to increase along with the density in which they are packed, overheating is becoming a serious factor affecting the performance of integrated circuits. As part of its functionality, the system could calculate the heat generated by a chip based on the results of circuit analysis. This would require calculations involving thermodynamics and heat conductivity of the various materials from which an integrated circuit is constructed. The results would then be displayed in a heat map superimposed over the image of the circuit. However, the complexity of the calculations required for this task to be performed is huge and therefore this requirement is considered to be out of the scope of this project. 3.2 Requirements Specification Functional Requirements Perform circuit analysis on DC ring and mesh circuits containing passive components Take as input the circuit architecture, including the nodes, branches, voltage sources and current sources Perform an accurate first iteration of circuit analysis Execute fast further iterations of circuit analysis Output the voltages at each of the nodes Output the currents through each of the branches Display the results graphically on the Lyric GUI 23

32 3.2.2 Non-functional Requirements Output accurate results Have good reliability Uphold Pulsic s security protocols Be easy to use Be able to run on all the platforms that Pulsic support 3.3 Constraints Hardware Constraints The author has been given use of an AMD Athlon PC with 512Mb of RAM by Pulsic. The author also has their own Pentium 4 3.1GHz notebook with 512Mb of RAM and the author also has use of the PCs available on campus at the University of Bath Software Constraints The author has use of the Windows XP operating system on their notebook, the SuSE 9.0 Linux operating system on their Pulsic machine and the UNIX operating system on the University of Bath computers. Servers at both Pulsic and the university also provide compilers for most mainstream languages that the author may wish to use Time Constraints The final deadline for the project is Monday 8th May. 3.4 Summary This ends the Requirements Analysis and Specification chapter. The next chapter investigates the various tools available for implementing the system and chooses the best ones for the task. 24

33 Chapter 4 Tools and Technologies 4.1 Programming Languages There are various languages available that could be used to implement the current analysis system. Here is a discussion of some of those languages, leading to a decision on which should be used C Advantages C has a simple, small core language with extra functionality being provided by a large range of libraries which include maths and file handling functions [36]. This allows programmers new to the language to quickly become proficient in the basics, while the more complicated routines are readily available when needed. The language the supports procedural programming paradigm [36] which lends itself to modular design. While C does not force modular design upon the programmer, good programmers can use the language to create a cohesive modular structure. The modules are usually separate files which can be compiled separately. This would be useful for this system since it has been designed as a set of modules with specific functionality. C is extremely flexible and allows the programmer to have low level control over the computer. As such, the programmer has full control of memory allocation and pointers to create program solutions which are tailored to the problem. The low level nature of the language also results in the language being fast in its 25

34 execution. This is a feature which would be welcomed for this system as there are parts of it which need to run as fast as possible. Through the use of special keywords, C allows the programmer to create new data types to suit the needs of the program solution. This is particularly advantageous for this project as some unique data structures will be needed to store the data for the objects in the system such as nodes, branches etc. The Lyric Physical Design Framework is programmed largely in C. If this system is also programmed in C, it would be easy to integrate it into Lyric which is an obvious advantage. Furthermore, the author has extensive experience of using C which would mean implementing the system in this language would be easier. Disadvantages One disadvantage of C is that memory allocation has to be done explicitly by the programmer. This can lead to errors when memory is not allocated properly. Allocated memory is also not initialised automatically [36] and so this too has to be done by the programmer to avoid getting bizarre values when trying to access data structures. If C is used, these disadvantages mean that the author will have to be particularly vigilant when allocating the memory for the data structures which will doubtlessly be needed. C is not a strongly typed language. This means that the compiler will often not complain when a variable is declared as one type and then used to store a value of a different type. Therefore, if using this language, the author will have to be careful when writing the program to ensure variables are used as declared to avoid getting any unusual behaviour. C has some idiosyncracies in its syntax which can catch the programmer out and cause unexpected behaviour in the program. A well known example of this is accidentally using if (x = 0) instead of if (x == 0). The former will set x to be zero rather than testing if x is equal to zero. This will usually cause the program to run differently than expected, but it will not be picked up by the compiler. Other such syntax issues include the dangling else and loops that only iterate over the first line if a block if the curly braces are forgotten. These issues mean the programmer has to be very careful when writing a program to ensure the code will perform exactly as they are expecting. The disadvantages above can mean debugging C code can be problematic which means the author will need good debugging skills. C also has no automatic garbage collection which means the programmer has to explicitly free all allocated memory. 26

35 4.1.2 C++ Advantages Since C++ is derived from C, it inherits many of the advantages of C such as support for procedural programming, the ability to create bespoke data structures and its general flexibility. C++ supports object-oriented programming [35]. This allows programs to be organised as a collection of classes and objects, which, enthusiasts claim, makes programming large systems easier. If the circuit analysis system had been designed with object oriented programming in mind, this would be an advantageous feature. However, the author is more comfortable with the procedural paradigm which is why the system has been designed in a modular fashion instead. Despite the extra functionality included into the language to support object oriented programming, C++ remains a fast language which is an advantage for the iterative circuit analysis tool which relies on speed. The majority of Pulsic s source code is written in C, while a good portion is written in C++. This means that if the system was written in C++, it would be easily integrated into the Pulsic software. The author has little experience with C++, but the fact that it is a derivation of C and that the author has a lot of experience using C, learning C++ should not present too much of a challenge. Disadvantages Since C++ is derived from C, it inherits many of the disadvantages of that language too, such as the idiosyncracies of the syntax and the lack of garbage collection. While the core of the C++ language is small like C, there are many libraries that deal with the additions for objected oriented programming which can make it seem like a large and complicated language [35]. If programmers try to use all of the functionality at their disposal, then it can be a difficult language to master. The additional functionality can also make C++ a slower language than C. Furthermore, while the standard library has been developed by many users over the years to become useful and reliable, many other libraries have not. This can cause problems when trying to develop programs that utilise these libraries. The C++ language contains constructors and destructors that are supposed to 27

36 help with memory allocation. In reality however, they can often hide a lack of deallocation of memory which then leads to memory leakage. The error messages produced by a C++ compiler are notorious for being extremely complicated and difficult to understand. This will mean choosing C++ to implement this system will require a lot of effort when it comes to debugging the program Java Advantages Java s syntax is heavily derived from that of C/C++ [40] and so it should look familiar and be easy to learn for those programmers who have experience with either of those languages. The author has had some experience with Java, which is an advantage should Java be chosen as the language to be used to implement the circuit analysis system. Java hides the details of the machine from the programmer. For instance, the programmer does not have to worry about pointers or explicit memory allocation. Java has automatic garbage collection [40], so implementing the system in this language would mean the author would not have to worry about explicitly freeing the memory used by any data structures. These features should make implementing the system easier. Since it is compiled to bytecode which can run on any machine with a Java Virtual Machine (JVM), Java is an extremely portable language [6]. This is an advantage for this project since the circuit analysis system has to be able to run on a variety of different machines and operating systems. Simply by installing a JVM on each of the platforms, the program would be able to run without any changes to it. Disadvantages Java is a pure object oriented language [40]. This means the design of the system would have to be changed to be organised in terms of classes and objects rather than the modular design it currently has, if Java is to be used. The author is also more comfortable with the procedural programming style rather than the object oriented approach. The inclusion of features such as an automatic garbage collector and the fact it is an interpreted language means that Java is generally recognised as being a fairly 28

37 slow language [6]. This is a disadvantage because, as discussed previously, speed is important in certain parts of the system. As Java hides away the complexities of the underlying machine away from the programmer, the language may be considered to be less flexible than C/C++. There may be occasions when implementing the system where having tight control over the machine may be beneficial, but this is something which Java will not be able to allow. As a company Pulsic does most of its programming in C or C++. This means that it will be more difficult to integrate a system programmed in Java into Pulsic s software than if the system were programmed in either C or C Python Python is an object oriented language that is good for graphical user interface programming. This is because of its Tkinter package which is a thin object oriented layer on top of Tcl/Tk - a graphical user interface toolkit [41]. As such, Python is the language that Pulsic use to implement all their GUIs. Pulsic also have a customised set of GUI widgets known as pwidgets. pwidgets are created simply by putting a wrapper around the normal Tcl/Tk widget set to give the widgets a look and feel that make them unique to Pulsic. Since the circuit analysis system will be integrated into Lyric and will use the same GUI, this project will use Python for any additions that need to be made to the interface. This is the obvious choice so that there wont be any need to integrate a foreign programming language into the GUI software. Furthermore, its imperative that any additions to the GUI retain the same look and feel as the rest of it. Therefore it is necessary that the added widgets are created from the pwidgets widget set, which means using Python Conclusion Having considered the pros and cons of the major languages available for implementing the circuit analysis system, the decision has been made to use C. This is because the author has extensive knowledge of the language which should reduce implementation time and also the majority of the Lyric source code is written in C which should mean integrating the two systems should be an easier task. Furthermore, C is a fast language which will help enable the system to meet its performance requirements, and the language supports the procedural program- 29

38 ming paradigm which is the author s preferred programming style. As for implementing the graphical user interface of the system, the only option really is to use Python since it will enable an easy integration into Lyric and also maintain Lyric s look and feel. 4.2 Integrated Development Environments (IDEs) An integrated development environment (IDE) is a piece of software that assists programmers to develop programs and usually consists of a source code editor, a compiler, build automation tools and a debugger [39]. They are generally supposed to make developing software easier. There are several IDEs available for the C programming language such as Eclipse, C-Free and the CodeForge IDE. However, the author has never used an IDE and feels comfortable programming without the aid of one. Therefore an IDE will not be used when implementing the circuit analysis system. 4.3 Compilers A compiler is a piece of software that converts the source code of a program written in a programming language into machine code that can be executed by a computer. There are many compilers available for the C programming language, but the author has always used the GNU Compiler Collection (GCC) compiler and feels most comfortable with it. GCC is produced by the GNU Project and is free software, distributed by the Free Software Foundation (FSF). Since it is open source software, GCC has been developed using the open source model in which users are treated as co-developers. Users are given access to the source code and are encouraged to develop new features, fix bugs, update documentation and so on. Advocates of the open source development methodology claim that in many ways it is better than the closed source method (commercial development). The open source enthusiast Eric S. Raymond goes so far as to suggest that the open source methodology is able to produce higher quality software than any other methodology or technique [29]. These claims can be partly backed up by studies that have shown that the time taken from bug discovery to bug fix is shorter in open source development. The result for GCC is a highly developed and tested piece of software that should be reliable and efficient. For these reasons and since the GCC compiler is available both on the University of Bath machines and on the computers at Pulsic, GCC 30

39 will be the compiler of choice for this project. 4.4 Debuggers Debuggers are software tools which help programmers identify the errors in their source code. There are several debuggers available for C, such as the DDD and GDB debuggers available on the Pulsic computers. Much of the debugging required can be performed manually with the careful insertion of print statements. However, for the difficult to find problems such as errors involved with pointers and memory allocation, the GDB debugger will be utilised. 4.5 Revision Control Systems Revision control is concerned with keeping track of the development and multiple revisions of the same units of information. Revision control systems keep a repository of files which developers check out in order to work on them before checking them back in and merging the changes made into the previous version. A history of the revisions is kept to ensure that the files can be reverted back to a previous version if necessary. These systems allow a team of people to work on the same files without having to worry about the conflicts between their work or fear of causing damage. A popular revision control system is the Concurrent Versions System (CVS) which is available on the Pulsic computers. However, since there will be just one developer working on the circuit analysis system, there is no need for a central repository of files for concurrent development and so CVS will not be utilised in the development of the system or its documentation. 4.6 Backing Up Files Unforeseen technical problems can occur within a computer, such as the hard drive failing or becoming corrupt, that can lead to the loss of files. For this reason important files should not be kept in just one location, they should be backed up. This means copying the files to some other storage device or devices so that if any files are somehow lost, there is always a reserve copy. 31

40 As a precaution in this project, the system s files will be regularly backed up to the university s servers, and also to a USB memory stick to allow for file recovery on the move. 4.7 Testing Technologies Since Modified Nodal Analysis revolves around solving equations involving matrices, Maple has been chosen as a platform for testing the circuit analysis system as it is being developed. Maple is a computer algebra system and as such is excellent at manipulating matrices quickly. It is intended that, during development the system will be tested by giving it some simple inputs and then printing out the matrices that are constructed and the solutions that are calculated. Meanwhile, for the same inputs the matrices are constructed by hand and then the solutions found by using Maple. Comparing the results will show whether the system is working correctly or if some changes are required. 4.8 Summary In summary, the language to be used for implementing the core system is C, while Python will be used for some of the GUI work. The compiler will be GCC, the debugger will be GDB and Maple will be used for the testing of prototypes. The next chapter will outline the high level design of the system. 32

41 Chapter 5 High Level Design This chapter outlines the high level design decisions made in order to create a system that satisfies the requirements laid out in the Requirements Analysis and Specification chapter. 5.1 System Structure The system has been designed in a modular fashion so that the system consists of a collection of units with a distinct functional purpose. It has been designed this way as the problem lends itself more to a procedural approach rather than the object oriented approach which would have led to the system being designed as a collection of classes and objects. Figure 5.1 displays the overall high level design of the system. It shows that the system is broken down into five modules: the input module, the initial circuit analysis module, the iterative circuit analysis module, the current calculation module and the output module. Following is a brief description of each of the modules: Input - this module is responsible for receiving the input of the system (circuit layout information) and storing it. This will involve entering the data into the system s data structures in an organised and efficient manner. Initial Circuit Analysis - this module will carry out the first iteration of circuit analysis on the circuit information held in the system s data structures. The focus of the circuit analysis at this point is to determine accurate values for the voltage at each of the node in the circuit design. The nodal voltages will then be saved back to the data structures ready for output. 33

42 Figure 5.1: The high level design of the circuit analysis system Iterative Circuit Analysis - this module will take the results of the initial analysis and perform further iterations of circuit analysis. The here is to recalculate the nodal voltages very quickly in response to minor changes made to the circuit so that errors in the design can be fixed in an efficient manner. Current Calculator - since the circuit analysis modules only calculate the nodal voltages, this module calculates the currents through the circuit branches. This will be done by applying Ohm s law to a pair of nodes and the branch between them. The results will be saved back to the data structures. Output - this module is concerned with returning the results of each iteration of the circuit analysis to the user. The most important method of output will be via a graphical user interface, although the results of the circuit analysis will also be printed to a file. This is so users will have a record of the results, but also because it will be useful for system testing. 5.2 Initial Circuit Analysis Algorithm As stated in Section on page 20, the requirement of the initial circuit analysis phase is accuracy and reliability with the speed of the algorithm of less importance. With this in mind, the decision of which method to use for this phase of 34

43 circuit analysis is to be made by examining the methods used by existing circuit analysis systems. The rationale for this line of thought is that existing circuit analysis systems which are or have been used in the commercial world will use methods which are accurate and reliable, since it is demanded by the users. It was shown in Section 2.4 on page 10 that two of the most well known circuit analysis systems are ECAP II and SPICE. SPICE performs circuit analysis by using the well known nodal analysis method, while ECAP II uses a more obscure method known as the mixed method. These two methods could be implemented in this project so a decision has to be made on which to use. Nodal analysis is a straight-forward concept and there is extensive literature on the subject explaining the process and its implementation. The mixed method however is a much more difficult algorithm and the availability of pertinent literature is much less. The success of the two circuit analysis systems may also be an indication of the relative merits of their two analysis methods. SPICE is the most popular circuit analysis tool available today, while ECAP II is rarely used if at all. This may indicate that nodal analysis is the better basis for a circuit analysis tool. For these reasons, this project s circuit analysis system will follow the SPICE method. However this still leaves the question of which version of the nodal analysis method to use. Early versions of SPICE were based on standard nodal analysis while later versions utilised the Modified Nodal Analysis (MNA) approach. The problem with standard nodal analysis is that it can become complicated when the effects of voltage sources have to be taken into account; either a separate equation has to be written for each source, which increases the number of equations to be solved, or the supernode method must be used which makes the implementation more difficult [5]. Since the ring and mesh circuits that the system has to analyse has many virtual voltage sources that have to be considered, using the standard nodal analysis could be problematic. MNA has no such problems trying to analyse the effects of voltage sources. Furthermore, it is easier to implement algorithmically on a computer [5], which is a significant advantage. For these reasons, the circuit analysis system will implement MNA as the basis for the initial circuit analysis module. 35

44 5.3 Matrix Inversion Algorithms When Modified Nodal Analysis is applied to a circuit with only passive elements (resistors) and independent current and voltage sources, as will be the case in ring and mesh circuitry, the result is a matrix equation of the form shown in Equation 5.1. Ax = z (5.1) For a circuit with n nodes and m independent voltage sources: A is an (n + m) * (n + m) matrix and consists only of known quantities, x is an (n + m) * 1 matrix (or vector) that holds the unknown quantities and z is an (n + m) * 1 matrix that holds only known quantities. Equation 5.1 is solved through matrix manipulation, forming Equation 5.2 from which the solutions can be easily read-off. Creating Equation 5.2 requires finding the inverse of matrix A. There are several methods for finding the inverse of a matrix and so following will be a discussion of some of those techniques, culminating in a decision of which will be used in this project. x = A 1 z (5.2) Gauss Jordan Elimination is a well known method for manipulating matrices. It is the most basic technique available and is straightforward, understandable and solid as a rock [26]. Its ease of implementation, however, is offset by a number of drawbacks, one of which is that it is not a very fast technique. This, along with the other drawbacks which will not be detailed here but can be found in [26], led to it being stated that: Gauss-Jordan elimination should usually not be your method of first choice, either for solving linear equations or for matrix inversion. [26] LU decomposition is another technique for manipulating matrices and is the method of choice for SPICE. The algorithm is fairly easy to implement and has an operations count which is roughly a factor of three better than Gauss Jordan Elimination, while having no obvious flaws. These features have resulted in LU decomposition being described as the preferred way to solve the linear set of equations of the form shown in Equation 5.1 [26]. As mentioned in Section on page 15, Cholesky decomposition is a technique that is relatively easy to implement while being a factor of two faster than LU 36

45 decomposition. However, since the algorithm only works on square matrices that are both symmetric and positive definite and the matrices produced by MNA can not be guaranteed to be of this form, Cholesky decomposition has to be ruled out as a candidate for use in the circuit analysis system. The final possibility to be considered here is Kron s method of tearing. While this method is faster than those examined here, it is disadvantaged by being by far the most difficult to implement and the fact that it is prone to round off errors. After considering the options, it has been concluded that LU decomposition will be implemented to solve the matrix equations generated by the Modified Nodal Analysis. While it is not the fastest choice, as stated in Section on page 20, speed is not the most important requirement of the first iteration of circuit analysis. LU decomposition is however fairly fast, is easy to implement and is used by SPICE which indicates that it is a reliable mechanism. 5.4 Iterative Circuit Analysis Algorithm As stated in Section 3.1.4, the iterative circuit analysis most important requirement is its speed. It must produce results fast enough for an automated tool to perform corrections to the circuit design efficiently. Just using Modified Nodal Analysis with LU decomposition will not be sufficient since calculating the inverse of a large matrix will take too long. Therefore a different algorithm is required for this section of the system. The key for any algorithm to be suitable for this task is the ability to localise computation so that when a small change is made to the resistance of a branch in a circuit, the whole circuit does not have to be recalculated. The literature review in Section 2 provides two candidate algorithms for this. The first of these is Kron s method of tearing, which although is based on manipulating matrices, manages to do so in a manner which localises computation so that the whole matrix does not need recomputing. However, as mentioned in Sections and 5.3, this method is very difficult to implement and is also prone to round-off errors. Therefore, Kron s method of tearing can be ruled out. The second option is the random walk algorithm. This algorithm is based on performing circuit analysis using the well known mathematical random walk principle. As such, the algorithm manages to compute a nodal voltage by performing a series of random walks that only encompasses part of the circuit, thus localising computation. In theory, this is an ideal solution for the iterative circuit analysis module. 37

46 Figure 5.2: Convergence toward actual voltage over a number of walks However, this algorithm is relatively new, with the paper introducing it only being published three years ago. As a result, there is very little supporting literature detailing the finer points of the algorithm and its implementation. Therefore, the random walk algorithm would be very difficult to implement and so will not be used in the circuit analysis system. Since the two main candidates for the iterative analysis algorithm have been ruled out, the alternative is to design and implement a whole new algorithm. Although the random walk algorithm has been ruled out, some lessons can be learnt from it that can help the design of the new algorithm. In the random walk algorithm, a number of random walks are performed across the circuit to determine the value of a nodal voltage. As the number of walks performed increases, the result found for the voltage oscillates and converges on the true value as seen in Figure 5.2. The algorithm stops once the oscillation of the voltage change drops below a certain specified value, thus limiting the amount of computation. The new algorithm which is to be developed will use this basic convergence technique and will follow the following basic steps in response to a change in resistance of a branch: Calculate the the new voltages at the nodes at either end of the modified 38

47 branch using Ohm s law. This is the first iteration of the algorithm. Store the new voltages of these two nodes Successive iterations will calculate and store the new voltages of nodes connected to the nodes analysed in the previous iteration. In this way, the circuit analysis will spread outwards from the initial branch. When the new voltage for a node is calculated and it is different to the original voltage by less than 0.01 percent, the node is flagged and the circuit analysis will not spread outwards past this node. In this way, the analysis area will reach a maximum radius from the initial branch, thus localising computation while also ensuring the calculations have an acceptable level of accuracy. When the maximum radius of nodes is reached, repeated iterations will contract the area of circuit analysis back down to zero as the nodal voltages converge towards their true new values. The process stops when all new nodal voltages differ from the values in the previous iteration by less than 0.01 percent. Through a series of iterations, this algorithm will converge on the new values of nodal voltages caused by the change of resistance in one branch. Figure 5.3 shows a section of a mesh circuit and gives a basic illustration of the algorithm. The yellow branch in the centre has been fattened or thinned which changes its resistance. The first iteration of the algorithm calculates the new nodal voltages for the red nodes, the second iteration calculates the new voltages for the blue nodes, and then the third iteration does likewise for the green nodes. At this point, the change in the voltage is less than one percent so the changes are sufficiently small to stop spreading the circuit analysis further. This process is then repeated until all the nodal voltages have converged to within a one percent oscillation in value, upon which the voltages are accurate enough to stop the analysis. 5.5 Units To Be Used The values that the system will have to deal with can range from one amp to a few nano amps in current, with similarly sized values for voltages and resistances. These wide ranging values bring up the question of what units to use for these quantities. For instance, since the current is always likely to be less than an amp, all the measurements for current could use milliamps or microamps as the base unit. 39

48 Figure 5.3: Possible iterations of circuit analysis using the iterative algorithm While this would avoid having to manipulate very small numbers, it could lead to confusion when having to use equations such as Ohm s law where calculations have to be made with voltages, currents and resistances. If they were in different base units such as milliamps, microvolts and ohms, incorrect answers may accidentally be produced if it were forgotten that the numbers were in different scales. For this reason, the units that will be used in this system will be the standard SI units of amps, volts and ohms. 5.6 Data Structures The circuit analysis system will have to be able represent matrices and also store data on the various components contained within a circuit design. Here follows a brief outline of the required data structures: matrices - the data structure to represent matrices will have to be some sort of two dimensional array of floating point numbers. The array will have to be dynamically allocated however, as it will not be possible to know the size of the circuit until after the program has started to run. nodes - the information that will need to be stored about nodes will include a unique identification number, the branches, voltage sources and current sources connected to it and the node s voltage. resistors - these are actually branches or wires in a circuit, but they are modelled as resistors. The pertinent data that needs storing about branches includes an id number, the two nodes between which the branch is connected and the resistance of the branch. 40

49 current sources - an identification number, the current it draws from the circuit and the node to which it is connected needs to be stored about each current source in the data structures. voltage sources - the information that needs to be stored about voltage sources includes and id number, the node to which it is connected and the value of the voltage it supplies to the circuit. 5.7 GUI Since the circuit analysis system is to be integrated into Lyric, it will use Lyric s user interface. A menu will be added to the interfaces toolbar from which the circuit analysis can be initiated. The section of circuitry on which to perform circuit analysis will be chosen by selecting an area of the circuit design with the mouse. It is often said that it is a mistake when designing a user interface to associate meanings with particular colours since ten percent of men are colour blind [30]. However, the decision has been made that the best way to display the results of the analysis so that they are clear is to use colour. The rationale behind this decision is that it should be far easier to see if a wire is carrying too much current by simply looking at its colour rather than interpreting a symbol or reading a number which is annotated on the wire. To display the colour, a mask will be laid over the display of the circuit that will render each node and branch of the circuit a certain colour depending on their associated values. The most obvious colours to use are the colours of traffic lights. For instance green is to be used for wires whose current is well within the limits, amber for wires whose currents are approaching the limit and red for wires whose current exceeds the specified limit. This way the colours used in the GUI are associated with something that will be known by the vast majority of users. To cater for the users who are colourblind, each of the wires and nodes will be annotated with their associated currents and voltages respectively, so that the users do not have to rely on colour alone to understand the results. This will also be useful for users who are not colour blind but want to know the exact results of the analysis. 41

50 5.8 Summary This concludes the high level design chapter. The decision has been made to use Modified Nodal Analysis as the algorithm to perform the initial circuit analysis, LU decomposition to solve the MNA equations and a new algorithm is to be developed to implement the iterative circuit analysis. The following chapter delves into the low level design of the system and its implementation. 42

51 Chapter 6 Low Level Design and Implementation This chapter details the decisions made when trying to create a detailed design to fulfill the requirements and how the design was implemented. 6.1 Code Files The circuit analysis system is implemented as a collection of files containing C code that reflect the modular design of the system as stated in Section 5.1 on page 33. Following is a brief description of the functionality contained within the files: input.c - provides an implementation of the input module. This file contains functions for setting up the data structures required for storing the circuit layout information. The are also methods for getting said circuit information from Lyric, and from a human user when the system is used as a stand alone system rather than integrated into Lyric. mna.c - provides an implementation of the initial circuit analysis module. This file contains methods for creating the matrices required for Modified Nodal Analysis (MNA) and executing the MNA algorithm to find the nodal voltages of a circuit. iterate.c - implementing the iterative circuit analysis module, this file contains the procedures that execute the iterative circuit analysis algorithm. current.c - implements the current calculation module, providing functions for calculating the current that flows through a circuit s branches. 43

52 output.c - an implementation of the output module. Provides functions for printing the results of circuit analysis to the results.txt output file and for displaying the results on screen when the system is used independently from Lyric. utilities.c - this file provides some methods for accessing data structures and freeing memory allocated by the system. mna interface.c - this file defines an API to allow the circuit analysis system to interface with Lyric. nodalanalysis.c - this function contains a main method which allows the circuit analysis system to be utilised as a stand-alone system, mainly for testing purposes. 6.2 Types As stated in Section 5.5 on page 39, this system will be using the SI units of volts, amps and ohms when measuring voltages, currents and resistances respectively. While this will make clear what units an answer should be in when performing calculations using equations such as Ohm s law, it will mean that very small values will have to be manipulated; the current through a wire in an integrated circuit can be as little as one nano amp ( amps). In this system there will be a lot of calculations using these small values, especially in the solving of equations involving matrices as in MNA. Therefore to ensure that the requirement that the system should produce accurate results is met, a suitable type has to be used for storing these numbers. The type should provide enough storage space that will avoid the need to truncate values as this can lead to rounding errors through repeated use of such values in computations. To reduce the likelihood of truncation as far as possible, the largest data type available could be used. In C, this is the long double, however not all platforms support this type. On those platforms that don t support long double, its size is the same as that of the standard double type. This is an issue for the circuit analysis system since it is required to run on all the platforms supported by Pulsic. The results returned by the system should be consistent whatever platform it is running on and so the long double type cannot be used for storing the electrical units. Therefore the system will use the double type as it generally provides sixty-four bits of storage space and is supported on all platforms. 44

53 6.3 Data Structures For the system to be able to store pertinent information in a logical format that allows efficient access to the data, some data structures had to be designed. Following is a discussion of the key decisions made in their design Matrices Since the MNA algorithm is based on matrix manipulation, a data structure had to be designed to represent a matrix. The basic structure of a matrix resembles a two dimensional array, so it was obvious to conclude that the data structure should be a two dimensional array. Each element of a matrix will be storing values relating to resistances, currents and voltages which, as stated in Section 6.2, are stored as type double. This means that the matrix data structure had to be a two dimensional array of type double. However, since the size of the circuit design is not known until after the system has started running, the size of the array required is also not known, which precludes the use of the C language s in-built array structures. The array has to be dynamically allocated using malloc. The most obvious way to create a dynamic two dimensional array of doubles is to allocate an array of pointers to doubles, and then for each pointer in that array, allocate an array of doubles. This is shown in the following section of code: 1 A = malloc ( rows s i z e o f ( double ) ) ; 2 for ( i = 0 ; i <= s i z e ; i ++) 3 { 4 A[ i ] = malloc ( columns s i z e o f ( double ) ) ; 5 } If the two dimensional array is implemented in this way, an element of the array can be accessed in the normal way. For example accessing the element at the fifth row and ninth column would be: 1 A [ 5 ] [ 9 ] However, there is another way of creating a two dimensional array in which accessing the elements of the array is faster than the previous method. The implementation shown above relies on the language/compiler keeping track of the pointers so that it is possible to index to the right location by inserting the row and column in the square brackets. It is possible to control the indexing manually which is faster than having the language/compiler do it. 45

54 This implementation involves allocating a one dimensional piece of memory that is rows * columns in length as seen below: 1 A = ( double ) malloc ( rows columns s i z e o f ( double ) ) ; Conceptually, this one dimensional piece of memory can be thought of as rows of a two dimensional array arranged end-to-end rather than on top of one another. To index to the right element, a simple calculation like the following is required: 1 A[ ( row c o l s ) + column ] Simply multiply the desired row to index to by the number of columns per row will index to the right row of the array. Then adding the column required will index to the exact element. In this way a two dimensional array can be modelled as a one dimensional one and is actually how the language/compiler models it. This second method is faster than allocating an array of pointers to arrays and letting the indexing being done automatically. This is because an array of pointers to arrays is likely to have 2 page misses, one looking for the row and then one for the column. Because of the construction of the array these are unlikely to be near to each other in memory which means cache prefetch will not help. This means two main memory fetches will occur and that can easily slow a 3GHz processor down to the speed of the memory bus or slower (as the memory bus speed is for bursts not for random access). If you have a one dimensional array, although you need to do a multiply to find the right index this will be a single cycle in the ALU of the processor. You then only get one memory access, and because this will be arranged in a pattern that CPU s are optimised for, you will find in most cases that the data has been prefetched by the CPU, hence the processor runs nearer its full speed. Having chosen the second option for implementing the matrices some methods were created for accessing the data. These implement the indexing mechanism described above and also do some bounds checking to ensure that the element required is actually within the confines of the array. The following is an example routine that enters a value into the matrix: 1 / Function to put a v a l u e in a p a r t i c u l a r element in a matrix / 2 void putval ( matrix p matrix, int row, int col, double value, int 3 n o r m a l i s e ) { 4 / Check i f t h e normalise f l a g has been s e t i f so normalise 5 t h e row and c o l f i e l d s. Needed s i n c e matrices are numbered 6 from 1.. n, arrays from 0.. n 7 / 8 i f ( n o r m a l i s e ) 9 { 10 row = row 1 ; 11 c o l = c o l 1 ; 12 } / Bounds c h e c k i n g / 15 i f ( 0 <= c o l && c o l < matrix >c o l s && 0 <= row && row < matrix >rows ) 46

55 16 { 17 matrix >mat [ ( row matrix >c o l s ) + c o l ] = value ; 18 } 19 else 20 { 21 p r i n t f ( Fatal e r r o r matrix index out o f bounds \n ) ; 22 e x i t ( 1 ) ; 23 } 24 } Circuit Elements A ring and mesh circuit that has to be analysed will contain circuit elements including nodes, branches (modelled as resistors), current sources and voltage sources. Each one of these components requires a data structure that will be able to store the important information that is related to them. First of all, it is important to be able to distinguish between the different nodes, current sources and so on, which is why each has been given a unique identification number. This is simply an integer which starts at one, and is incremented as each circuit element is read in by the system. To be able to reflect in the data structures how the circuit is connected, the resistors connected to a node are stored. Since there can only be a maximum of four resistors connected to any one node, the resistor identification numbers are stored in a four element array. If there are fewer than four resistors connected to a node, zero is stored in the unused array elements to signify the lack of a resistor in that position. A node may also be connected to one voltage source and one current source, so there are integer slots in the node data structure to store the identification numbers of these, or zero if one is not connected. Since circuit analysis calculates the voltage at each node, there also has to be a slot for storing the voltage that is calculated, which as explained earlier in Section 6.2 on page 44 are stored as type double. For a resistor, it is necessary to know the nodes that are connected to in order to describe the circuit properly. So in the resistor data structure there are integer slots that store the identification numbers of the two nodes at either end of the resistor. There are also slots of type double for storing the values of the resistance of the resistor and the current flowing through it. The current source data structure and voltage source data structure are very similar. They store the identification number of the node the element is connected to and the current/voltage that they draw or supply to the circuit respectively. 47

56 Following is a section of code that illustrates the resistor data structure: 1 struct r e s i s t o r s 2 { 3 int i d ; 4 double r e s i s t a n c e ; / ohms / 5 int node1 ; 6 int node2 ; 7 double c u r r e n t ; / amps / 8 int changed ; / Flag t h a t i s s e t when a r e s i s t o r i s changed 9 and re a n a l y s i s o f t h e c i r c u i t i s r e q u i r e d / 10 } ; With each circuit element being stored in their own data structure, there needs to be a of way organising a collection of the data structures so that a individual element, a node for instance, can easily be located. This larger structure has to be dynamically allocated as the number of circuit elements that have to be stored will only be known after the system has started running. One method of doing this would be to create a linked list of each type of data structure. This would require adding a pointer field to each data structure that would be set to point at the next structure in the list. Finding the desired element would then require a search down the list, checking the identification number of each element until the correct one is found. This search would mean a time penalty each time a piece of information is required about a node, resistor and so on. To avoid this time penalty, a dynamically allocated one dimensional array is used instead to hold each type of data structure. The array for the node data structures is declared as follows: 1 / Create t h e node t a b l e / 2 ntable = ( node p ) c a l l o c ( s i z e, s i z e o f ( node p ) ) ; 3 i f (! ntable ) 4 { 5 p r i n t f ( Error a l l o c a t i n g memory f o r node t a b l e \n ) ; 6 e x i t ( 1 ) ; 7 } Each node is stored in the element that corresponds to its identification number. Therefore a node can be found in the array in one calculation by simply going to the array index of the id, thus removing the search time required by the linked list method. 6.4 Filling the Data Structures When the circuit analysis tool is initiated, the first thing that has to be done is to initialise the data structures. The number of nodes, resistors, voltage sources and current sources in the design being displayed in Lyric are counted up and 48

57 Figure 6.1: The A matrix passed as arguments to the function createtables(), which allocates the correct amount of memory to store the circuit elements in their respective arrays. The interface between Lyric and the system then iterates through all of the circuit elements in the design and creates the individual data structures for each of the components so that the connectivity of the design is stored in the circuit analysis system. Some simple circuit designs are also hard-coded into the system for testing purposes. 6.5 Modified Nodal Analysis Algorithm As was explained in Section 5.2 on page 34, the algorithm chosen to perform the initial circuit analysis was Modified Nodal Analysis, which is based on Equation 6.1, where A, x and z are matrices. The first step in executing this algorithm is constructing the matrices. Ax = z (6.1) For a circuit with n nodes and m independent voltage sources, A is an (n + m) * (n + m) matrix and is initialised to contain zero in each location. To be able to construct this matrix more easily, it is developed as a combination of four smaller matrices, G, B, C and D as shown in Figure 6.1. G is an n * n matrix and is determined by the interconnections between the resistors in the circuit. The sum of conductances (1/resistance) for each node fill the diagonal of the G matrix. This is implemented by examining each node in the node table in turn and iterating through the resistor identification numbers stored in the node s resistor array. Each resistor id is looked up in the resistor table to find the resistor s resistance value. The reciprocal of the resistance is taken to give the conductance which was then added to a running sum. When all the resistors for the node have been considered, the total conductance is placed in the appropriate matrix element; for node 1, this is element (1,1), for node 2 element (2,2) and so on. 49

58 The off diagonal elements are the negative conductance of a resistor between its corresponding nodes at either end. Therefore a resistor between nodes 1 and 2 goes into the G matrix at location (1,2) and locations (2,1). This is implemented by iterating through each resistor in the resistor array and determining the two nodes that the resistor joins. The resistor s resistance is then negated and the reciprocal taken to give the negative conductance and then inserted into the correct matrix location. Matrix B is n * m in size, contains only 0 or 1 values and is determined by the connection of the voltage sources. If the positive terminal of a ith voltage source is connected to node k, then the element (i,k) in the B matrix is a 1, otherwise elements of the B matrix are zero. In a ring and mesh circuit, nodes which connect to the power ring are modelled as if they are connected to the positive terminal of a voltage source. Therefore, to fill the B matrix, the voltage sources (i s) are iterated through and the node (k) to which they are attached are found, so that a value of 1 can be entered into location (i,k). Since all the matrix locations were initialised to zero at the beginning, the rest of the locations already contain the necessary 0 values. Matrix C is m * n in size and like matrix B, contains only 0 or 1 values and is determined by the connection of the voltage sources. In fact, when only independent voltage sources are considered, as with a ring and mesh circuit, matrix C is the transpose of matrix B. If the positive terminal of the ith voltage source is connected to node k, then the element (k,i) in the C matrix is a 1, otherwise the elements will be zero. The method for filling this matrix is virtually identical to that of the B matrix above. The D matrix is an m * m matrix and when only independent voltage sources are considered as is the case with ring and mesh circuits, all the elements are zero. Since the matrix is initialised to zero, nothing needs doing here to fill the D matrix. This concludes the construction of the A matrix. The x matrix is an (n + m) * 1 matrix (or vector) that holds the answers of modified nodal analysis when the algorithm finishes. The first n elements are the calculated nodal voltages, while the following m elements contain the currents though the voltage sources. Since this matrix holds the answers, it doesn t need constructing. The z matrix is an (n + m) * 1 matrix that contains the independent voltage and current sources. It is developed as a combination of the two smaller matrices i and e as seen in Figure 6.2. Matrix i is is an n * 1 matrix with each element of the matrix corresponding to a particular node. The value of each element of i is the value of any current source 50

59 Figure 6.2: The z matrix connected to the corresponding node. If there are no current sources connected to the node, the value is zero. To build this matrix, the current sources in the current source array are iterated through and the node that each is connected to is determined. The value of the current source is then entered into the matrix location that matches the node to which it is attached. Matrix e is an m * 1 matrix with each element of the matrix equal in value to the corresponding independent voltage source. To construct this matrix, the voltage sources in the voltage source table are examined one by one with their voltage value being entered into the matrix location that matches their identification number. Having constructed the matrices for the MNA algorithm, the results are determined by solving Equation 6.2 which involves finding the inverse of matrix A. As explained in Section 5.3 on page 36, LU decomposition was chosen as the algorithm for solving the equation and is discussed in the following section. x = A 1 z (6.2) 6.6 LU Decomposition Algorithm LU decomposition is based on the ability to write matrix A as the product of two matrices L and U as shown in Equation 6.3. L.U = A (6.3) L is lower triangular, which means it has elements only on the diagonal and above, while U is upper triangular, having elements only on the diagonal and below. For a 4*4 matrix A, Equation 6.3 would look like this: 51

60 Equation 6.3 can be used to solve the linear set A.x = (L.U).x = L.(U.x) = b (6.4) by first solving for vector y such that L.y = b (6.5) and then solving U.x = y (6.6) The advantage of breaking up one linear set into two successive ones is that the solution of a triangular set of equations is quite trivial [26]. In a divide and conquer type strategy, solving a set of triangular equations is much easier than solving a single standard matrix equation. This is the essence of the LU decomposition algorithm. The LU decomposition algorithm is well known and well documented. As such it is easy to find an implementation of the algorithm written in the C programming language. On the advice of this project s supervisor, the decision was made to take advantage of this fact and utilise LU decomposition procedures as found in [26], rather than creating them from scratch. While the procedures provide the basic functionality, they have been modified to work with the data structures used within the circuit analysis system as can be seen in the code listings in Appendix G. 6.7 Iterative Circuit Analysis Algorithm The iterative circuit analysis algorithm aims to quickly recalculate the nodal voltages for a circuit design in response to a change in the resistance of a branch (resistor). A change of resistance will be caused by the user thinning or fattening a wire in the design. When this is done, a flag is set on the resistor to indicate that a change has been made. At the start of the iterative algorithm, the first thing performed is a search through the resistors in the resistor table to determine whether a resistor has been modified. If not, the algorithm ends here as there is nothing to recalculate. 52

61 Having found a modified resistor, the algorithm proper begins. The first iteration revolves around recalculating the new nodal voltages of the nodes at either end of the resistor. The two nodes are stored in a linked list, with each list element containing a node id and a pointer to the next element in the list. For each node in the list the following process occurs: Firstly, the resistors connected to the node are looked up in the resistor table and their resistances added up to give the total resistance connected to the node. Secondly, the current through each of the resistors is calculated and added together. According to Kirchhoff s current law, the sum of currents at a node should be zero, but since the resistor has been changed, the equilibrium of the node has moved and so the total current will be a positive or negative value. This is the amount of current that needs to be added or removed from the node to regain equilibrium through changing the node s voltage. The change of voltage required is calculated using Ohm s law as shown in Equation 6.7. voltagechange = currentdif f erence totalresistance (6.7) This voltage can then be added to the node s old voltage value to give it a new value. However, only fifty percent of this voltage change is added rather than the whole amount. Scaling to a correction factor in this way is known as relaxation. Taking a factor of fifty percent as done here is known as under-relaxation since the scaling factor is less than 1. Doing this will ensure that the algorithm iterates more quickly to a final solution. After a node has been analysed, the nodes that are connected to it by resistors are added to a new list, if not already present. This new list contains all the nodes to be analysed in the next iteration. This process is performed on both initial nodes at the end of which the new voltage values are stored in place of the old ones. The process is then repeated iteratively on the nodes in the new list, until the stop condition is reached, as explained here: After the new voltage value has been found for a node, it is checked to see if the difference in voltage for that node is more than 0.01 percent of the largest voltage source value. This is a circuit-wide margin of error - if the change in voltage is greater than this margin for any node that is analysed, the analysis continues for another iteration. Once the changes made are smaller than this margin for all nodes analysed, an acceptable level of accuracy has been met and the outer bounds of the iteration have been found. Further iterations will contract the nodal voltages toward their true values as changes become smaller and smaller 53

62 until the original two nodes register a change in voltage which is less than the error margin and the analysis is complete. In this way, the analysis computation is localised to an area around the modified resistor, so that the whole circuit does not have to be recalculated as in the MNA algorithm. 6.8 Current Calculation Once the nodal voltages are known, calculating the current flowing through a branch (resistor) is trivial using Ohm s law. The resistors in the resistor table are iterated through and the current calculated for each. The identification number is found for the nodes at either end of the resistor and then the node structures themselves can be retrieved from the node table. The voltage of one node is then subtracted from the voltage of the other and divided by the resistance of the resistor to give the current. The following code section shows this: 1 / C a l c u l a t e t h e c u r r e n t through each o f t h e branches ( r e s i s t o r s ) / 2 for ( count = 1 ; count <= r T a b l e S i z e ; count++) 3 { 4 r e s i s t o r = rtable [ count ] ; 5 6 / Get t h e node i d s / 7 nodeid1 = r e s i s t o r >node1 ; 8 nodeid2 = r e s i s t o r >node2 ; 9 10 / Get a c t u a l node s t r u c t u r e s / 11 nodea = ntable [ nodeid1 ] ; 12 nodeb = ntable [ nodeid2 ] ; / C a l c u l a t e t h e c u r r e n t through t h e r e s i s t o r u sing Ohm s Law / 15 c u r r e n t = ( nodea >v o l t a g e nodeb >v o l t a g e ) / r e s i s t o r >r e s i s t a n c e ; 16 } 6.9 GUI implementation As mentioned in Section 5.7 on page 41, with the circuit analysis system being integrated into Lyric, it will use the same graphical user interface. The section of circuit for the analysis to be performed on is indicated by using Lyric s select tool and clicking and dragging on the circuit displayed in the graphics window to highlight it. The analysis is then initiated by selecting the new Circuit Analysis option from the Dev menu on the menu bar. The initial design for the use of colour in the interface was to use the colours of traffic lights to indicate the results of the analysis. Branches coloured green 54

63 Figure 6.3: Annotated branches would indicate that the current flowing through it is well within the specified bounds, while amber would mean the current is approaching the limit and red meaning the current is over the limit. However, after consultation with some of the staff at Pulsic, namely Jeremy Birch, it was decided it would be best to follow the colour scheme used in Lyric so that users would not be confused by the use of two different colour schemes. In Lyric, the maximum current and minimum current flowing through a circuit are calculated. Then the branches carrying the maximum amount of current are rendered a bright colour approaching white, while the branches carrying the minimum amount of current are rendered black with a red outline. The branches carrying currents with a value in between are rendered a colour on a brightness scale from white to black depending on the current value (see Appendix B for screenshots). The values of the branch currents and nodal values are also annotated on to the branches in the design display, so that the user doesn t have to rely on interpreting colour to read the analysis results. Each branch is labelled with the voltage of the nodes at either end and the current flowing through it (see Figure 6.3). Additionally, the currents and nodal voltages are also displayed in the command window at the bottom of the interface for extra clarity, so precluding the need for the user to zoom in on each branch read off the values. 55

64 6.10 Intermediate Testing Results In some intermediate testing that was conducted on a prototype version of the system, it was noticed that the results being produced by the MNA algorithm were incorrect when compared to the results return by SPICE. Comparing the results to matrix calculations made using Maple showed that the matrices were being constructed and solved correctly as Maple gave the same incorrect results. After studying the system, it was discovered that the current sources were being modelled incorrectly. The current was being stored as a positive value which would indicate that the current sources were supplying current to the circuit rather than draining it which is actually the case. This problem was easily solved by storing the current value of current sources as a negative number Summary This concludes the details of how the low level design of the system was reached and then implemented to best satisfy the system requirements. The next chapter details the testing of the system. 56

65 Chapter 7 System Testing This chapter involves testing the system to check that it meets the requirements set out in the Requirements Analysis and Specification chapter. 7.1 Test Strategy Once the system requirements were finalised, a test plan was drawn up to set out how testing was to be conducted. The basic strategy employed was black box testing - to test the functionality of the system against the requirements expected of it. As such, the test plan, which can be found in Appendix C on page 76, sets out the requirements of the system, an outline of a test to be performed to check that the requirement has been met and the expected outcome for passing the test. Although this system is planned for use in the commercial world as part of the Lyric Physical Design Framework, the testing performed here will not be sufficiently detailed to ensure that the system is completely bug free and ready for general release. The volume of testing required for this would be beyond the scope of the project. Here the testing is sufficient enough only to determine if it satisfies the initial requirements. Further testing will be required before the system is ready for sale. The remainder of this chapter explores the most important tests, how they were implemented and the results gained. 57

66 7.2 System Accuracy As stated in the the Requirements Analysis and Specification chapter, one of the requirements is for the system to produce accurate results from the initial circuit analysis using MNA. Since SPICE is a circuit analysis tool and somewhat of an industry standard, it was decided that the best test of accuracy was to input the same circuit designs into both the system s MNA algorithm and Cadence PSpice (a version of SPICE) and compare the results. Since circuit designs are entered into PSpice by dragging and dropping components onto a canvas, it is difficult to create very big designs. For this reason, the rather simple designs Test Design 1 and Test Design 2 (see Appendix D, page 78) were created for this test, as they are easy to enter into PSpice. The fact that the circuits are small shouldn t impact on the reliability of the tests, since the same procedure is carried out irrespective of the circuit design. The output that is important from these tests are the nodal voltages that are calculated. The branch currents are not important since they are calculated using the nodal voltages and so will depend on them. If the two systems produce the same nodal voltages, the currents are guaranteed to be the same. After analysing the two test circuits, the results outputted by the circuit analysis system and PSpice are the same, except for the fact that this project s system provides a greater degree of accuracy (see Appendix E, page 80). While the test was not exhaustive since only two simple cases were considered, it is sufficient enough to indicate that the system s MNA algorithm does provide accurate results. The iterative algorithm takes as input the results of MNA and recalculates the nodal voltages in response to a change in a branch resistance. While the emphasis here is speed, the results produced must still achieve a good level of accuracy. To test this accuracy, Test Designs 1 was run through the MNA algorithm to produce the initial results, then a change was made to the circuit and the results recalculated using the iterative algorithm. The updated circuit was also analysed by PSpice to determine what the true nodal values should be and then a comparison was made. The following table shows the results: 58

67 PSpice Iterative Algorithm 5.000v v 3.999v v 3.000v v 4.399v v 3.997v v 0.623v v 2.249v v 4.199v v 4.000v v 3.125v v The table shows that the iterative algorithm is accurate to within an average of 0.01v when compared to the results produced by PSpice. This is a good level of accuracy when the speed at which these results are found are considered. 7.3 Speed of the Iterative Algorithm One of the most important requirements of the circuit analysis system is that it should quickly recalculate the results in response to small changes to the circuit design. This is the responsibility of the iterative algorithm. To test the speed of the iterative algorithm, circuit designs were analysed by MNA, then a change was made to the circuit before being re-analysed by the iterative algorithm. The time taken for each analysis were measured by using functions from the C time.h library as follows: 1 s t a r t t i m e = c l o c k ( ) ; 2 f r e q = CLOCKS PER SEC ; 3 4 / Perform a n a l y s i s / 5 6 endtime=c l o c k ( ) ; 7 p r i n t f ( time taken = %l f \n, ( ( double ) ( endtime s t a r t t i m e ) / f r e q ) ) ; This above code prints the time taken for the analysis to the screen. The nodal voltages and branch currents calculated by each algorithm were also printed to separate files so it could be seen that they were both producing results. For the test to work, circuit designs were needed which would take long enough to analyse so as to be able to measure the time taken. For this reason, a function called createbigdesign() was written which would automatically produce large mesh circuits. 59

68 The test produced the following results: Number of nodes in circuit MNA algorithm time Iterative algorithm time seconds seconds seconds seconds seconds seconds The iterative algorithm seems to work so quickly that the timing function doesn t register that its taken any time at all. Certainly by watching the test execute it can be seen that it terminates almost instantaneously. However, it can be proved that the algorithm has worked, by performing a diff on the output files produced by the two algorithms during the test. The diff shows that the files are different in certain places where the iterative algorithm has recalculated some values. This test shows that the goal to be able to re-analyse a circuit rapidly without having to re-compute every node has been met. While there was no emphasis on the Modified Nodal Analysis algorithm to be as fast as possible, as the tests were conducted on it and compared to PSpice, MNA seemed to produce results faster than PSpice, although no actual timings were taken to back this up. 7.4 Multi-platform Ability Since Pulsic provides Lyric to run on a variety of platforms, it is necessary that the circuit analysis system be able to run on those same platforms and produce consistent results. To test that the circuit analysis system is able to function on multiple platforms, it had to be installed on a range of platforms and then run with Test Designs 1 and 2. While Lyric is compatible with various versions of Windows, SuSE Linux, RedHat Linux, Solaris and HP-UX, it is asking to much of this project to test the system on all of these platforms. Therefore the system was installed on a selection of the above including: Windows XP Professional, SuSE Linux 9.0 and Solaris 8. It was also intended to test the system on a machine running HP-UX 11.11, but this computer was unavailable at the time this testing was being carried out. For the test to be successful, the system should produce the same results on each of the platforms. The results of the test are displayed in Appendix E on page 81. They show that the nodal voltages calculated by the system on all three test beds are the same. 60

69 While this test did not explore all the possible platforms that the system may be called upon to be compatible with, it has showed that it is possible to run circuit analysis accurately on more than one platform. 7.5 Reliability It is important for any computer software to be reliable, but it is especially so for that which is to be sold commercially. If the system is to be released as a tool for Lyric, it will have to uphold the reliability standards maintained by Pulsic Limited. Testing for the reliability of software involves many hours of user testing, trying out all the combinations of actions on all possible platforms in order to find bugs and errors. While this scale of testing is not feasible for this project, some staff at Pulsic spared some time to perform some simple circuit analyses using the system. The testing did find a couple of bugs. A bug was found that occurs only when the system is used on Windows XP and SuSE Linux systems and causes the system to crash. The bug has been tracked down to a section of code that cleans up when the system is exiting. The code cycles through all of the data structures used by the system and frees the memory, when it appears that it tries to free a pointer that causes a crash. The reason for this has yet to be determined, but the fact that the bug has been located will mean a solution should be able to be found. The second bug that has arisen from this user testing is that the system does not allow a new circuit analysis to begin after having finished one. The system has to be restarted before another circuit analysis can be initiated. The reason for this bug is not an error with the circuit analysis system, but rather its interface with Lyric. The job of integrating the system into Lyric was a difficult one that had to involve help from Pulsic s Jeremy Birch as the author did not have a great enough understanding of Lyric to be able to do it themselves. Since Mr Birch is a very busy person, he could only spare enough time to ensure the interface would work, but there are still areas that need tidying up. With a bit more time, this bug can easily be located and fixed. 61

70 7.6 Usability Testing It is important that the circuit analysis system is easy to use and integrated into Lyric in a fashion that maintains the look and feel of the software. To determine whether the system satisfied these needs, some of the Pulsic staff participated in some user testing. They simply carried out circuit analysis on some simple designs and gave feedback on what it is like to work with. The users seemed to think that the system was easy to use. With the circuit to be analysed being chosen using Lyric s Select tool using the mouse, and the analysis being initiated by selecting an item from the Dev menu, they felt it was very familiar as it mimics the way many of Lyric s other tools function. Users also found the results of the analysis easy to understand. Since the system uses the same colouring system as Lyric to show the current through each of the branches, the users could easily determine the results. This allied to the fact that the results are annotated onto the branches in the circuit and printed to the Lyric command line interface meant that they could choose to view the results in any of three ways, which seemed to be appealing. Finally, the users seemed to think the system maintained Lyric s general appearance since the changes made to the interface were so slight. The system mostly takes advantage of features already part of Lyric, so as not to confuse users. As is apparent, the feedback from the usability testing was positive, even if the testing wasn t as exhaustive as it might have been. 7.7 Summary To conclude, the system testing shows that the circuit analysis system produces accurate results, is able to work on a range of platforms, contains few bugs and appears to be easy to use. 62

71 Chapter 8 Conclusion This chapter reflects upon the system and the project as a whole, identifying the good points and the bad points and recognising work that could be done in the future. 8.1 Meeting Requirements As has been seen in the System Testing chapter and in the test plan, the system seems to have met most of its requirements quite well. The MNA algorithm appears to provide a satisfactory solution for performing the initial circuit analysis. The fact that it returns results that are identical to those produced by PSpice indicates that it is accurate, while it is also fairly fast although this was not a priority. The iterative algorithm has been a success in that it has been able to localise computation to avoid having to re-analyse an entire circuit. This is born out by the testing which showed that it took virtually no time at all to recompute the nodal voltages in a circuit after a single branch resistance was changed. The circuit analysis system has been shown to work on at least some of the platforms that Pulsic support. While not all of the platforms have been tested, there is no reason to believe that it wouldn t be possible to have the system work on any given platform. Although a few tweaks may be needed to deal with any difference in the native GCC compiler. The users at Pulsic seem to be enthusiastic about the system, which seems to point at it being rather user friendly. This is due to the fact that the interface 63

72 with Lyric was designed in such a way to cause as little confusion and disruption for the user as possible. However, it can t be said that the system has met the requirement of being reliable, since there are a couple of bugs that exist that were flagged up by the system testing. These will have to be eradicated and some exhaustive user testing performed before the system would be ready for commercial release with the Lyric software. 8.2 Positive Aspects The fact that a working circuit analysis system has been implemented that produces accurate results has to be considered a huge positive. This was a difficult aim to achieve but the project has been largely successful. The iterative algorithm was a particular success also in the way in manages to localise computation. The algorithm was created based on the knowledge of some other algorithms in order to solve the challenge of quickly re-analysing a circuit. It is not known whether other algorithms exist that use the same techniques, or whether it is an entirely new solution to the problem. The fact that the system has been integrated into the Lyric Physical Design Framework shows that it also so has value in the commercial world. If an agreement can be made between the University of Bath and Pulsic Limited over who owns the intellectual property rights of the system, Pulsic will sell the circuit analysis system as part of their software. 8.3 Things That Could Be Improved As the System Testing chapter highlighted, there is a bug that rears its head on some platforms when the system tries to free all the memory it has allocated and exit. It would have been better if the cause of this bug were found and fixed, but this is something that will have to be done at a later date. There are some issues with the how the system is integrated into Lyric that cause some problems. One such problem as highlighted in Section 7.5 on page 61 is the inability to perform a new circuit analysis after having just finished one without reloading the tool. Issues like this occur as the integration was more of a rush job than it should have been. The reason for this is that Lyric is a very complicated piece of software and so the integration had to be done with the help of Pulsic s Chief Technology Officer, Jeremy Birch. Since he is a very busy person, he could 64

73 not spare enough of his time for the integration to be completed to the highest standards. The integration will hopefully be improved in the future as more time is spent on it. The system could also have been tested more thoroughly. For the purposes of the project, the system has probably been tested enough, but a lot more testing should be done to ensure that it is reliable enough to be released to Pulsic s customers. The time management during the execution of the project left a lot to be desired. The initial stages of the project were carried out adequately, but during the middle and latter stages, the work was not getting completed according to the schedule set out in the project plan. There were some medical issues that impacted on this, but in hindsight they should have been resolved sooner so that the end of the project did not need to be completed in a rush. 8.4 Future Work The work that could be done on the system in the future will mostly cover the areas that were deemed to be outside of the scope of this project Full Chip Analysis So far the circuit analysis system has concentrated on analysing only ring and mesh circuits since these are easy to model and made the project achievable. However, this is only one type of circuit that may be found in an integrated circuit design. With modern chips containing more than ten million components, there are many other types of circuit that require analysing to ensure that the chip is reliable over its entire surface area rather than just sections of it. The expansion to analysing whole chips may mean that the algorithm for performing the initial circuit analysis will have to be modified. It took MNA ninety seconds to analyse a ring and mesh with 1600 nodes, so it could take a prohibitive amount of time for really large circuits Accommodation of Active Circuit Elements The circuit analysis system has only been considering circuits which contain passive components. Ring and mesh circuits only contain resistors and independent 65

74 current and voltage sources which are all passive devices; they consume energy rather than produce it. Active circuit elements such as transistors have the ability to control the flow of energy and as such are much harder to model and analyse. To be able to incorporate active devices into the circuit analysis, further research will have to be carried out on the various different types of active component and how they affect the flow of energy so that they can be modelled accurately. Understanding their behaviour would then allow algorithms to be developed and implemented so that circuits containing active devices can be analysed AC Circuit Analysis The circuit analysis system has so far concentrated on only performing DC analysis in order for the project to be of achievable size. The step could taken however to modify the system to perform AC circuit analysis, although this may prove to be a difficult task as AC analysis is performed in the frequency domain whereas DC analysis is in the time domain. This change in domain means that the Ohm s law that was implemented by the system (V = IR), would have to be generalised to take into account capacitors and inductors. The voltage across and current through a component in a circuit would have to be represented as complex variables as follows: These generalisations obviously make the computations necessary much more difficult. Further research would have to be done into AC circuit analysis techniques such as phasors and laplace transforms in order to implement a successful AC analysis tool Heat Maps Producing heat maps was considered as a requirement for the circuit analysis tool before being dismissed due the complexity of the task. As the integration of microchips becomes greater and greater and the spaces between components reduces, the problem of overheating is becoming more important. The idea of heat maps is to analyse the circuit elements of a chip and determine the heat they are generating based on the current flowing through them, the voltage across them, the thermal conductivity of them and so on. This information 66

75 is then used to produce a graphical representation (or map) of the heat being outputted across the chip. Chip designers can then see where problems may arise due to overheating and rearrange the circuitry or add heat sinks to correct them. Producing these heat maps is a mammoth task and would require considerable research into the field of thermodynamics Beyond Circuit Analysis The reason for creating a circuit analysis system was to enable chip designers to create more reliable microchips by highlighting areas susceptible to the issues of electromigration and IR drop. However, these are not the only types of problem that can cause chip unreliability, there are other issues such as failures in the logic can that cause a chip to behave unexpectedly. Therefore, the system could be expanded to include testing of the logic of a chip design. Implementing this would require extensive research into how logic is implemented in a circuit and how to test that if it will work correctly. 67

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80 Appendix A Example ring and mesh from an IC design in Lyric Figure A.1: The thick track that runs around the outside of the gridded area is known as a ring. It is a track of metal that supplies power. The gridded area is known as a mesh. It is a grid of wires that delivers power from the ring to the cells beneath it. 72

81 Appendix B Screenshots Figure B.1: Circuit analysis in Lyric 73

82 Figure B.2: Colouring of the branches after circuit analysis Figure B.3: The Lyric toolbar 74