PIEZOELECTRIC materials can be fabricated as a generator

Transcription

1 electric Micro-power Generation to Charge Supercapacitor with Optimized Duty Cycle ZHOU ZHAO,* SHIRUI WANG AND CHAO YOU Department of Electrical and Computer Engineering, North Dakota State University, Fargo, ND, USA ABSTRACT: Energy harvesting has been proved to be a novel solution to replace the batteries in remote power supply applications. Unfortunately, the limited capacity and low efficiency of output power constraint the practical applications of energy harvesting in daily life. After a systematic review of previous researches about energy harvesting in power management perspective, a circuit design, which focuses on low-frequency mechanical vibration, is introduced. With classical piezoelectric cantilever configuration, the maximum charging current of a supercapacitor can be obtained by optimizing the duty cycle of a buck regulator through software implemented pulse width modulation. The results of experiments prove the capacitive electric model of the piezo, the existence of maximum charging current of the supercapacitor, and the adaptive control of the designed circuits. With the duty cycle optimized to 2.17%, the maximum charging current of ma is measured, which is approximately four times fold of previous researches in similar vibration conditions. An active RFID application is proposed to utilize the harvested power of 67.2 mw. Key Words: piezoelectric devices, energy storage, DC DC power convertors, capacitors, pulse width modulation. INTRODUCTION PIEZOELECTRIC materials can be fabricated as a generator to transform mechanical energy in ambient vibration into electrical energy, which can be stored and used to power some ultra low-power devices such as radio frequency identification (RFID) tags. Since most of the ultra low-power devices are wireless, it becomes essential to have their own independent power supplies. In tradition, the power supplies come from bulky batteries, which have environment unfriendly chemical ingredients. Most importantly, the batteries have limited life of cycles compared to millions or more for most commercially available supercapacitors. With the development of wireless sensor network and microelectromechanical systems technologies, intelligent sensors are developed to be embedded in remote locations such as structural health monitoring sensors embedded in the bridges, medical sensors implanted in the human body, and global positioning system sensors attached to animals to track their behaviors in wildlife. Obtaining the sensors to replace the batteries could be very time-consuming and expensive. In the embedded case, the accessibility is even impossible and destructive. If a strain energy scavenging technology is realized, the life spans of those sensors could be extended *Author to whom correspondence should be addressed. zhouzhao@usc.edu significantly or even the batteries themselves could be replaced. There are many researches that successfully realize energy harvesting in the labs, but the total power efficiencies of the designed systems are constrained by the tradeoff among efficiencies of each subsystems. For instance, some researchers pay much attention to maximizing the output power of the piezoelectric source, but the useful power stored in the energy buffer is degraded by the significant power dissipation of the regulator. Based on systematic analysis of piezoelectric energy harvesting in power management perspective, the maximum charging current of a supercapacitor with optimized duty cycle is investigated. In the Background section, the previous researches are categorized along the power flow of energy harvesting. In the Theory section, the electrical model, output power of a piezo, and charging a supercapacitor are introduced. The circuit design and implementation are described in the Implementation section. The experiment setup and results are presented in the final section. BACKGROUND Sodano et al. (2004) presented a comprehensive review of piezoelectric energy harvesting, in which researches were summarized in categories including piezoelectric theoretical fundamentals, mechanical JOURNAL OF INTELLIGENT MATERIAL SYSTEMS AND STRUCTURES, Vol. 21 July X/10/ $10.00/0 DOI: / X ß The Author(s), Reprints and permissions:

2 1132 Z. ZHAO ET AL. Conversion efficiency vibration, power efficiency, storage circuitry, and wearable applications. Generally, the motivations of power management focus on efficiency improvement by reducing power dissipation of the whole system, which increases system stability, saves cost, and reduces impact on the environment. The methods to improve the efficiency of energy harvesting system can be categorized into four blocks along the energy harvesting power flow as shown in Figure 1. They include optimizations in conversion efficiency of energy source, transfer efficiency from the source to the load, buffering efficiency of the energy storage device, and consumption efficiency of the load. The techniques of designing the structures of piezoelectric material and ultra low-power applications are out of the scope of this article. The article focuses on transfer and buffering efficiency optimizations. Transfer Efficiency Transfer efficiency Buffering efficiency Figure 1. Power flowchart of energy harvesting system. Consumption efficiency Due to the capacitive characteristic of the piezoelectric materials, a power regulator is needed in the subsystem of transfer efficiency. Many control mechanisms of the power regulator have been proposed to improve the transfer efficiency. Kasyap et al. (2002) designed a flyback converter whose input impedance did not depend on the load. With impedance match between the piezo and the converter, peak power efficiency of 20% was achieved with 80% flyback converter efficiency. Ottman et al. (2002) presented an adaptive control scheme using charging current versus duty cycle curve. The maximum charging current of 4.3 ma was available with optimal duty cycle of 3.18% at a rectifier voltage of 20.4 V, which approximated the half of the open circuit voltage of the piezoelectric source. With the highest mechanical excitation level of V open circuit voltage, the harvested power increased from to mw with converter power loss of mw. Hofmann et al. (2003) designed a stepdown converter operating in discontinuous conduction mode to reduce the power loss of the digital signal processor (DSP). With switch frequency of 1 khz, the optimal duty cycle approached constant of 3.16%. The harvested power increased from 9.45 mw by direct charging to mw with converter efficiency of 65%. Le et al. (2006) proposed a circuit to solve the problem that conventional diode rectifier did not provide efficient power conversion of piezo. Tan et al. (2008) presented a synchronous charge extraction circuits which increased the output power of piezo from 1.75 to 5.6 mw. Ramadass and Chandrakasan (2009) demonstrated a bias-flip rectifier circuitry with a shared inductor to improve the power extraction from piezo up to 4.2 times compared with regular full-bridge rectifier. Unfortunately, most of these techniques did not consider the charging characteristics of the buffering subsystem, which is very important in optimizing the usable power for the load. In addition, strong strain with vibration frequency up to khz is fully investigated. However, the strong vibration is limited in industry applications while most vibrations cannot be even sensed in daily life. Therefore, this article focuses on efficiently harvesting usable energy stored in the buffer from more popular low-frequency microvibrations. Buffering Efficiency Due to the low current output characteristic of the piezo, the harvested energy cannot be directly used by most electronics without accumulating a significant amount of charge in energy storage devices such as capacitors or rechargeable batteries. Umeda et al. (1997) investigated the impact of varying the size of capacitances on the efficiencies of the energy harvesting system. Sodano et al. (2003a) investigated the possible power output from the piezoelectric materials in cantilever configuration. They emphasized using capacitors as a method of energy storage for direct energy access. Sodano et al. (2003b) presented the results of charging various sized batteries using piezoelectric energy harvesting. The numerical equations between energy efficiency and vibration parameters were derived. Because of high power density, supercapacitors have been widely used in energy harvesting applications such as vehicle regenerative braking (Cerovsky and Mindl, 2005). Simjee and Chou (2006, 2008) designed a power regulator using a supercapacitor as an energy storage device, which proved that supercapacitor has better efficiency than battery to store the intermittent energy harvested from the piezo. THEORY This section investigates the theories about the output power of a piezo and supercapacitor charging technique. The piezo in cantilever vibration can be modeled as a sinusoid current source paralleled with parasitic capacitance as shown in Figure 2 (Ottman et al., 2002). The generated AC power needs to be converted to DC power before a load can use it. The output power of piezo is derived in the following section. Based on the equations in the following section, the derivations about maximized supercapacitor charging current are investigated in the section Charging Supercapacitor. Output Power The ideal current waveforms generated from the piezo i p (!t) and the rectified output current i o (!t) are

3 electric Micro-power Generation 1133 i p (ωt) i p (ωt) I p o V p (ωt) V rect V rect i o (ωt) i o (ωt) o C p Piezelectric model Vp (ωt) kπ IV I II III o kπ π (k 1)π kπ π π (k 1)π (k 1)π Figure 3. Voltage and current waveforms of a full-wave rectifier. D 3 i o (ωt) D 1 D 2 D 4 2π 2π 2π i o (ωt) C rect Vrect R l Figure 2. electric capacitive model with a full-wave rectifier and loads. ωt ωt ωt V o by Equation (1) in one period: i o ð!tþ ¼ 0, for 0!t k; ji p ð!tþj, for k!t : ð1aþ ð1bþ The DC component of output current flowing through the resistive load hi o (!t)i can be evaluated as: hi o ð!tþi ¼ 1 Z k I p sinð!tþd ð!tþ in which I p is the amplitude of current i p (!t). Equation (2) can be reduced to: hi o ð!tþi ¼ I p ð1 þ cos kþ: ð3þ In order to figure out the hi o (!t)i, the cos k in Equation (3) can be evaluated by the current and voltage relationship across the C p, which is: C p dv p dt ¼ I p sin!t: Multiply dt with both sides of equation and integrate over the period from 0 to k: Z Vrect! C p dv p ¼ V rect Z k 0 I p sin!t d!t, ð2þ ð4þ ð5þ shown in Figure 3. The waveform of voltage across the piezoelectric electrode capacitor V p (!t) can be divided into four operation periods. In the period of I, the voltage V p (!t) is equal to the voltage V rect and the current i p (!t) is positive. Therefore, the diodes D 1 and D 4 are conducting. When the current i p (!t) becomes negative at the point of, the C p is discharged. Thus, the voltage V p (!t) is decreased and all diodes are reversed-biased in the period of II. The insulation between the piezo and load continues until the voltage V p (!t) is reverse charged to the voltage of V rect at (k þ 1). Then, the diodes D 2 and D 3 are conducting and the voltage V p (!t) are maintained constant of V rect in the period of III. When the current i p (!t) becomes positive at 2, the voltage V p (!t) is charged back to V rect in period IV. When the magnitude of voltage V p (!t) is smaller than V rect, all diodes are reversed-biased and no current flows through the resistive load in periods II and IV. In periods I and III, output current flows through the rectifier capacitor C rect and the resistive load R l. Assuming C rect C p, the majority of the generated current will be delivered to the resistive load instead of maintaining the voltage across the electrode capacitor C p when the diodes are conducting. The output current i o (!t) can be represented which can be reduced to: cos k ¼ 1 2!C pv rect I p : ð6þ Substitute cos k in Equation (3) with the Equation (6), the hi o (!t)i can be represented as: hi o ð!tþi ¼ 2I p 2V rect!c p : ð7þ The output power of the piezo can be shown to vary with the value of the V rect as: Charging Supercapacitor Pð!tÞ ¼ 2V rect ði p V rect!c p Þ: ð8þ There are three methods to charge a supercapacitor: constant current charging, constant power charging, and AC line charging. The constant current charging is the quickest form with controllable charging current. Since the power generated by the piezo has the characteristic of

4 1134 Z. ZHAO ET AL. high voltage with low current, a buck regulator is usually an essential topology not only to regulate the output voltage to an applicable range but also strengthen the current driving capability of the piezo. In addition, continuous output current of the buck regulator overwhelms other switching mode regulators in the supercapacitor charging application (Maxwell, 2005). The electric model of a supercapacitor with a buck regulator and a piezoelectric model are shown in Figure 4, in which the equivalent parallel resistance of the supercapacitor is R c. The regulated charging current i c can be represented in Equation (9) in the continuous conduction mode: i c ¼ hi oð!tþi, ð9þ k in which hi o (!t)i and k are the DC component of piezo output current and duty cycle of the buck regulator, respectively. Since the relationship between input and output voltages of the buck regulator maintains: kv rect ¼ V o : ð10þ Using Equations (7), (9), and (10), the charging current of the supercapacitor can be represented as: i c ¼ 2I p k 2V o!c p k 2 : ð11þ In addition, the voltage and current relationship across the supercapacitor maintains: dv o dt ¼ i c C s : ð12þ Since the capacitance of the supercapacitor is so huge, the output voltage across the supercapacitor will be almost constant when the charging current is in limit range (Gualous et al., 2007). Therefore, if the charging current is maximized, the power supplied to the supercapacitor is maximized. Substituting k 1 in Equation (11) with x yields: which is equivalent to: i c ¼ 2V o!c p x I 2 p þ 2V o!c p I 2 p 2V o!c p : ð14þ The charging current of supercapacitor i c can be maximized only when x is equal to I p 2V o!c p, which means the optimized duty cycle can be represented by: kðoptþ ¼ 2V o!c p, ð15þ I p and the maximized charging current is: i c ðmaxþ ¼ IMPLEMENTATION I 2 p 2V o!c p : ð16þ The architecture of designed piezoelectric energy harvesting system is shown in Figure 5. A buck regulator is designed to regulate the power flow from the piezo to the load. A feedback control system is designed in obtaining the optimized duty cycle according to the charging current of the supercapacitor across a current sensitive resistor to make sure the charging current is maximized. The signal of charging current is amplified, digitized, and sent to a field programmable gate array (FPGA) for optimal duty cycle computations. In the following section, the elements used in the buck regulator are evaluated. The feedback control system is introduced in the later section. DC DC Buck Regulator The classical circuit diagram of a buck regulator is shown in Figure 6 (Rashid, 2003). The maximum voltage drop between the source and drain of the power switch Q 1 appears when Q 1 is turned off and the input voltage is maximized. In addition, the peak current Q 1 L i c ¼ 2I p x 2V o!c p x 2, ð13þ C rect D m C s R l R s electric model C rect i o (ωt) Vrect Buck i c C s V o R c Supercapacitor electric model Feedback control system Terminal Driver FPGA 0.15Ω Buffer ADC Amplifier Figure 4. Electric model of a supercapacitor with a piezo and a buck regulator. Figure 5. Architecture of a piezoelectric energy harvesting system.

5 electric Micro-power Generation 1135 flowing through the Q 1 is equal to the maximum current flowing through the inductor L when the Q 1 is conducting. According to the peak-to-peak ripple current of the inductor L, the peak current can be evaluated as: I 2 ¼ V oðv s V o Þ þ I 1, ð17þ flv s in which the I 1 and I 2 are minimum and maximum of the inductor current, respectively, as shown in the Figure 7. In order to minimize the power dissipation of the conducting D m, a low forward voltage drop zener diode is used. The zener diode has only 5 ma leakage current when reversed-biased at 29.7 V. In addition, it has 115 ma surge current, which is much higher than the calculated peak inductor current of 26.8 ma. The absolute maximum ratings of the Q 1 are V dss ¼ 200 V, I d ¼ 18 A with turn-on resistance of 0.15, which decreases the power dissipation when the switch is conducting. Since the assumed highest open-circuit DC voltage of the piezo is about 20 V, a switching frequency of 1 khz and a 33 mf, 35 V voltage rate electrolytic capacitor is adopted. i s V s i L I 2 I 2 I L I 1 I L o V c ðmaxþ ¼ V oðv s V o Þ 8LCf 2 V s þ V o : ð18þ I 1 II I o kt i C V C o Q 1 D m kt kt III i L IV T T T (k 1)T (k 1)T (k 1)T Figure 7. Waveforms of a classical DC DC buck converter. L A i c i o V c C R l V o Figure 6. Schematic of a classical DC DC buck converter. 2T 2T 2T t t t As shown in Figure 7, the waveform of the capacitor current i c can be divided into two periods. In period III, the i c is positive, which means the capacitor is charged. In period IV, when the i c becomes negative, the capacitor is discharged. The maximum output voltage across the capacitor can be evaluated by Equation (18). Since the expected maximum output voltage across the supercapacitor is less than 2.5 V, the design uses a 400 F, 2.5 V voltage rate supercapacitor as the energy buffer, which has 5.10 Wh/kg energy density and very low DC equivalent series resistance (ESR) of 3.2 m. In order to maintain the continuous current flowing through the inductor, this design employs a 140 mh inductor. Feedback Control System In order to use the charging current of the supercapacitor to control the duty cycle of the buck regulator, an analog-to-digital converter (ADC) is used to sample the voltage across a 0.15 current sensitive resistor as shown in Figure 5. Since there requires sufficient time to stabilize the charging current, the ADC samples the signal at 1 Hz with a 2-pole Sallen-Key filter. The sampled data is sent to the FPGA through serial peripheral interface (SPI). After the conversion, the ADC works in the shutdown mode to decrease power dissipation. Optimized Duty Cycle Computation: The flowchart of optimized duty cycle generation is showed in Figure 8. In system initialization, the output duty cycle is initialized to 100% and an 8-bit counter in FPGA is set to 255. Then, the duty cycle will decrease 0.39% per second, during which the sampled current is stored in on-chip memory. After 256 steps, the optimized duty cycle corresponding to maximized charging current is obtained among the 256 sampled data. The total process time to obtain the optimized duty cycle is about 4 min, which can be reconfigured according to different application requirements. If the mechanical vibration of the piezo is changed, the sampled instantaneous charging current is changed. The program will re-initialize to obtain the new optimized duty cycle to maximize the corresponding charging current. Software-defined PWM: The pulse width modulation (PWM) generation is implemented by using instructions executed by a PicoBlaze processor in the FPGA. The digital system design in the FPGA is shown in Figure 9. The software implementation indicates that the dynamics of the PWM are totally flexible by the instruction executions in the processor. The two key parameters of the PWM are the pulse repetition frequency (PRF) and the resolution of the duty cycle. This design has the PRF of 1 khz and the

6 1136 Z. ZHAO ET AL. resolution of 8-bits. Each step can be resolved at intervals of: 1ms 2 8 ¼ 3:90625 ms: ð19þ The PicoBlaze processor is a highly predictable processor requiring precise two clock cycles to execute one instruction. Although the PicoBlaze processor can be clocked faster in a higher speed grade of FPGA devices, this design makes direct use of a 50 MHz crystal oscillator on a development board. The PicoBlaze processor is able to execute 25 million instructions per second or Initialize counter=255 Counter=0? No Sample current Store the sampled current in memory Decrease the duty cycle of PWM Decrease counter by1 ISR Yes Find the maximized charging current Output optimized PWM duty cycle Sample current Current change? Yes Figure 8. Algorithm of duty cycle computation in the processor. No one instruction every 40 ns. The amount of instructions that can be executed within the ms step interval to support the PRF and duty cycle resolution is: 3:90625 ms 40 ns ¼ 97: ð20þ Increasing the PRF or the duty cycle resolution will reduce the number of instructions, which can be executed during each step. In the end, there will only be enough instructions available to generate the PWM itself. Higher clock rates can be a solution only when the speed grade of FPGA permits. However, 97 instructions in this design are adequate to drive the PWM signal and still have approximately 50% of the processor resources available for the higher level control tasks such as dealing with the universal asynchronous receiver/ transmitter, processing the text commands from the terminal, and communicating with the ADC through the SPI interface as shown in Figure 9. EXPERIMENT The experiment setup is shown in Figure 10(d). The experiment uses piezo, QuickPack QP20W, from Mide Inc., which is shown in Figure 10(a). The bimorph piezo has two 10 mil depth piezoelectric materials stacked in one epoxy. The specifications of the piezo is shown in Table 1. The piezo equivalent capacitance is only 0.2 mf, which is much smaller than the 33 mf rectifier capacitor used in the design. Therefore, most of the power generated from the vibrating piezo will feed into the load during the conduction of the diodes. One edge of the piezo is fixed on a mechanical wave vibrator in horizontal cantilever configuration as shown in Figure 10(b). The mechanical wave vibrator has frequency response of khz with an amplitude Address ROM Instruction RXD ADC MUX1 1 Sel Input Output PicoBlaze 8 Processor 8 0 MUX2 1 Sel 8 TXD PWM Port select 8 Interrupt Counter 8 Decode at 195 D Q1 Q CLR D Q Q2 Interrupt ack CK Q CK PR Q CLK Figure 9. Architecture of the digital system in a FPGA.

7 electric Micro-power Generation 1137 displacement up to 7 mm at 1 Hz. The maximum vibration amplitude will decrease when the vibration frequency is increased, which can simulate the practical microvibration in daily life. Since the driving signal of the vibrator requires a function generator with minimum of ±8 V, 0.5 A output, an accurate frequency adjustable signal generator with a power amplifier is used to drive the mechanical wave vibrator. In order to simulate the low frequency vibrations with acceptable output voltage level from piezo and not to break the fragile piezoelectric material, three experiments are conducted with frequency of 7 Hz with constant vibration amplitude. The variations of the vibration is beyond the scope of this article. The harvested energy from the piezo is rectified, regulated, fed to the supercapacitor through a designed printed circuit board (PCB) shown in Figure 10(c). The ADC module in Figure 10(d) samples the charging current of the supercapacitor and sends the information of charging current to the PicoBlaze processor in a Spartan-3E FPGA. The generated PWM signal from the FPGA general-purpose IO drives the power MOSFET in the buck regulator through a driver. Meanwhile, the information of the charging current and duty cycle is sent to a terminal through a serial communication. The piezo was measured with open circuit in the first experiment. The open circuit peak-to-peak voltage V oc (pk pk) generated from the piezo is about 87.0 V and measured root mean square (RMS) value V oc (rms) is about 28.9 V. When the piezo is paralleled with a variable resistive load, the RMS value of output voltage across the resistive load is measured with different resistances as shown in the Figure 11(a). When the load are set to 100 k and 1 M, the RMS value of output voltage across the load are approximately 5 V and 22 V, respectively. The corresponding output power of the piezo are about 0.25 and 0.48 mw. When the resistive load is increased to above 2 M, the resistive load behaves as an open circuit and the RMS value of output voltage approximates to open circuit voltage of 28.9 V, which shows the power generation capability of the piezo at 7 Hz vibration frequency. In the second experiment, the piezo is paralleled with a 100 mf capacitor without any resistive load. When the vibration frequency is 7 Hz, the capacitor can be charged up to 20.3 V. After the 100 mf capacitor is Table 1. Specifications of piezo, QuickPack QP20W. Specifications Value Device size (inch) Device weight (oz) 0.28 Active elements 1 stack of 2 piezos wafer size (inch) Device capacitance (mf) 0.20 Full scale voltage range (V) ±200 (a) (b) (c) 3.69 inch (d) Designed PCB Supercapacitor 4.31 inch PWM output FPGA development board ADC Vibrator Figure 10. Setup of experiment: (a) packaged piezo QP20W from Mide Inc., (b) cantilever configuration of the piezo on a vibrator, (c) PCB board of a buck regulator with interfaces, (d) experiment setup of the piezoelectric energy harvesting system.

8 1138 Z. ZHAO ET AL. (a) f c =7HZ V oc (pk-pk)=87.0v V oc (rms)=28.9v (b) f c =7HZ V oc (mean)=20.3v Output rms voltage (V) V o Output power (mw) V c V o ( ) ( ) (c) f c =7HZ V oc (rms)=28.9v The charging current of supercapacitor (ma) V c Buck Feedback V o R s ( ) Figure 11. Results of experiment: (a) output voltage of piezo with a direct resistive load when V oc (rms) ¼ 28.9 V, (b) output power vs mean output voltage when V oc (mean) ¼ 20.3 V, (c) charging current of supercapacitor vs duty cycle when V oc (rms) ¼ 28.9 V. paralleled with a variable resistive load, the stable voltage charged on the capacitor will depend upon the load resistances. When the resistance is increased, the charged voltage will increase, because the discharge current is decreased. The relationship between output power and the charged voltage is shown in Figure 11(b). As the resistive load is increased from 10 k to 1 M, the mean output voltage will increase from 420 mv to V, and the output power will increase from 0.02 to 0.1 mw. Although, the mean output voltage keeps on increasing when the resistive load is increased, the output power is decreased after the mean output voltage reaches 10 V. The maximum output power of 0.1 mw is available when the mean output voltage is around 10 V, which is approximately the half of the open circuit voltage V oc (mean) of 20.3 V. This result proves the existence of the maximum output power of the piezo in 7 Hz vibration. The input voltage of the buck regulator can be adjusted to around 10 V, when the vibration frequency of piezo is 7 Hz, the corresponding output voltage across the 93 k resistive load is 2.5 V. The corresponding output power of buck converter is mw. With the maximized piezo output power of 0.1 mw, the transfer efficiency of buck regulator is about 67.4%. In the third experiment, the designed feedback control system is used to test the performance of the designed circuit as shown in Figure 11(c). The relationship between the sampled charging current of the supercapacitor and duty cycle is provided. When the vibration level of the piezo is 7 Hz with V oc (rms) of 28.9 V, the measured charging current is very small until the duty cycle is decreased to 25%. The charging current increases significantly when duty cycle is decreased from 10% to 2%. However, duty cycle smaller than 1.4% degrades the charging current of the

9 electric Micro-power Generation 1139 Table 2. Electrical specifications of different supercapacitors. Specifications PC-10 BCAP0025 BCAP0050 BCAP0150 BCAP0310 BCAP350 NESSCAP Capacitance (F) Voltage (V) DC ESR (m) Operation temp ( C) 40 to to to to to to to 60 Power density (W/kg) Energy density (Wh/kg) 6.9 mah Leakage current (ma) Table 3. Design performance benchmark. Specifications Ottoman (2002) Zhou Optimized duty cycle 3.18% or 3.16% 2.17% Maximized charging current (ma) Rectifier voltage (V) Open-circuit voltage (V) PWM frequency (khz) 1 1 Converter efficiency 65% 67.4% Setup time (s) supercapacitor. The maximum charging current of ma is measured when the duty cycle is optimized to 2.17%. As shown in Figure 11(b), the measured maximum output power of piezo is about 100 mw. Then, the estimated I p is about 4.89 ma. Using Equation (15) with! of 7 Hz and C p of 0.2 mf, the estimated V o will be about 6 mv. At this point, if the piezo is just connected with a 93 k resistive load, the output voltage can stabilize at 2.5 V, which means the output power of piezo is about 67.2 mw. With the same input impedance in Figure 11(a), the I p will be about 70.7 ma. Using Equation (16), the estimated i c is ma, which is close to measured ma. With different supercapacitors, the maximized charging current is increased when the ESR of supercapacitor is decreased, which is shown in Figure 11(c). However, there is also tradeoff of energy density in choosing proper supercapacitor. A variety of supercapacitors with different specifications are shown in Table 2 (Maxwell, 2009). As shown in the Table 3, the performance of the circuit design is compared with similar design in previous researches. The Ottoman s research used similar piezo in size of inch with vibration frequency of 53.8 Hz. Although the rectifier voltage and the efficiency of converter approximate to previous researches, the charging current of the supercapacitor is improved four times, because the supercapacitor can quickly soak up the power generated from piezo. In addition, only 69.4% of previous setting time is needed to scan the full scale of duty cycle. As shown in Table 4, only about 1 2% FPGA resource is used to adaptively optimize the duty cycle. According to the Table 4. Device resource utilization of Spartan-3E FPGA. Specifications Used Available Utilization No. of flip-flops % No. of occupied slices % No. of 4 input LUTs % No. of bonded IOBs % No. of RAMB16s % No. of BUFGMUXs % Table 5. Specifications of ASIC design. Specifications AMIS IBM 7HP TSMC TSMC Technology 0.5 mm 180 nm 130 nm 90 nm Cells Core area (mm 2 ) 2,690,703 38,204 57,585 28,362 Leakage power (nw) ,173 Dynamic power (nw) 165,216,621 5,615,867 1,828, ,870 Total power (nw) 165,217,434 5,615,867 1,828, ,044 Xilinx power analyzer, the total quiescent and dynamic power consumption of FPGA are about 81 and 3 mw, respectively. Based on the ultra high frequency RFID research (Karthaus and Fischer, 2003), the DC power of 16.7 mw extracted from RF signal is necessary to power tag internal logic. With the energy of 67.2 mw harvested from piezo, the front stage voltage multiplier of the tag can be eliminated. In addition, the reading distance of the active tag powered by a piezo can be further extended. In order to prove the feasibility of designing a standalone energy harvesting system, the digital design in FPGA is synthesized using different process technologies. The specifications of ASIC design with different process technologies are shown in Table 5. Both core area and power consumption are decreased with smaller process node. The power consumption of about 0.86 mw in 90 nm process is close to the harvested power of 0.1 mw. CONCLUSION Due to the high power density of the supercapacitor, the output voltage is almost constant. Therefore, the

10 1140 Z. ZHAO ET AL. charging current of a supercapacitor is critical in evaluating the efficiency of energy storage in the supercapacitor. With the designed feedback control system, the charging current of the supercapacitor can be maximized by computing the optimized duty cycle of the buck regulator. The maximum charging current of ma is obtained when the duty cycle is optimized to 2.17%. Future researches will focus on affect of vibrations on circuit performance and designing ultra-low power integrated circuits to make energy harvesting system stand-alone. ACKNOWLEDGMENT This research was supported by the 3M Non-Tenured Faculty Award and NSF EPSCoR. REFERENCES Cerovsky, Z. and Mindl, P Regenerative Braking by Electric Hybrid Vehicles Using Supercapacitor and Power Splitting Generator, In: Proceedings of European Conference on Power Electronics and Applications, Dresden, Germany. Gualous, H., Louahlia-Gualous, H., Gallay, R. and Miraoui, A Supercapacitor Thermal Characterization in Transient State, In: Proceedings of 42nd IAS Annual Meeting on Industry Applications, New Orleans, LA, USA, pp Hofmann, H.F., Ottman, G.K. and Lesieutre, G.A Optimized Pieoelectric Energy Harvesting Circuit Using Step-down Converter in Discontinuous Conduction Mode, IEEE Trans. Power Electron., 18: Karthaus, U. and Fischer, M Full Integrated Passive UHF RFID Transponder IC with 16.7-W Minimum RF Input Power, IEEE J. Solid-State Circuits, 38: Kasyap, A., Johnson, D., Horowitz, S., Nishida, T., Ngo, K., Sheplak, M. and Cattafesta, L Energy Reclamation from a Vibrating electric Composite Beam, In: Proceedings of 9th International Congress on Sound and Vibration, Orlando, USA, Vol Le, T.T., Han, J., Jouanne, A.V., Mayaram, K. and Fiez, T.S electric Micro-power Generation Interface Circuits, IEEE J. Solid-State Circuits, 41: Maxwell Charging of Ultracapacitors, Datasheet, Maxwell Technologies, Inc., San Diego, CA. Maxwell BOOSTCAP Õ Ultracapacitors Information Sheet, Available at: (accessed date January, 2009). Ottman, G.K., Hofmann, H.F., Bhatt, A.C. and Lesieutre, G.A Adaptive electric Energy Harvesting Circuit for Wireless Remote Power Supply, IEEE Trans. Power Electron., 17: Ramadass, Y.K. and Chandrakasan, A.P An Efficient electric Energy-harvesting Interface Circuit Using a Biasflip Rectifier and Shared Inductor, In: IEEE International Solid-State Circuits Conference, San Francisco, USA, pp Rashid, M.H Power Electronics: Circuits, Devices and Applications, 3rd edn, Prentice Hall, Englewood Cliffs, NJ. Simjee, F.I. and Chou, P.H Everlast: Long-life Supercapacitoroperated Wireless Sensor Node, In: Proceedings of International Symposium on Low Power Electronics and Design, Tegernsee, Bavaria, Germany. Simjee, F.I. and Chou, P.H Efficient Charging of Supercapacitors for Extended Lifetime of Wireless Sensor Nodes, IEEE Trans. Power Electron., 23: Sodano, H.A., Inman, D.J. and Park, G A Review of Power Harvesting from Vibration Using electric Materials, The Shock and Vibration Digest, 36: Sodano, H.A., Park, G., Leo, D.J. and Inman, D.J. 2003a. Use of electric Energy Harvesting Devices for Charging Batteries, In: Proceedings of SPIE 10th Annual International Symposium on Smart Structures and Materials, San Diego, CA, USA, Vol Sodano, H.A., Park, G., Leo, D.J. and Inman, D.J. 2003b. Model of electric Power Harvesting Beam, In: Proceeding of ASME International Mechanical Engineering Congress and Exposition, Washington, D.C., USA, Vol. 40. Tan, Y.K., Lee, J.Y. and Panda, S.K Maximize electric Energy Harvesting Using Synchronous Charge Extraction Technique for Powering Autonomous Wireless Transmitter, In: IEEE International Conference Sustainable Energy Technologies, Singapore, pp Umeda, M., Nakamura, K. and Ueha, S Energy Storage Characteristics of a -generator Using Impact Induced Vibration, Jap. J. Appl. Phys., 36: