Earliest Due Date (EDD) [Ferrari] Delay EDD. Jitter EDD

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1 Earliest Due Date (EDD) [Ferrari] Based on EDF Delay-EDD vs. jitter-edd Works for periodic message models (single packet in period): (pi,, Di) Partition end-to-end deadline D i into local deadlines D i,k during connection establishment procedure. -Phase establishment procedure: Phase : tentative establishment Sender OK? Receiver Phase : relaxation Sender Fine! Receiver Delay EDD Upon arrival of Packet j of connection i: determine effective arrival time: a e i,j = max(a e i,j- + p i, a i,j ) stamp packet with local deadline: d i,j = a e i,j + D i,k process packets in EDF order. Delay EDD is greedy. Problem with EDD: jitter max end-to-end delay over k switches:! k min end-to-end delay over k switches: k D i, k Jitter EDD Problem with Delay-EDD: does not control jitter. This has effect on buffer requirements. Jitter-EDD is non-greedy. Jitter-EDD maintains Ahead Time ah i,j, which is the difference between local relative deadline D i,k- and actual delay at switch k-. Ahead time is stored in packet header (alternatively, we use global time synchronization) Upon receiving the j-th packet of connection i with ah i,j at time a i,j : Calculate ready time at switch k: a e i,j =max(ae i,j- + p i, a i,j ) r i,j = max(a e i,j, a i,j + ah i,j ) Stamp packet with deadline d i,j =r i,j +D i,k and process according to EDF starting from ready time r i,j. Result: regenerate traffic at each switch.

2 Delay-/Jitter-Control r i,j = a e i,j r i,j = a i,j + ah i,j at the first switch at each of the downstream switches 5 S a e ae ae ae a e 5 5 S a e ae ae ae a e 5 5 S a e ae ae ae a e 5 Ready Times at S Weighted Round Robin (WRR) w i Each connection i is assigned a weight w i, i.e., it is allocated w i slots during each round. Slot: time to transmit maximum-sized packet. Traffic model: constant bit rate periodic model M i = (p i, e i, D i ) Realizations: greedy WRR Stop-and-Go (SG) Hierarchical Round Robin (HRR) Greedy WRR Each connection i is guaranteed w i slots in each rounds. Round length : upper bound on sum of weights (design parameter) " wi! Constraints: Delays:.. < p min & e! " # $ i wi ' % pi at first switch: $ e " i # wi! downstream: once packet passes first switch, it is immediately eligible on switches downstream -> has to wait at most => end-to-end delay through N switches: Wi $ (! ei wi " + N # ) $ pi + ( N # )

3 Problems with Greedy WRR Greedy WRR does not control jitter: min end-to-end delay: e i +(N-) max end-to-end delay: p i +(N-) jitter: p i -e i +(N-)(-) Buffer needed at k-th switch for connection i: ( +!( k # )( # ) / p i ") ei Need traffic shaping at each switch. Stop & Go Frame-based: divide time in of length. Packet arriving during frame at input link is eligible for transmission during next frame on output link. input output input Stop-and-Go is not work-conserving. Packet arriving during j-th frame, departs during (j+)st frame in switch, (j+)nd frame in switch, etc.: end-to-end delay: p i +N* Buffer space: per connection: *w i Assumption: clocks () of switches are synchronized (otherwise delay can be p i +(N-)*) Stop & Go Implementation Implementation : FIFO scheduler with double-queue structure Implementation :

4 Hierarchical Round Robin End-to-end delay and jitter of S&G depends on only. How about having multiple S&G servers, with different s, and multiplex them on the same outgoing link? Server X w i x sw x Server S Server X is seen as periodic stream of requests by Server S, with e x = sw x, p x = x, D x = x schedule using rate-monotonic scheduler check whether task set {(sw x, x, x )} is schedulable. Admission control: Bandwidth test: check sum of required w i s <= sw x Delay test: end-to-end delay: p i + N* x Jitter test: * x, with buffer requirement *w i Hierarchical Round Robin In HRR, there are number of levels, each with a fixed number of slots serviced in a round-robin fashion A channel/stream is allocated a given number of service slots at a selected level The scheduler cycles through the slots at each level The time taken to service all the slots at a given level is called the frame time at that level The total link bandwidth is partitioned in among these levels The key to HRR lies in its ability to give each level a constant share of the link s bandwidth. The frame time for level, which is the smallest of all the levels, is the basic cycle time If there are n slots in a level frame, then b slots are allocated to higher levels, and the remaining (n b ) slots are used for the level connections The frame time for level- = FT = n The frame time for level- = FT = (n / b ) * n Bandwidth allocated for a level i = (n i b i ) / FT i HRR Design for a MB Link Level i n i b i FT i Slot b/w n Mbps Level b L slot 6 50 Kbps 0 5 Kbps Level b L slot Level

5 Connection Allocation Example Channel Bandwidth need Level Assigned # of slots n C C Mbps Mbps Level b c c c L C C 50 Kbps 500 Kbps Level b c c c L C5 C6 5 Kbps 00 Kbps c5 c6 Level c c c c c c c c c c c c c c c c5 HRR Schedule up to 6 slots 5