vci_anoc_network Specifications & implementation for the SoClib platform

Transcription

1 Laboratoire d électronique de technologie de l information DC roject oclib vci_anoc_network pecifications & implementation for the oclib platform ditor :. MR ANAD Version. : // articipants aux travaux :. Miro anades. Vivet /

2 vci_anoc_network pecifications & realization for the oclib platform able of contents vci_anoc_network overview.... ANC Network on Chip.... vci_anoc_network specifications.... vci_anoc_wrapper.... ANC routing and traffic strategy.... Limitations... Demonstrator platform... V. : // : nitial version Modifications history oclib //. Miro. / anades Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page

3 vci_anoc_network pecifications & realization for the oclib platform vci_anoc_network overview he vci_anoc_network is an interconnect module implementing the ANC Networkon-Chip which is compatible with interfaces.. ANC Network on Chip ANC stands for Asynchronous Network-on-Chip (NoC) and has been developed by the CA-Leti. ANC is a wormhole packet switching NoC. ts architecture is composed by five ports routers interconnected by bidirectional links using send/accept asynchronous handshake protocol. hus, the ANC protocol offers naturally a GAL architecture. As the ANC routers are asynchronous, the entire end-to-end path traveling the packets is completely asynchronous. he ANC topology is not reduced to regular D mesh. rregular D mesh or D torus topology can also be implemented as ANC uses a source routing algorithm. Moreover, source routing can be used to minimize the congestion on some links, and thus reduce the packet latency. A flit is the smallest flow control unit of the network. ach flit contains two control bits, egin of acket () and nd of acket (). is set on the head flit, and is set on the tail flit. Furthermore, the first flit of the packet contains the routing information and the router uses this path-to-target to decide the correct routing destination. he routing information is enclosed on -bits and two bits encodes each routing hop, which allows addressing a path of at most router hops. ANC provides two virtual channels per NoC link. A low latency channel VC is provided for real-time applications and a higher latency and lower priority channel VC for best effort traffic.. vci_anoc_network specifications he vci_anoc_network is a configurable interconnect implementing the ANC network. n order to simplify the implementation of the ANC Network, the vci_anoc_network module implements a regular D mesh topology of ANC routers as shown in next figure. n this example, a x network is depicted. he big round represents the ANC routers. ach ANC router has attached a vci_anoc_wrapper () module which converts the ANC protocol into the protocol and vice versa. [,] [,] [,] [i,j] ANC router vci_anoc_wrapper stopper [,] [,] [,] oclib //. Miro. / anades Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page

4 vci_anoc_network pecifications & realization for the oclib platform he D mesh topology can have any width (W) and height (H) he input and output ports of the vci_anoc_network module are: W*H target ports W*H initiator ports A clock signal A reset port he configuration parameters allow to define the network width and height independently. All the ANC routers and the ports will be automatically allocated to satisfy the topology. he ANC router placed on the sides of the network do not have all their links connected with other ANC routers. hus, these links are connected to topper modules to detect error situations. f a topper module receives a packet, it will print a warning message. he local port of the ANC routers are connected to vci_anoc_wrapper modules which translate the packets into ANC transactions and vice versa. he vci_anoc_network is intended to be used as a second order interconnect network in a hierarchic manner. t is strongly recommended to interconnect the initiator and target s of the same cluster through a local interconnect. therwise, the communication between initiator and target of the same cluster will be penalized by the local port of the network. K Not recommended [i,j] [i,j]. vci_anoc_wrapper he vci_anoc_wrapper is a wrapper module that translate the protocol into ANC transactions. n the side, it has two ports, one initiator and one target port. he vci_anoc_wrapper do not implement a bypass through the initiator and the target ports. Any request/response is directly send to the ANC. herefore, the vci_anoc_network should be used as a second order interconnect. oclib //. Miro. / anades Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page

5 vci_anoc_network pecifications & realization for the oclib platform oclib //. Miro anades. / Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page he request/response commands are converted into ANC packets of bits per flit. his conversion is represented in the next table. he yellow areas are reserved areas. he first flit contains the ANC routing path while the second flit contains the address. he third flits encodes all the information of the request command. A read request command requires only these three flits while a write request command requires additional data flits. he forth and following flits contains the data to write and its associated byte enable signals. request command encoded into a ANC packet: ANC routing path address srcid c m d c o n t c o n s plen trid pktid wdata N- wdata N- he response packet is similar as the request packet. he first flit contains the ANC routing path while the second contains the response information. he response packet to a write request contains just two flits, while the response to a read request contains the additional flits. he third and following flits are the read data of the read request command. response command encoded into a ANC packet ANC routing path rsrcid rerror rtrid rsrcid rdata rdata N-

6 vci_anoc_network pecifications & realization for the oclib platform. ANC routing and traffic strategy ANC router can be used to implement non regular D mesh topologies. However, in this implementation, all the topologies are regular D. he ANC router allow to use any of its ports as the local port (where a vci_anoc_wrapper could be connected). n this implementation, only one port, the local router port, is used to connect the vci_anoc_wrappers. he ANC router uses a source routing algorithm to route the packets over the network. n order to simplify the implementation while being deadlock free, the X-First routing algorithm is used. n each vci_anoc_wrapper, the mapping table is used to determine the Destination cluster of a request/response command. he source routing path-to-target is computed with the X-First algorithm using two information: i) the rigin information provided by the [i,j] coordinates of vci_anoc_wrapper in the ANC D topology and ii) the Destination information of the addressed cluster provided by the mapping table. n a memory mapped system, request and response packets must be fully independent to provide a deadlock free NoC traffic. n order to reduce the complexity of having two real networks, we use the virtual channel policy of the ANC router to split these two traffics. he request packets travels through the virtual channel VC while the response packets use the virtual channel VC.. Limitations he number of allowed hops in the network is limited to. hus, the width and height of the network are conditioned to this limitation. he next equation have to be respected: width_network+ height_network - <= oclib //. Miro. / anades Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page

7 vci_anoc_network pecifications & realization for the oclib platform Demonstrator platform he basic multi_timer-mips platform has been implemented using the vci_anoc_network interconnect. his demonstrator platform can be fond: soclib/platform/topcells/caba-anoc-multi_timer-mips he vci_anoc_network module is located: soclib/module/network_component/vci_anoc_network his platform has been designed based on the DNLU implementation of the multi_timer-mips platform. he initial vci_dspinplus_network has been replaced by the vci_anoc_network. RAM CU Y CU [,] [,] timer CU lock CU [,] [,] oclib //. Miro. / anades Nom hème Réf rojet Réf donnée. Chrono secrétariat Date Auteur artenaire Version n page