Interconnection Networks

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Interconnection Networks"

Transcription

1 CMPT765/ Interconnection Networks Qianping Gu 1 Interconnection Networks The note is mainly based on Chapters 1, 2, and 4 of Interconnection Networks, An Engineering Approach by J. Duato, S. Yalamanchili, and L. Ni and Section of Multiwavelength Optical Networks, A Layered Approach, by T.E. Stern and K. Bala. Interconnection for digital systems Interconnection networks provide the interconnection for digital systems. Examples of interconnection networks include the internal buses in VLSI circuits, telephone switches and networks, networks for parallel/distributed computing systems (including vector supercomputers, multicomputers, multiprocessors, cluster/network of workstations), LAN, MAN, WAN, and networks for industrial applications and electronic devices. Parallel computing and networks Parallel computing systems have been developed to meet the increasing demands on computing powers. A bottleneck in parallel computing systems is the the communication between processors. Therefore, the performance of interconnection networks is a critical issue in parallel computing. This has been a major driving force for the research of interconnection networks. The study of interconnection networks in parallel computing system includes the performance and cost issues. Parallel computer architecture Distributed memory multiprocessors (multicomputers) A multicomputer consists of a set of processors, each processor has its own memory, interconnected by a network. Communications between processors are realized by message passing on the interconnection network. It is easy to make a multicomputer with a large number of processors (and thus a large computing power in theory) but it is difficult to make programs on multicomputers because data and tasks need to be distributed to processors in an efficient way. Shared memory mutliprocessors In this model, all processors in a system share a common memory space. The communication between processors are realized by read/write the shared memory cells through interconnection networks. This simplifies the data exchange between processors. When the system is small, the access time to the memory of every processor can be considered uniform. However, this is not true if the system is large. Distributed shared-memory multiprocessors This model combined the previous two models, each processor has a local cache memory, and all processors share a common main memory. Multicomputers, shared memory multiprocessors, and distributed shared-memory multiprocessors are known as fine grained parallel computing systems, because the computation and communication between processors can be performed in a highly synchronized way.

2 CMPT765/ Interconnection Networks Qianping Gu 2 Network of workstations This model refers to a set of workstations/pcs connected by a network such as a LAN. The model can be further classified into two categories: NOW (network of workstations) and COW (cluster of workstations). NOW is a system dedicated to the parallel computing. Usually, the performance issue of the network in NOW is considered when the system is built. COW refers to a set of workstations/pcs connected by a network that the system may work for other purposes but its extra computing power is used for parallel computing. This model is known as coarse grained parallel computing systems. The computation on this model can be bulk synchronized. Classification of Interconnection Networks Interconnection networks provide the interconnection among end systems and can be classified into shared-medium networks, direct networks, indirect networks, and hybrid networks. Shared-medium networks In shared-medium networks, processors are connected by a common transmission medium such as a bus. All processors share the medium which does not generate message. To send a message to a destination, a source broadcasts the message on the medium and the destination picks up the message. Because processors may send messages to the medium simultaneously, the resolution of network access conflicts is needed. The nature of the shared medium also limits the bandwidth of the network and the number of end systems in the network. Examples of the shared medium networks include the Ethernet. The protocol of for the medium access control used in the Ethernet is known as CSMA/CD (carrier sense multiple access with collision detection). Point-to-point networks In point-to-point networks, end systems are connected by point-to-point communication links. The networks can be further classified into two categories: direct networks and indirect networks. In direct networks, point-to-point links directly connect each end system to some other end systems. In indirect networks, end systems are connected via one or more switches, switches are connected via point-to-point links. Hybrid networks Some networks may have more complicated structures such as hierarchical structures or hypergraph topologies. Such networks are classified as hybrid networks. Direct Networks A direct network consists of a set of nodes and a set of point-to-point links. Each node is directly connected to a small subset of nodes by links. Each node performs both routing and computing. A direct network is usually modeled as a graph, with vertices and edges

3 CMPT765/ Interconnection Networks Qianping Gu 3 of the graph for the nodes and links in the network, respectively. A direct network is characterized by its topology and the routing/switching technologies used in the network. Important topology properties of the network include node degree (the number of links connected to the node), diameter (the maximum distance between two nodes in the network), regularity (a network is regular when all nodes have the same degree), symmetry (a network is symmetric when it looks alike from every node), and orthogonal property (a network is orthogonal if its nodes and links can be arranged in n dimensions such that each link is placed in exactly one dimension). In direct networks, the paths for message transmission are selected by routing algorithms. The switching mechanisms determine how inputs are connected to outputs in a node. All the switching techniques can be used in direct networks. Popular topologies for direct networks r-dimensional mesh The r-dimensional mesh consists of N = k 1 k 2... k r nodes, k i nodes along dimension i, k i 2. Each node is identified by a label (a 1,..., a r ), 0 a i k i 1 and 1 i r. Two nodes u = (a 1,..., a r ) and v = (b 1,..., b r ) are connected by a link iff there is exactly one j such that a j = b j ± 1 and a i = b i for all i j. The most important mesh networks in practice are the 2-D mesh (r = 2, k 0 = k 1 = n, N = n 2 ) and the 3-D mesh (r = 3, k 0 = k 1 = k 2 = n, N = n 3 ). r-dimensional torus Similar to the r-dimensional mesh, the r-dimensional torus consists of N = k 1 k 2... k r nodes, k i nodes along dimension i, k i 2. Each node is identified by a label (a 1,..., a r ), 0 a i k i 1 and 1 i r. Two nodes u = (a 1,..., a r ) and v = (b 1,..., b r ) are connected by a link iff there is exactly one j such that a j = b j ± 1 mod k j and a i = b i for all i j. The torus can be considered as the mesh with wrap around connections. When k 1 = k 2 =... = k r = k, the r-dimensional torus is called the k-ary r-cube. When r = 1, the network is the ring. The 2-D torus (r = 2, k 0 = k 1 = n, N = n 2 ) and the 3-D torus (r = 3, k 0 = k 1 = k 2 = n, N = n 3 ) are important networks. Hypercube The n-dimensional hypercube (n-cube) consists of 2 n nodes. Each node is identified by (a 1,..., a n ), a i {0, 1}, 1 i n. There is a link between u = (a 1,..., a n ) and v = (b 1,..., b n ) iff u and v differ in exactly one bit position. The n-cube has degree n and diameter n. Tree The k-ary tree is a tree in which every node except leaves has exactly k children. When k = 2, the k-ary tree is known as the binary tree. Cube-connected cycles The cube-connected cycle network can be considered as an n-dimensional hypercube of virtual nodes, each virtual node is a ring of n nodes (n2 n nodes in total). The cubeconnected cycle have node-degree 3 and diameter O(n).

4 CMPT765/ Interconnection Networks Qianping Gu 4 Shuffle-Net The (δ, k)-shufflenet is a regular digraph of in-/out-degree δ, N = kδ k nodes, and kδ k+1 arcs. The nodes are arranged in k columns, each column has δ k nodes. The nodes in each column are connected to the next column via δ k+1 arcs in a generalization of the perfect shuffle pattern. The (δ, k)-shufflenet has diameter d = 2k 1 and N = d+1 2 δ(d+1)/2 nodes. debruijn digraphs The debruijn digraph B(δ, d) has in-/out-degree δ, diameter d, and N = δ d nodes. Each node has a label (a 1,..., a d ), a i {0, 1,..., δ 1}. There are arcs from node v = (a 1, a 2,..., a d ) to nodes with labels (a 2,..., a d, α), α {0, 1,..., δ 1}. Star graph The n-dimensional star graph has n! nodes, each node is identified by a permutation of (1, 2,..., n). Nodes u and v are connected iff v can be obtained by exchanging the 1st symbol with the ith symbol, 2 i n, in the permutation of u. The n-dimensional star graph has node-degree n 1 and diameter 3(n 1)/2. Indirect Networks Nodes are connected by network of switches which can be set dynamically in different topologies. Only nodes can be end systems (sources and destinations). A network can be modeled by a graph, with vertices for switches and edges for links. End systems are not shown usually. The source systems are connected to the inputs and the destination systems are connected to the outputs of the network. Typical indirect networks include the crossbar network and the multistage interconnection networks (MIN). Main factors for the networks include the topology, routing, and switching. Cross bar network An r n crossbar network consists of r input lines, n output lines, and rn cross-points located at the intersections of the lines. At each cross point, the input line and output line are connected by a binary switch which has two states, connected and disconnected. Any set of point-to-point connections (permutations) can be realized on an n n crossbar by closing one cross point in each row and each column. A problem with a crossbar switch is the large number of crosspoints in the switch. Multistage interconnection networks (MIN) In MIN, the inputs are connected to the outputs through a number of switch stages. Key factors for the MIN include the number of stages and the connection pattern between stages. Three stage Clos networks For a network with n inputs and n outputs, there are k p m cross bar networks in the 1st stage, m k k cross bar networks in the 2nd stage, and k m p cross bar networks in the 3rd stage, where n = kp.

5 CMPT765/ Interconnection Networks Qianping Gu 5 Generalized Clos networks For n a power of 2, taking p = m = 2, there are n/2 2 2 switches in each of the 1st and 3rd stages, and 2 n/2 n/2 networks in the 2nd stage. Recursively realizing the networks in the 2nd stage, we get a 2 log 2 n 1 stages network (Beneš network, has O(n log 2 n) 2 2 switches). A network with S connection states requires at least log 2 S binary switching elements. For n n network for realizing any permutations, there are S = n! connection states and needs at least n log n 1.44n binary switches. Generalized MIN model Assume that each stage has the same number of inputs and outputs. patterns between stages can be defined by permutations. The connection Basic Permutations Assumptions: Each stage has k n 1 k k switches. k n inputs/outputs are identified by x n 1...x 0, 0 x i k 1 for 0 i n 1. Perfect k-shuffle σ k (x n 1...x 0 ) = x n 2...x 1 x 0 x n 1. σ 2 perfectly shuffles N cards. Inverse perfect shuffle connection σ k 1 (x n 1...x 0 ) = x 0 x n 1...x 1. Digit reversal connection ρ k (x n 1...x 0 ) = x 0 x 1...x n 1 The ith k-ary butterfly permutation, 0 i n 1, β k i (x n 1...x i+1 x i x i 1...x 1 x 0 ) = x n 1...x i+1 x 0 x i 1...x 1 x i The ith cube connection E i, 0 i n 1, k = 2 E i (x n 1...x i+1 x i x i 1...x 0 ) = x n 1...x i+1 x i x i 1...x 0. The ith k-ary baseline permutation, 0 i n 1, δ k i (x n 1...x i+1 x i x i 1...x 1 x 0 ) = x n 1...x i+1 x 0 x i x i 1...x 1. Classification of MINs Blocking network: A path from a free input to a free output is not always possible because of the conflicts with existing connection paths. Nonblocking network: A path from a free input to a free output is always possible without affecting the existing connection path. Rearrangeable networks: A path from a free input to a free output is always possible with possible rearrangements of the paths for existing connections. Unidirectional MINs: Links and switches are unidirectional. Bidirectional MINs: Links and switches are bidirectional.

6 CMPT765/ Interconnection Networks Qianping Gu 6 Unidirectional MINs An MIN of N inputs/outputs and k k switches needs at least log k N stages to allow a connection between any input/output pair. For the MINs of n stages, we number the stages 0, 1,..., n 1 from left (input) to right (output). Let C i (1 i n 1) denote the connection pattern between (i 1)st stage and ith stage, C 0 be the connection pattern between the sources and inputs of stage 0, and C n be the connection pattern between outputs of stage n 1 and the destinations. Baseline network: C 0, σ k ; C i (1 i n), δ k n i. Butterfly network: C 0, β k 0 ; C i (1 i n 1), β k n i; C n, β k 0. Cube MINs: C 0, σ k ; C i (1 i n), β k n i. Omega network: C i (0 i n 1), σ k ; C n, β k 0. Bidirectional MINs (BMINs) The BMIN consists of bidirectional switches/links. Bidirectional switches support three types of connections: forward, backward, and turnaround. End systems are connected to one side (e.g., left) of the network. Routing paths are established by crossing stages in forward direction, a turnaround connection, and in backward direction. Butterfly BMINs: Can be viewed as a folded Beneš network Inverse butterfly BMINs: Can be viewed as fat-tree (used in CM-5) Hybrid Networks Hierarchical Networks: Example, hierarchical buses. Cluster based network. Hypergraph topology. Blocking properties of indirect networks Accessibility: A network is fully accessible, if there is a path from any input to any output in the network. Non-blocking property: A set of one-to-one connection requests on an N N network can be defined by a permutation. A network is non-blocking, if any permutation can be realized by edge-disjoint paths in the network. Non-blocking properties can be further classified into rearrangeable non-blocking, wide-sense non-blocking, and strict-sense nonblocking, depending on if the permutation is realized statically or dynamically. Rearrangeable non-blocking A network is rearrangeable non-blocking if any permutation can be realized by edgedisjoint paths when the entire permutation is known. In other words, any permutation can be statically realized. The word rearrangeable refers to that if the connection

7 CMPT765/ Interconnection Networks Qianping Gu 7 requests in a permutation arrive dynamically, the permutation can be realized with possible rearranging active connections. This is equivalent to realize a permutation statically. Wide-sense nonblocking When connection requests in a permutation arrive dynamically in sequence, the permutation can be realized by edge-disjoint paths without rearranging active connections subject to the condition that a selected path is used for each new connection request. In other words, any permutation can be dynamically realized with the help of a wise algorithm. Strict-sense nonblocking When connection requests in a permutation arrive dynamically in sequence, the permutation can be realized by edge-disjoint paths without rearranging active connections, any idle path can be used for each new connection request. In other words, any permutation can be dynamically realized. Obviously, the strict-sense non-blocking implies the wise-sense non-blocking which implies the rearrangeable non-blocking. Networks by 2 2 Switches A 2 2 switch has two input links and two output links and has a through state and a cross state for one-to-one connection from inputs to outputs. An r n cross bar network can be constructed by r n switches at the r n cross points of r input lines and n output lines. An n n crossbar network is strict-sense nonblocking MINs: An n-dimensional MIN has N = 2 n inputs/outputs and multiple stages of switches, with N/2 switches in each stage. A k-stage network has k N/2 switches. A necessary condition for the full accessibility is that the network has at least n stages. Sufficient conditions for the full accessibility depend on connection patterns between stages. A k-stage MIN has 2 k N/2 distinct states. To realize all permutations on an N N network, at least N! distinct states of the network is needed. A necessary condition on the number of stages for rearrangeable non-blocking networks is k 2 log N O(1). Sufficient conditions on the number of stages for rearrangeable non-blocking networks, depend on connection patterns between stages. The n-dimensional Beneš network has 2 log N 1 stages and is rearrangeable non-blocking. Blocking MINs There is a class of well known n-dimensional full accessible MINs with n stages of 2 2 switches. There is a unique path from any input to any output in a network of this class. Examples of the networks include baseline networks, omega networks, butterfly networks, indirect binary n-cube networks, and the inverse networks of the above. These networks are blocking networks. The networks in the class have similar structures. Especially, many of them are topologically or functionally equivalent.

8 CMPT765/ Interconnection Networks Qianping Gu 8 Routing on n-dimensional MINs Routing on the n-dimensional Omega network Ω n An input u = (u n 1...u 1 u 0 ) and an output v = (v n 1...v 1 v 0 ) can be connected by the unique path Collisions (u n 1 u n 2...u 0 ) (u n 2...u 0 v n 1 ) (u n 3...u 0 v n 1 v n 2 )... (u n i...u 0 v n 1...v n i+1 )... (v n 1...v 0 ). If two paths share an edge then a collision occurs. Paths (u n 1...u 0 ) (v n 1...v 0 ) and (s n 1...s 0 ) (t n 1...t 0 ) are edge-disjoint iff i, 0 i n 1, u n i...u 0 v n 1...v n i+1 s n i...s 0 t n 1...t n i+1 For two paths u v and s t, let α(u, s) be the largest l such that the rightmost (least significant) l bits of u and s are the same, and let β(v, t) be the largest l such that the leftmost (most significant) l bits of v and t are the same. Paths u v and s t are edge-disjoint if α(u, s) + β(v, t) < n. Routing on other networks like butterfly networks is similar. Non-blocking networks N N cross bar network This network is strict-sense non-blocking. A problem with the cross bar network is the large number O(N 2 ) of switches in the network. How to construct a non-blocking network with as few switches as possible has been a major research topic in circuit-switched networks. The number of switches can be reduced by increasing the number of stages in the network. Clos network Three stage N N Clos network (N = k p), k p m cross bar networks in the 1st stage m k k cross bar networks in the 2nd stage k m p cross bar networks in the 3rd stage The outputs of one stage are connected to the inputs of the next stage by a shuffle pattern. More precisely, let the k networks in the 1st stage be identified by an integer x 0 {0, 1,.., k 1} and let the m outputs of each switch be identified by an integer x 1 {0, 1,.., m 1}. Let the m networks in the 2nd stage be identified by integer

9 CMPT765/ Interconnection Networks Qianping Gu 9 x 1 {0, 1,.., m 1} and let the k outputs of each switch be identified by integer x 0 {0, 1,.., k 1}. Then output (x 1 x 0 ) of the 1st stage is connected to input (x 0 x 1 ) of the 2nd stage. Similarly, output (x 0 x 1 ) of the 2nd stage is connected to input (x 1 x 0 ) of the 3rd stage. A necessary and sufficient condition to make the three stage Clos network strict-sense non-blocking is m = 2p 1. An outline for proving this is given below. For any idle input/output pair (u, v), where u is an input of network x 0 in the 1st stage and v is an output of network x 0 in the 3rd stage, at most m 1 networks of the 2nd stage have been used for the connections from the inputs other than u of network x 0, and at most m 1 networks of the 2nd stage have been used for the connections to the outputs other than v of network x 0. Since there are 2m 1 networks at the 2nd stage, there is at least one network which is not used by any of the previous connections from network x 0 or to network of x 0. Therefore, (u, v) can be connected via that network of the 2nd stage. For N = p 2, taking m = 2p 1, a non-blocking Clos-network can be realized by O(N 3/2 ) switches. Reduce switches by increasing stages The number of switches can be further reduced by increasing the number of stages with a recursive construction. Let N = p r+1 (r 1) and m = 2p 1. The construction starts from a 3-stage network k = p r p m cross bars in the 1st stage m p r p r cross bars in the 2nd stage p r m p cross bars in the 3rd stage Recursively realize the middle stage cross-bars until each of the cross-bars in the 2nd stage becomes a p p network. The number of switches in the above construction is O(N 1+1/(r+1) ). Beneš Networks For N = 2 n, taking p = m = 2, N/2 2 2 switches in the 1st stage 2 N/2 N/2 networks in the 2nd stage N/2 2 2 switches in the 3rd stage Recursively realizing the networks in the 2nd stage, we get a 2 log 2 N 1 stages network which is known as the n-dimensional Beneš network and has O(N log 2 N) 2 2 switches. The Beneš network is rearrangeable non-blocking. A strict-sense non-blocking network can be constructed by n = log 2 N copies of the Beneš networks (known as Cantor network) as follows: At the input stage, there are N 1 n switches. In the middle stage, there are n copies of the Beneš networks. At the output stage, there are N n 1 switches.

10 CMPT765/ Interconnection Networks Qianping Gu 10 Network equivalence Topological equivalence: Two networks are topologically equivalent if one can be obtained from the other by relabeling switches and/or inputs/outputs of switches. Functional equivalence: Two networks are functional equivalent if they realize the same set of permutations. Routing on direct networks A direct network consists of a set of nodes, each is connected to some other nodes (neighbors) by point-to-point links. The network is also known as the point-to-point network or message-passing network. The term is usually used for parallel/distributed computing systems. The communication in the network is realized by message passing. Usually a message is partitioned into packets. A packet consists of a header and a data area. A header has routing and sequencing information. Usually each node in the network performs both computing and routing. In most systems, each node has a dedicated router to free the CPU from routing. Each router usually can realize non-blocking routing from its inputs to its outputs. Communication time A common metric for communication time is communication latency which has three parts: Start-up latency It is the time to handle packet at source and destination nodes and depends on the protocols and internal architectures of the nodes. Network latency It is the time between a packet leaving the source and arriving at the destination assuming that there is no contention during the transmission. It depends on the topology of the network, the channel capacity, switching techniques, routing algorithms, and structures of routers. Blocking time It is the time delay caused by contentions. The contention can happen on links and routers. The blocking time depends on dynamic behaviors of the network. Queueing theory is a main methodology for analyzing the average blocking time. Main factors on the communication latency include the topology, routing, flow control, and switching. Topology The topology refers to how nodes are interconnected by communication links (channels). It is ideal that any two nodes is directly connected by a link. The corresponding graphs to such networks are complete. However, due to the hardware constraints and cost, it is not feasible to have large complete networks. Much research work has been done on network topologies. Some basic preferable properties of topologies include small diameter,

11 CMPT765/ Interconnection Networks Qianping Gu 11 small node degree, multiple disjoint paths between nodes, symmetry, and regularity. Some properties contradict with each other, like diameter and node degree. Additional properties related to performances of the network include the following. Orthogonal property, provides the base for dimension based routing which is easy to realize. Bisection width, the minimum number of links to partition the network into two parts. This property is important to the fault tolerance of the network. Channel bandwidth, the data rate of a link. It is the product of channel width and the channel rate, where the channel width is the number of bits can be transmitted in parallel on a link (the number of lines) and the channel rate is the peak transfer rate of bits on a single line. The channel bandwidth determines the performance of the link. Routing Routing is to select a path for delivering messages from source to destination. The following strategies have been used for routing. Source routing The source node determines the routing path which is fixed. The packet must carry the information on the routing path. Distributed routing Each router decides the neighbor node to which it sends the message without the global information of the network. The algorithm used by routers should be fast and easy to implement. Deterministic routing A unique routing path is used for a source and destination pair. The path does not depend on the dynamic states of the network. This is also known as oblivious routing. Adaptive routing The routing path for a source and destination pair may not be unique. The path depends on the dynamic states of the network. Minimal routing The routing path is always a shortest path. We will study routing in more details later. Switching in direct networks Both circuit-switching and packet-switching have been used in direct networks. Circuit switching In circuit-switching networks, a dedicated path is set-up to connect a pair of source and destination. The message is transfered without buffering on the path. The communication

12 CMPT765/ Interconnection Networks Qianping Gu 12 latency consists of the time for path set-up and the delay in transferring the message. In most of the circuit-switching parallel computing systems, the paths are set-up by passing a prob (control) packet from the source to the destination. Let T be the communication latency, L c be the length of the control packet, L be the length of the message, B be the channel bandwidth, and d be the length (the number of channels) in the path. Then T = d L c B + L B. If L c << L then the latency can be considered independent of d. The circuit-switching is not efficient for busty traffics. For short messages if a circuit is released each time, then the time for path set-up is excessive. If a circuit is not released then the channels in the circuit are idle, resulting in low utilization. Another problem is that one busy channel can block a whole circuit. Packet switching In packet-switching networks, the path for transmitting messages from a source to a destination may not be dedicated or unique and messages are transmitted with possible buffering at the intermediate routers on the path from the source to the destination. This overcomes some problems in circuit-switching networks. We discuss a number of variants of circuit-switching techniques. Message-switching In message-switching networks, messages are routed dynamically using routing algorithms. Usually the algorithms are distributed and adaptive ones. Messages are transmitted in a store-and-forward way: messages are stored in buffers at intermediate nodes and the whole message is stored before it is forwarded to the next node. Each message has a header which contains the routing information like the source/destination addresses. A link (channel) can be shared by messages for multiple connections. Let β be the start-up time for transmitting a message at a node. The communication latency for message-switching networks is T = d(β + L B ). For a network with diameter D the worst case lower bound for the latency is D(β + L B ). Problems with the above networks include large buffers required at routers (because a buffer should be able to store messages of different sizes) and latency proportional to the distance from source to destination.

13 CMPT765/ Interconnection Networks Qianping Gu 13 Packet-switching In packet-switching networks, a message is partitioned into packets (usually of fixed size), each packet has a header containing routing information. Each packet is routed in a storeand-forward way independently. This allows two types of parallelism in routing. One is that several links in a same path are simultaneously used for transferring packets (packets pipelined) and the other is that packets can be routed on multiple paths from the source to the destination. Because the packets have the same size, it is easier to control the buffer size at routers. Packet-switching networks have better resource utilization than messageswitching networks but have duplicated headers and more overhead at routers. Let P be the size of the packets. Then the latency for the first packet is d(β + P B ). If packets are pipelined on the links of the path, the communication latency for the message is T = (d + L P 1)(β + P B ). For a network with diameter D and cut-width C (the number of edges that separate the network), the worst case lower bound for the latency is Virtual cut-through max{dβ, L BC }. The virtual cut-through switching can be considered as a mixture of circuit-switching and packet-switching. The idea here is that when the next channel is available at an intermediate router, the router sends the received part of a packet to the channel before the entire packet is stored. A router only buffers an entire packet when the output channel is busy. In the worst case, the latency of the network is similar to that of a packet-switched network. In the best case, the latency is similar to that of a switched network. In the ideal case, the latency is Wormhole routing T = dβ + L B. In wormhole-switching networks, a packet is further partitioned into smaller units (flits). The first flit(s) contains the header and the other flits contain data. The routing decision is based on header flits and data flits follow the route for the header in a pipelined fashion (the router does not buffer data flits). Since data flits do not contain routing information, a contiguous path of channels is needed. When a header is blocked, all flits stop advancing and remain in channels. This is different from the virtual-cut-through switching where the data are moved from channels to buffers of the router. The latency of the network is T = dβ + T B

14 CMPT765/ Interconnection Networks Qianping Gu 14 if there is no contention. The advantages of the networks is small latency (almost independent to d if no contention) and very small buffers (just FIFO flit buffers). Problems include large blocking time if network congested and deadlocks in routing. An example of a deadlock may like this: packet A holds some resources while requesting others held by packet B which is demanding the resources held by A. Resources are buffers in store-and-forward and virtual-cut-through networks and channels in circuit-switching and wormhole networks. Much work has been done on preventing and avoiding deadlocks. The details are omitted here. Virtual channels In the VC switching, a message/packet is transmitted through a virtual path. A virtual path is not a dedicated one for a connection but can be shared by multiple connections. Similar to the circuit-switching, there are three phases in the VC switching, connection establishment, transmission, and connection termination. The advantages of the virtual channel switching include the similar latency to and better resource utilization than those of circuit-switching networks. Disadvantages include the increased scheduling complexity and the physical channel shared by multiple virtual connections can be a bottleneck which increases the latency. Routing Strategies Deterministic routing For orthogonal networks, an efficient approach is dimension-ordered routing. The routing path consists of a sequence of links with a specific dimension order. The intermediate routers can easily compute the next output link from the source and destination addresses in the message. An example of dimension-ordered routing is the E-cube routing on the hypercube network: A packet contains the destination address d {0, 1} n. When the packet arrives at a node with label v {0, 1} n, the node computes d v, where is the bitwise binary sum, and uses the link on the dimension corresponding to the rightmost (least significant) 1 in d v as the output link (if d v = 0, the packet has arrived at the destination d). Another example is mesh-xy -routing. In this approach, a packet is first routed in the X direction to the correct row and then in the Y direction to the correct column. Adaptive routing This routing strategy can choose routing paths based on the conditions of the network. There are a number of approaches. Details are omitted. Table look-up routing This is a distributed routing strategy. Each node keeps a table to indicate which outgoing link to use for a destination. The Internet uses this approach. Key points for this approach include getting information for updating the routing table and reducing the table size.

System Interconnect Architectures. Goals and Analysis. Network Properties and Routing. Terminology - 2. Terminology - 1

System Interconnect Architectures. Goals and Analysis. Network Properties and Routing. Terminology - 2. Terminology - 1 System Interconnect Architectures CSCI 8150 Advanced Computer Architecture Hwang, Chapter 2 Program and Network Properties 2.4 System Interconnect Architectures Direct networks for static connections Indirect

More information

Interconnection Networks. Interconnection Networks. Interconnection networks are used everywhere!

Interconnection Networks. Interconnection Networks. Interconnection networks are used everywhere! Interconnection Networks Interconnection Networks Interconnection networks are used everywhere! Supercomputers connecting the processors Routers connecting the ports can consider a router as a parallel

More information

Interconnection Network

Interconnection Network Interconnection Network Recap: Generic Parallel Architecture A generic modern multiprocessor Network Mem Communication assist (CA) $ P Node: processor(s), memory system, plus communication assist Network

More information

Interconnection Networks Programmierung Paralleler und Verteilter Systeme (PPV)

Interconnection Networks Programmierung Paralleler und Verteilter Systeme (PPV) Interconnection Networks Programmierung Paralleler und Verteilter Systeme (PPV) Sommer 2015 Frank Feinbube, M.Sc., Felix Eberhardt, M.Sc., Prof. Dr. Andreas Polze Interconnection Networks 2 SIMD systems

More information

Lecture 2 Parallel Programming Platforms

Lecture 2 Parallel Programming Platforms Lecture 2 Parallel Programming Platforms Flynn s Taxonomy In 1966, Michael Flynn classified systems according to numbers of instruction streams and the number of data stream. Data stream Single Multiple

More information

Interconnection Network Design

Interconnection Network Design Interconnection Network Design Vida Vukašinović 1 Introduction Parallel computer networks are interesting topic, but they are also difficult to understand in an overall sense. The topological structure

More information

Topological Properties

Topological Properties Advanced Computer Architecture Topological Properties Routing Distance: Number of links on route Node degree: Number of channels per node Network diameter: Longest minimum routing distance between any

More information

Lecture 18: Interconnection Networks. CMU 15-418: Parallel Computer Architecture and Programming (Spring 2012)

Lecture 18: Interconnection Networks. CMU 15-418: Parallel Computer Architecture and Programming (Spring 2012) Lecture 18: Interconnection Networks CMU 15-418: Parallel Computer Architecture and Programming (Spring 2012) Announcements Project deadlines: - Mon, April 2: project proposal: 1-2 page writeup - Fri,

More information

Lecture 23: Interconnection Networks. Topics: communication latency, centralized and decentralized switches (Appendix E)

Lecture 23: Interconnection Networks. Topics: communication latency, centralized and decentralized switches (Appendix E) Lecture 23: Interconnection Networks Topics: communication latency, centralized and decentralized switches (Appendix E) 1 Topologies Internet topologies are not very regular they grew incrementally Supercomputers

More information

Introduction to Parallel Computing. George Karypis Parallel Programming Platforms

Introduction to Parallel Computing. George Karypis Parallel Programming Platforms Introduction to Parallel Computing George Karypis Parallel Programming Platforms Elements of a Parallel Computer Hardware Multiple Processors Multiple Memories Interconnection Network System Software Parallel

More information

Components: Interconnect Page 1 of 18

Components: Interconnect Page 1 of 18 Components: Interconnect Page 1 of 18 PE to PE interconnect: The most expensive supercomputer component Possible implementations: FULL INTERCONNECTION: The ideal Usually not attainable Each PE has a direct

More information

Chapter 2. Multiprocessors Interconnection Networks

Chapter 2. Multiprocessors Interconnection Networks Chapter 2 Multiprocessors Interconnection Networks 2.1 Taxonomy Interconnection Network Static Dynamic 1-D 2-D HC Bus-based Switch-based Single Multiple SS MS Crossbar 2.2 Bus-Based Dynamic Single Bus

More information

Why the Network Matters

Why the Network Matters Week 2, Lecture 2 Copyright 2009 by W. Feng. Based on material from Matthew Sottile. So Far Overview of Multicore Systems Why Memory Matters Memory Architectures Emerging Chip Multiprocessors (CMP) Increasing

More information

Outline. Switching and Routing

Outline. Switching and Routing Outline Basics of switching Blocking Interconnection examples Complexity Recursive constructions Switching and Routing Switching is generally the establishment of connections on a circuit basis Routing

More information

Scalability and Classifications

Scalability and Classifications Scalability and Classifications 1 Types of Parallel Computers MIMD and SIMD classifications shared and distributed memory multicomputers distributed shared memory computers 2 Network Topologies static

More information

Parallel Programming

Parallel Programming Parallel Programming Parallel Architectures Diego Fabregat-Traver and Prof. Paolo Bientinesi HPAC, RWTH Aachen fabregat@aices.rwth-aachen.de WS15/16 Parallel Architectures Acknowledgements Prof. Felix

More information

CS 6290 Many-core & Interconnect. Milos Prvulovic Fall 2007

CS 6290 Many-core & Interconnect. Milos Prvulovic Fall 2007 CS 6290 Many-core & Interconnect Milos Prvulovic Fall 2007 Interconnection Networks Classification: Shared Medium or Switched Shared Media Networks Need arbitration to decide who gets to talk Arbitration

More information

Chapter 4 Multi-Stage Interconnection Networks The general concept of the multi-stage interconnection network, together with its routing properties, have been used in the preceding chapter to describe

More information

Lecture Overview. Multiple Processors. Multiple processors. Continuous need for faster computers

Lecture Overview. Multiple Processors. Multiple processors. Continuous need for faster computers Lecture Overview Multiple processors Multiprocessors UMA versus NUMA Hardware configurations OS configurations Process scheduling Multicomputers Interconnection configurations Network interface User-level

More information

Parallel and Distributed Computing Chapter 5: Basic Communications Operations

Parallel and Distributed Computing Chapter 5: Basic Communications Operations Parallel and Distributed Computing Chapter 5: Basic Communications Operations Jun Zhang Laboratory for High Performance Computing & Computer Simulation Department of Computer Science University of Kentucky

More information

Interconnect. Jesús Labarta. Index

Interconnect. Jesús Labarta. Index Interconnect Jesús Labarta Index 1 Interconnection networks Need to send messages (commands/responses, message passing) Processors Memory Node Node Interconnection networks Components Links Switches Network

More information

COMP 422, Lecture 3: Physical Organization & Communication Costs in Parallel Machines (Sections 2.4 & 2.5 of textbook)

COMP 422, Lecture 3: Physical Organization & Communication Costs in Parallel Machines (Sections 2.4 & 2.5 of textbook) COMP 422, Lecture 3: Physical Organization & Communication Costs in Parallel Machines (Sections 2.4 & 2.5 of textbook) Vivek Sarkar Department of Computer Science Rice University vsarkar@rice.edu COMP

More information

Introduction to Multiprocessors (Part I) Prof. Cristina Silvano Politecnico di Milano

Introduction to Multiprocessors (Part I) Prof. Cristina Silvano Politecnico di Milano Introduction to Multiprocessors (Part I) Prof. Cristina Silvano Politecnico di Milano Outline Key issues to design multiprocessors Interconnection network Centralized shared-memory architectures Distributed

More information

Module 15: Network Structures

Module 15: Network Structures Module 15: Network Structures Background Topology Network Types Communication Communication Protocol Robustness Design Strategies 15.1 A Distributed System 15.2 Motivation Resource sharing sharing and

More information

Operating System Concepts. Operating System 資 訊 工 程 學 系 袁 賢 銘 老 師

Operating System Concepts. Operating System 資 訊 工 程 學 系 袁 賢 銘 老 師 Lecture 7: Distributed Operating Systems A Distributed System 7.2 Resource sharing Motivation sharing and printing files at remote sites processing information in a distributed database using remote specialized

More information

Chapter 14: Distributed Operating Systems

Chapter 14: Distributed Operating Systems Chapter 14: Distributed Operating Systems Chapter 14: Distributed Operating Systems Motivation Types of Distributed Operating Systems Network Structure Network Topology Communication Structure Communication

More information

Interconnection Networks

Interconnection Networks Interconnection Networks Z. Jerry Shi Assistant Professor of Computer Science and Engineering University of Connecticut * Slides adapted from Blumrich&Gschwind/ELE475 03, Peh/ELE475 * Three questions about

More information

Chapter 16: Distributed Operating Systems

Chapter 16: Distributed Operating Systems Module 16: Distributed ib System Structure, Silberschatz, Galvin and Gagne 2009 Chapter 16: Distributed Operating Systems Motivation Types of Network-Based Operating Systems Network Structure Network Topology

More information

Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors

Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors 2011 International Symposium on Computer Networks and Distributed Systems (CNDS), February 23-24, 2011 Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors Atefeh Khosravi,

More information

Introduction to LAN/WAN. Network Layer

Introduction to LAN/WAN. Network Layer Introduction to LAN/WAN Network Layer Topics Introduction (5-5.1) Routing (5.2) (The core) Internetworking (5.5) Congestion Control (5.3) Network Layer Design Isues Store-and-Forward Packet Switching Services

More information

Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng

Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption

More information

Routing in packet-switching networks

Routing in packet-switching networks Routing in packet-switching networks Circuit switching vs. Packet switching Most of WANs based on circuit or packet switching Circuit switching designed for voice Resources dedicated to a particular call

More information

Chapter 12: Multiprocessor Architectures. Lesson 04: Interconnect Networks

Chapter 12: Multiprocessor Architectures. Lesson 04: Interconnect Networks Chapter 12: Multiprocessor Architectures Lesson 04: Interconnect Networks Objective To understand different interconnect networks To learn crossbar switch, hypercube, multistage and combining networks

More information

Computer Network. Interconnected collection of autonomous computers that are able to exchange information

Computer Network. Interconnected collection of autonomous computers that are able to exchange information Introduction Computer Network. Interconnected collection of autonomous computers that are able to exchange information No master/slave relationship between the computers in the network Data Communications.

More information

Chapter 15: Distributed Structures. Topology

Chapter 15: Distributed Structures. Topology 1 1 Chapter 15: Distributed Structures Topology Network Types Operating System Concepts 15.1 Topology Sites in the system can be physically connected in a variety of ways; they are compared with respect

More information

Computer Networks Vs. Distributed Systems

Computer Networks Vs. Distributed Systems Computer Networks Vs. Distributed Systems Computer Networks: A computer network is an interconnected collection of autonomous computers able to exchange information. A computer network usually require

More information

Scaling 10Gb/s Clustering at Wire-Speed

Scaling 10Gb/s Clustering at Wire-Speed Scaling 10Gb/s Clustering at Wire-Speed InfiniBand offers cost-effective wire-speed scaling with deterministic performance Mellanox Technologies Inc. 2900 Stender Way, Santa Clara, CA 95054 Tel: 408-970-3400

More information

Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip

Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip Ms Lavanya Thunuguntla 1, Saritha Sapa 2 1 Associate Professor, Department of ECE, HITAM, Telangana

More information

Scalable Interconnection Networks

Scalable Interconnection Networks Scalable Interconnection Networks 1 Scalable, High Performance Network At Core of Parallel Computer Architecture Requirements and trade-offs at many levels Elegant mathematical structure Deep relationships

More information

Communication Networks. MAP-TELE 2011/12 José Ruela

Communication Networks. MAP-TELE 2011/12 José Ruela Communication Networks MAP-TELE 2011/12 José Ruela Network basic mechanisms Introduction to Communications Networks Communications networks Communications networks are used to transport information (data)

More information

The Butterfly, Cube-Connected-Cycles and Benes Networks

The Butterfly, Cube-Connected-Cycles and Benes Networks The Butterfly, Cube-Connected-Cycles and Benes Networks Michael Lampis mlambis@softlab.ntua.gr NTUA The Butterfly, Cube-Connected-Cycles and Benes Networks p.1/16 Introduction Hypercubes are computationally

More information

Local-Area Network -LAN

Local-Area Network -LAN Computer Networks A group of two or more computer systems linked together. There are many [types] of computer networks: Peer To Peer (workgroups) The computers are connected by a network, however, there

More information

MULTISTAGE INTERCONNECTION NETWORKS: A TRANSITION TO OPTICAL

MULTISTAGE INTERCONNECTION NETWORKS: A TRANSITION TO OPTICAL MULTISTAGE INTERCONNECTION NETWORKS: A TRANSITION TO OPTICAL Sandeep Kumar 1, Arpit Kumar 2 1 Sekhawati Engg. College, Dundlod, Dist. - Jhunjhunu (Raj.), 1987san@gmail.com, 2 KIIT, Gurgaon (HR.), Abstract

More information

Behavior Analysis of Multilayer Multistage Interconnection Network With Extra Stages

Behavior Analysis of Multilayer Multistage Interconnection Network With Extra Stages Behavior Analysis of Multilayer Multistage Interconnection Network With Extra Stages Thesis submitted in partial fulfillment of the requirements for the award of degree of Master of Engineering in Computer

More information

Parallel Architectures Group Grupo de Arquitecturas Paralelas (GAP)

Parallel Architectures Group Grupo de Arquitecturas Paralelas (GAP) Handling in Interconnection Deadlock Networks Parallel Architectures Group Switching Techniques, Adaptive Routing and Jose Duato de Ingeniera de Sistemas, Computadores y Automatica Dept. Politecnica de

More information

Principles and characteristics of distributed systems and environments

Principles and characteristics of distributed systems and environments Principles and characteristics of distributed systems and environments Definition of a distributed system Distributed system is a collection of independent computers that appears to its users as a single

More information

Asynchronous Bypass Channels

Asynchronous Bypass Channels Asynchronous Bypass Channels Improving Performance for Multi-Synchronous NoCs T. Jain, P. Gratz, A. Sprintson, G. Choi, Department of Electrical and Computer Engineering, Texas A&M University, USA Table

More information

ECE 358: Computer Networks. Solutions to Homework #4. Chapter 4 - The Network Layer

ECE 358: Computer Networks. Solutions to Homework #4. Chapter 4 - The Network Layer ECE 358: Computer Networks Solutions to Homework #4 Chapter 4 - The Network Layer P 4. Consider the network below. a. Suppose that this network is a datagram network. Show the forwarding table in router

More information

Wide Area Networks. Learning Objectives. LAN and WAN. School of Business Eastern Illinois University. (Week 11, Thursday 3/22/2007)

Wide Area Networks. Learning Objectives. LAN and WAN. School of Business Eastern Illinois University. (Week 11, Thursday 3/22/2007) School of Business Eastern Illinois University Wide Area Networks (Week 11, Thursday 3/22/2007) Abdou Illia, Spring 2007 Learning Objectives 2 Distinguish between LAN and WAN Distinguish between Circuit

More information

Routing in Switched Networks

Routing in Switched Networks Routing in Switched Networks Chapter 12 CS420/520 Axel Krings Page 1 Routing in Circuit Switched Network Many connections will need paths through more than one switch Need to find a route Efficiency Resilience

More information

EE4367 Telecom. Switching & Transmission. Prof. Murat Torlak

EE4367 Telecom. Switching & Transmission. Prof. Murat Torlak Packet Switching and Computer Networks Switching As computer networks became more pervasive, more and more data and also less voice was transmitted over telephone lines. Circuit Switching The telephone

More information

Data Communications & Computer Networks. Circuit and Packet Switching

Data Communications & Computer Networks. Circuit and Packet Switching Data Communications & Computer Networks Chapter 9 Circuit and Packet Switching Fall 2008 Agenda Preface Circuit Switching Softswitching Packet Switching Home Exercises ACOE312 Circuit and packet switching

More information

Router Architectures

Router Architectures Router Architectures An overview of router architectures. Introduction What is a Packet Switch? Basic Architectural Components Some Example Packet Switches The Evolution of IP Routers 2 1 Router Components

More information

Overview of Network Hardware and Software. CS158a Chris Pollett Jan 29, 2007.

Overview of Network Hardware and Software. CS158a Chris Pollett Jan 29, 2007. Overview of Network Hardware and Software CS158a Chris Pollett Jan 29, 2007. Outline Scales of Networks Protocol Hierarchies Scales of Networks Last day, we talked about broadcast versus point-to-point

More information

UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS

UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS UNIT 2 CLASSIFICATION OF PARALLEL COMPUTERS Structure Page Nos. 2.0 Introduction 27 2.1 Objectives 27 2.2 Types of Classification 28 2.3 Flynn s Classification 28 2.3.1 Instruction Cycle 2.3.2 Instruction

More information

Agenda. Distributed System Structures. Why Distributed Systems? Motivation

Agenda. Distributed System Structures. Why Distributed Systems? Motivation Agenda Distributed System Structures CSCI 444/544 Operating Systems Fall 2008 Motivation Network structure Fundamental network services Sockets and ports Client/server model Remote Procedure Call (RPC)

More information

Introduction to Local Area Networks

Introduction to Local Area Networks For Summer Training on Computer Networking visit Introduction to Local Area Networks Prepared by : Swapan Purkait Director Nettech Private Limited swapan@nettech.in + 91 93315 90003 Introduction A local

More information

Chapter 8 Multiple Processor Systems. 8.1 Multiprocessors 8.2 Multicomputers 8.3 Distributed systems

Chapter 8 Multiple Processor Systems. 8.1 Multiprocessors 8.2 Multicomputers 8.3 Distributed systems Chapter 8 Multiple Processor Systems 8.1 Multiprocessors 8.2 Multicomputers 8.3 Distributed systems Multiprocessor Systems Continuous need for faster computers shared memory model message passing multiprocessor

More information

Multiprocessor Systems. Chapter 8 Multiple Processor Systems. Multiprocessors. Multiprocessor Hardware (1)

Multiprocessor Systems. Chapter 8 Multiple Processor Systems. Multiprocessors. Multiprocessor Hardware (1) Chapter 8 Multiple Processor Systems Multiprocessor Systems 8.1 Multiprocessors 8.2 Multicomputers 8.3 Distributed systems Continuous need for faster computers shared memory model message passing multiprocessor

More information

Load balancing in a heterogeneous computer system by self-organizing Kohonen network

Load balancing in a heterogeneous computer system by self-organizing Kohonen network Bull. Nov. Comp. Center, Comp. Science, 25 (2006), 69 74 c 2006 NCC Publisher Load balancing in a heterogeneous computer system by self-organizing Kohonen network Mikhail S. Tarkov, Yakov S. Bezrukov Abstract.

More information

Distributed Computing over Communication Networks: Topology. (with an excursion to P2P)

Distributed Computing over Communication Networks: Topology. (with an excursion to P2P) Distributed Computing over Communication Networks: Topology (with an excursion to P2P) Some administrative comments... There will be a Skript for this part of the lecture. (Same as slides, except for today...

More information

Data Center Network Topologies: FatTree

Data Center Network Topologies: FatTree Data Center Network Topologies: FatTree Hakim Weatherspoon Assistant Professor, Dept of Computer Science CS 5413: High Performance Systems and Networking September 22, 2014 Slides used and adapted judiciously

More information

Lecture 2.1 : The Distributed Bellman-Ford Algorithm. Lecture 2.2 : The Destination Sequenced Distance Vector (DSDV) protocol

Lecture 2.1 : The Distributed Bellman-Ford Algorithm. Lecture 2.2 : The Destination Sequenced Distance Vector (DSDV) protocol Lecture 2 : The DSDV Protocol Lecture 2.1 : The Distributed Bellman-Ford Algorithm Lecture 2.2 : The Destination Sequenced Distance Vector (DSDV) protocol The Routing Problem S S D D The routing problem

More information

Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip

Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip Cristina SILVANO silvano@elet.polimi.it Politecnico di Milano, Milano (Italy) Talk Outline

More information

Router Architectures

Router Architectures Router Architectures An overview of router architectures. Introduction What is a Packet Switch? Basic Architectural Components Some Example Packet Switches The Evolution of IP Routers Copyright 1999. All

More information

Optimizing MPI Collective Communication by Orthogonal Structures

Optimizing MPI Collective Communication by Orthogonal Structures Optimizing MPI Collective Communication by Orthogonal Structures Matthias Kühnemann Fakultät für Informatik Technische Universität Chemnitz 917 Chemnitz, Germany kumat@informatik.tu chemnitz.de Gudula

More information

Circuit-Switched Coherence

Circuit-Switched Coherence Circuit-Switched Coherence Natalie Enright Jerger*, Li-Shiuan Peh +, Mikko Lipasti* *University of Wisconsin - Madison + Princeton University 2 nd IEEE International Symposium on Networks-on-Chip Motivation

More information

WAN Data Link Protocols

WAN Data Link Protocols WAN Data Link Protocols In addition to Physical layer devices, WANs require Data Link layer protocols to establish the link across the communication line from the sending to the receiving device. 1 Data

More information

CS252 S05. Connecting Multiple Computers. CMSC 411 Computer Systems Architecture Lecture 21 Networking. Connection-Based vs.

CS252 S05. Connecting Multiple Computers. CMSC 411 Computer Systems Architecture Lecture 21 Networking. Connection-Based vs. Connecting Multiple Computers CMSC 411 Computer Systems Architecture Lecture 21 Networking Shared Media vs. Switched: pairs communicate at same time: point-to-point connections Aggregate BW in ed network

More information

Computer Networks. By Hardeep Singh

Computer Networks. By Hardeep Singh Computer Networks Contents Introduction Basic Elements of communication systemnetwork Topologies Network types Introduction A Computer network is a network of computers that are geographically distributed,

More information

Optical interconnection networks with time slot routing

Optical interconnection networks with time slot routing Theoretical and Applied Informatics ISSN 896 5 Vol. x 00x, no. x pp. x x Optical interconnection networks with time slot routing IRENEUSZ SZCZEŚNIAK AND ROMAN WYRZYKOWSKI a a Institute of Computer and

More information

Local Area Networks (LANs)

Local Area Networks (LANs) Local Area Networks (LANs) Broadcast Networks Multiple Access Protocols Ethernet (IEEE 802.3) Token Ring (IEEE 802.5, FDDI) Introduction So far, we have dealt with switched communication networks. Recall

More information

Definition. A Historical Example

Definition. A Historical Example Overlay Networks This lecture contains slides created by Ion Stoica (UC Berkeley). Slides used with permission from author. All rights remain with author. Definition Network defines addressing, routing,

More information

Interconnection Networks

Interconnection Networks Advanced Computer Architecture (0630561) Lecture 15 Interconnection Networks Prof. Kasim M. Al-Aubidy Computer Eng. Dept. Interconnection Networks: Multiprocessors INs can be classified based on: 1. Mode

More information

Switched Interconnect for System-on-a-Chip Designs

Switched Interconnect for System-on-a-Chip Designs witched Interconnect for ystem-on-a-chip Designs Abstract Daniel iklund and Dake Liu Dept. of Physics and Measurement Technology Linköping University -581 83 Linköping {danwi,dake}@ifm.liu.se ith the increased

More information

Infrastructure Components: Hub & Repeater. Network Infrastructure. Switch: Realization. Infrastructure Components: Switch

Infrastructure Components: Hub & Repeater. Network Infrastructure. Switch: Realization. Infrastructure Components: Switch Network Infrastructure or building computer networks more complex than e.g. a short bus, some additional components are needed. They can be arranged hierarchically regarding their functionality: Repeater

More information

Computer Networks. Definition of LAN. Connection of Network. Key Points of LAN. Lecture 06 Connecting Networks

Computer Networks. Definition of LAN. Connection of Network. Key Points of LAN. Lecture 06 Connecting Networks Computer Networks Lecture 06 Connecting Networks Kuang-hua Chen Department of Library and Information Science National Taiwan University Local Area Networks (LAN) 5 kilometer IEEE 802.3 Ethernet IEEE 802.4

More information

Multiplexing From one channel to multiple channels

Multiplexing From one channel to multiple channels Multiplexing From one channel to multiple channels How to share one medium while facilitating multiple channels of communication: Frequency Division and Time Division Multiplexing 1 Frequency Division

More information

White Paper Abstract Disclaimer

White Paper Abstract Disclaimer White Paper Synopsis of the Data Streaming Logical Specification (Phase I) Based on: RapidIO Specification Part X: Data Streaming Logical Specification Rev. 1.2, 08/2004 Abstract The Data Streaming specification

More information

CS 78 Computer Networks. Internet Protocol (IP) our focus. The Network Layer. Interplay between routing and forwarding

CS 78 Computer Networks. Internet Protocol (IP) our focus. The Network Layer. Interplay between routing and forwarding CS 78 Computer Networks Internet Protocol (IP) Andrew T. Campbell campbell@cs.dartmouth.edu our focus What we will lean What s inside a router IP forwarding Internet Control Message Protocol (ICMP) IP

More information

From Hypercubes to Dragonflies a short history of interconnect

From Hypercubes to Dragonflies a short history of interconnect From Hypercubes to Dragonflies a short history of interconnect William J. Dally Computer Science Department Stanford University IAA Workshop July 21, 2008 IAA: # Outline The low-radix era High-radix routers

More information

CSCI 362 Computer and Network Security

CSCI 362 Computer and Network Security The Purpose of ing CSCI 362 Computer and Security Introduction to ing Goals: Remote exchange and remote process control. A few desirable properties: Interoperability, Flexibility, Geographical range, Scalability,

More information

Lecture Outline. Topology Design: I. Topologies and Reliability. Another Case: Mobile Performance Optimization. Jeremiah Deng.

Lecture Outline. Topology Design: I. Topologies and Reliability. Another Case: Mobile Performance Optimization. Jeremiah Deng. Lecture Outline Topology Design: I 1 Review Jeremiah Deng 2 University of Otago 3 1 / 22 Review Another Case: Mobile Performance Optimization 2 / 22 Topologies and Reliability T. Everts, Rules for mobile

More information

Journal of Parallel and Distributed Computing 61, 11481179 (2001) doi:10.1006jpdc.2001.1747, available online at http:www.idealibrary.com on Adaptive Routing on the New Switch Chip for IBM SP Systems Bulent

More information

Packetization and routing analysis of on-chip multiprocessor networks

Packetization and routing analysis of on-chip multiprocessor networks Journal of Systems Architecture 50 (2004) 81 104 www.elsevier.com/locate/sysarc Packetization and routing analysis of on-chip multiprocessor networks Terry Tao Ye a, *, Luca Benini b, Giovanni De Micheli

More information

WAN. Introduction. Services used by WAN. Circuit Switched Services. Architecture of Switch Services

WAN. Introduction. Services used by WAN. Circuit Switched Services. Architecture of Switch Services WAN Introduction Wide area networks (WANs) Connect BNs and LANs across longer distances, often hundreds of miles or more Typically built by using leased circuits from common carriers such as AT&T Most

More information

Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point:

Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point: Point-to-Point Vs. Shared Channel Communication In LANs Point-to-point: Computers connected by communication channels that each connect exactly two computers with access to full channel bandwidth. Forms

More information

LOAD-BALANCED ROUTING IN INTERCONNECTION NETWORKS

LOAD-BALANCED ROUTING IN INTERCONNECTION NETWORKS LOAD-BALANCED ROUTING IN INTERCONNECTION NETWORKS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT

More information

R2. The word protocol is often used to describe diplomatic relations. How does Wikipedia describe diplomatic protocol?

R2. The word protocol is often used to describe diplomatic relations. How does Wikipedia describe diplomatic protocol? Chapter 1 Review Questions R1. What is the difference between a host and an end system? List several different types of end systems. Is a Web server an end system? 1. There is no difference. Throughout

More information

MPLS. Packet switching vs. circuit switching Virtual circuits

MPLS. Packet switching vs. circuit switching Virtual circuits MPLS Circuit switching Packet switching vs. circuit switching Virtual circuits MPLS Labels and label-switching Forwarding Equivalence Classes Label distribution MPLS applications Packet switching vs. circuit

More information

Parallel Computing. Benson Muite. benson.muite@ut.ee http://math.ut.ee/ benson. https://courses.cs.ut.ee/2014/paralleel/fall/main/homepage

Parallel Computing. Benson Muite. benson.muite@ut.ee http://math.ut.ee/ benson. https://courses.cs.ut.ee/2014/paralleel/fall/main/homepage Parallel Computing Benson Muite benson.muite@ut.ee http://math.ut.ee/ benson https://courses.cs.ut.ee/2014/paralleel/fall/main/homepage 3 November 2014 Hadoop, Review Hadoop Hadoop History Hadoop Framework

More information

Module 6. Internetworking. Version 2 CSE IIT, Kharagpur

Module 6. Internetworking. Version 2 CSE IIT, Kharagpur Module 6 Internetworking Lesson 1 Internetworking Devices Specific Instructional Objectives At the end of this lesson, the students will be able to: Specify the need for internetworking State various issues

More information

Real-Time (Paradigms) (51)

Real-Time (Paradigms) (51) Real-Time (Paradigms) (51) 5. Real-Time Communication Data flow (communication) in embedded systems : Sensor --> Controller Controller --> Actor Controller --> Display Controller Controller Major

More information

PART III. OPS-based wide area networks

PART III. OPS-based wide area networks PART III OPS-based wide area networks Chapter 7 Introduction to the OPS-based wide area network 7.1 State-of-the-art In this thesis, we consider the general switch architecture with full connectivity

More information

Lecture 6 Types of Computer Networks and their Topologies Three important groups of computer networks: LAN, MAN, WAN

Lecture 6 Types of Computer Networks and their Topologies Three important groups of computer networks: LAN, MAN, WAN Lecture 6 Types of Computer Networks and their Topologies Three important groups of computer networks: LAN, MAN, WAN LAN (Local Area Networks) 10/28/2008 Vasile Dadarlat - Computer Networks 1 MAN (Metropolitan

More information

Performance of networks containing both MaxNet and SumNet links

Performance of networks containing both MaxNet and SumNet links Performance of networks containing both MaxNet and SumNet links Lachlan L. H. Andrew and Bartek P. Wydrowski Abstract Both MaxNet and SumNet are distributed congestion control architectures suitable for

More information

Bandwidth Efficient All-to-All Broadcast on Switched Clusters

Bandwidth Efficient All-to-All Broadcast on Switched Clusters Bandwidth Efficient All-to-All Broadcast on Switched Clusters Ahmad Faraj Pitch Patarasuk Xin Yuan Blue Gene Software Development Department of Computer Science IBM Corporation Florida State University

More information

Annotation to the assignments and the solution sheet. Note the following points

Annotation to the assignments and the solution sheet. Note the following points Computer rchitecture 2 / dvanced Computer rchitecture Seite: 1 nnotation to the assignments and the solution sheet This is a multiple choice examination, that means: Solution approaches are not assessed

More information

Computer Networking: A Survey

Computer Networking: A Survey Computer Networking: A Survey M. Benaiah Deva Kumar and B. Deepa, 1 Scholar, 2 Assistant Professor, IT Department, Sri Krishna College of Arts and Science College, Coimbatore, India. Abstract- Computer

More information

Architecture of distributed network processors: specifics of application in information security systems

Architecture of distributed network processors: specifics of application in information security systems Architecture of distributed network processors: specifics of application in information security systems V.Zaborovsky, Politechnical University, Sait-Petersburg, Russia vlad@neva.ru 1. Introduction Modern

More information