FEATRES Dual DACs with 12-Bit Resolution SO-8 Package Rail-to-Rail Output Amplifiers Internal Reference Maximum DNL Error:.5LSB 3V Operation (LTC1446L): I CC = 65µA Typ 5V Operation (LTC1446): I CC = 1µA Typ Settling Time: 14µs to ±.5LSB Power-On Reset Clears DACs to V 3-Wire Cascadable Serial Interface with 5kHz pdate Rate Schmitt Trigger On Input Allows Direct Optocoupler Interface Low Cost APPLICATIO S Digital Calibration Industrial Process Control Automatic Test Equipment DESCRIPTIO LTC1446/LTC1446L Dual 12-Bit Rail-to-Rail Micropower DACs in SO-8 The LTC 1446/LTC1446L are dual 12-bit digital-to-analog converters (DACs) available in an SO-8 package. They are complete with a rail-to-rail voltage output amplifier, an internal reference and an easy-to-use 3-wire cascadable serial interface. The LTC1446 has an internal reference and a full-scale output of 4.95V. It operates from a single 4.5V to 5.5V supply. The LTC1446L has an internal reference and a full-scale output of 2.5V. It operates from a single 2.7V to 5.5V supply. The low power supply current makes the LTC1446 family ideal for battery-powered applications. These DACs are available in space saving 8-pin SO and PDIP packages and require no external components for operation. Cellular Telephones, LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION µp 2 1 3 4 CLK Functional Block Diagram: Dual 12-Bit Rail-to-Rail DAC CS/LD D OT 7 24-BIT SHIFT REG AND DAC LATCH V CC POWER-ON RESET LTC1446: 5V LTC1446L: 3V TO 5V 12-BIT DAC B 12-BIT DAC A GND + + V OT B V OT A 6 1446/1446L TA1 8 RAIL-TO-RAIL VOLTAGE OTPT 5 DNL ERROR (LSB) Differential Nonlinearity vs Input Code.5.4.3.2.1.1.2.3.4.5 512 124 1536 248 256 372 3584 495 CODE 1446/46L G13 1
ABSOLTE AXI RATI GS W W W V CC to GND....5 to 7.5V Logic Inputs to GND....5 to 7.5V Operating Temperature Range LTC1446C/LTC1446LC... C to 7 C LTC1446I/LTC1446LI... 4 C to 85 C (Note 1) V OT A /V OT B....5V to V CC +.5V Maximum Junction Temperature... 125 C Storage Temperature Range... 65 C to 15 C Lead Temperature (Soldering, 1 sec)... 3 C PACKAGE/ORDER INFORMATION CLK 1 2 CS/LD 3 D OT 4 TOP VIEW 8 7 6 5 N8 PACKAGE 8-LEAD PDIP T JMAX = 125 C, θ JA = 1 C/W V OT B V CC GND V OT A Consult factory for Military grade parts. W ORDER PART NMBER LTC1446CN8 LTC1446IN8 LTC1446LCN8 LTC1446LIN8 CLK 1 2 CS/LD 3 D OT 4 TOP VIEW 8 7 6 5 S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = 125 C, θ JA = 15 C/W V OT B V CC GND V OT A ORDER PART NMBER LTC1446CS8 LTC1446IS8 LTC1446LCS8 LTC1446LIS8 S8 PART MARKING 1446 1446L 1446I 1446LI ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range. V CC = 4.5V to 5.5V (LTC1446), 2.7V to 5.5V (LTC1446L), V OT A and V OT B unloaded, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS DAC Resolution 12 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) ±.2 ±.5 LSB INL Integral Nonlinearity T A = 25 C ±2. 4.5 LSB ±2.5 5. LSB ZSE Zero-Scale Error 3 18 mv V OS Offset Error ±2 ±18 mv V OS TC Offset Error Tempco ±15 µv/ C V FS Full-Scale Voltage LTC1446, T A = 25 C 4.65 4.95 4.125 V LTC1446 4.45 4.95 4.145 V LTC1446L, T A = 25 C 2.47 2.5 2.53 V LTC1446L 2.46 2.5 2.54 V V FS TC Full-Scale Voltage Tempco ±.1 LSB/ C Power Supply (LTC1446) V CC Positive Supply Voltage For Specified Performance 4.5 5.5 V I CC Supply Current 4.5V V CC 5.5V (Note 5) 1 15 µa Power Supply (LTC1446L) V CC Positive Supply Voltage For Specified Performance 2.7 5.5 V I CC Supply Current 2.7V V CC 5.5V (Note 5) 65 1 µa 2
ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range. V CC = 4.5V to 5.5V (LTC1446), 2.7V to 5.5V (LTC1446L), V OT A and V OT B unloaded, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Op Amp DC Performance Short-Circuit Current Low V OT Shorted to GND 55 12 ma Short-Circuit Current High V OT Shorted to V CC 7 12 ma Output Impedance to GND Input Code = 4 16 Ω AC Performance Voltage Output Slew Rate (Note 3).5 1 V/µs Voltage Output Settling Time (Notes 3, 4) to ±.5LSB 14 µs The denotes the specifications which apply over the full operating temperature range.v CC = 5V (LTC1446), V CC = 3V (LTC1446L), T A = T MIN to T MAX, unless otherwise noted. LTC1446 LTC1446L SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Digital I/O V IH Digital Input High Voltage 2.4 2 V V IL Digital Input Low Voltage.8.6 V V OH Digital Output High Voltage I OT = 1mA V CC 1. V CC.7 V V OL Digital Output Low Voltage I OT = 1mA.4.4 V I LEAK Digital Input Leakage V IN = GND to V CC ±1 ±1 µa C IN Digital Input Capacitance Guaranteed by Design 1 1 pf Switching t 1 Valid to CLK Setup 4 6 ns t 2 Valid to CLK Hold ns t 3 CLK High Time 4 6 ns t 4 CLK Low Time 4 6 ns t 5 CS/LD Pulse Width 5 8 ns t 6 LSB CLK to CS/LD 4 6 ns t 7 CS/LD Low to CLK 2 3 ns t 8 D OT Output Delay C LOAD = 15pF 15 22 ns t 9 CLK Low to CS/LD Low 2 3 ns Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 495 (full scale). Note 3: Load is 5kΩ in parallel with 1pF. Note 4: DAC switched between all 1s and the code corresponding to V OS for the part. Note 5: Digital inputs at V or V CC. 3
TYPICAL PERFORMANCE CHARACTERISTICS DNL ERROR (LSB).5.4.3.2.1.1.2.3.4.5 W LTC1446 Differential Nonlinearity (DNL) LTC1446 Integral Nonlinearity (INL) LTC1446L Differential Nonlinearity 512 124 1536 248 256 372 3584 495 CODE INL ERROR (LSB) 3 2 1 1 2 3 512 124 1536 248 256 372 3584 495 CODE DNL ERROR (LSB).5.4.3.2.1.1.2.3.4.5 512 124 1536 248 256 372 3584 495 CODE 1446/46L G1 1446/46L G2 1446/46L G3 INL ERROR (LSB) 3 2 1 1 2 LTC1446L Integral Nonlinearity V CC V OT (V).8.6.4.2 LTC1446 Min Supply Headroom for Full Output Swing vs Load Current V OT < 1LSB CODE: ALL 1's V OT = 4.95V V CC V OT 1.2 1..8.6.4.2 LTC1446L Min Supply Headroom for Full Output Swing vs Load Current V OT < 1LSB CODE: ALL 1's V OT = 2.5V 3 512 124 1536 248 256 372 3584 495 CODE 5 1 LOAD CRRENT (ma) 15 5 1 LOAD CRRENT (ma) 15 1446/46L G4 LTC1446/46L TPC5 LTC1446/46L TPC6 OTPT PLL-DOWN VOLTAGE (mv) 6 5 4 3 2 1 LTC1446 Min Output Voltage vs Output Sink Current CODE: ALL 'S 125 C 25 C 55 C FLL-SCALE VOLTAGE (V) 4.11 4.1 4.9 4.8 LTC1446 Full-Scale Voltage vs Temperature SPPLY CRRENT (ma) 3. 2.6 2.2 1.8 1.4 1. LTC1446 Supply Current vs Logic Input Voltage 5 1 OTPT SINK CRRENT (ma) 15 4.7 55 25 5 35 65 TEMPERATRE ( C) 95 125.6 1 2 3 4 LOGIC INPT VOLTAGE (V) 5 LTC1446/46L TPC7 1446/46L G9 1446/46L G9 4
TYPICAL PERFORMANCE CHARACTERISTICS W 1.2 LTC1446L Supply Current vs Logic Input Voltage 97 LTC1446 Supply Current vs Temperature 7 LTC1446L Supply Current vs Temperature 1.1 96 69 SPPLY CRRENT (ma) 1..9.8.7 SPPLY CRRENT (µa) 95 94 93 92 V CC = 5.5V V CC = 5V SPPLY CRRENT (µa) 68 67 66 65 64 V CC = 3.3V V CC = 3V V CC = 2.7V.6 91 V CC = 4.5V 63.5.5 1. 1.5 2. 2.5 3. LOGIC INPT VOLTAGE (V) 9 55 35 15 5 25 45 65 85 15 TEMPERATRE ( C) 125 62 55 35 15 5 25 45 65 85 15 125 TEMPERATRE ( C) 1446/46L G1 1446/46L G11 1446/46L G12 Large Signal Transient Response V OT (2V/DIV) CS/LD (5V/DIV) TIME (1µs/DIV) 1446L G13 PIN FNCTIONS CLK: The Serial Interface Clock. : The Serial Interface Data. CS/LD: The Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high data is loaded from the shift register into the DAC registers, updating the DAC outputs. D OT : The output of the shift register which becomes valid on the rising edge of the serial clock. GND: Ground. V OT A,V OT B : Buffered DAC Outputs. V CC : Positive Supply Input. 4.5V V CC 5.5V (LTC1446), 2.7V V CC 5.5V (LTC1446L). Requires a.1µf bypass capacitor to ground. 5
BLOCK DIAGRAM W REFERENCE CLK 1 LD DAC B REGISTER 12-BIT DAC B + 8 V OT B 2 24-BIT SHIFT REGISTER 7 V CC CS/LD 3 LD DAC A REGISTER 12-BIT DAC A + 6 GND D OT 4 5 V OT A POWER-ON RESET 1446BD W W TI I G DIAGRA t 4 t 3 t 1 t 2 t 6 t 7 CLK t 9 B-B PREVIOS WORD B11-A MSB B-A LSB B11-B MSB B-B LSB t 8 t 5 CS/LD D OT B11-A PREVIOS WORD B1-A PREVIOS WORD B-A PREVIOS WORD B11-B PREV WORD B1-B PREV WORD B-B PREV WORD B11-A CRRENT WORD 1446 TD 6
DEFI ITIO S Resolution (n) Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2 n ) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (V FS ) This is the output of the DAC when all bits are set to one. Voltage Offset Error (V OS ) The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near V resulting in the transfer curve shown in Figure 1. OTPT VOLTAGE NEGATIVE OFFSET V DAC CODE Figure 1. Effect of Negative Offset 1446/46L F1 The offset of the part is measured at the code that corresponds to the maximum offset specification: V OS = V OT [(Code)(V FS )/(2 n 1)] Least Significant Bit (LSB) One LSB is the ideal voltage difference between two successive codes. LSB = (V FS V OS )/(2 n 1) = (V FS V OS )/495 LTC1446/LTC1446L Nominal LSBs: LTC1446 LSB = 4.95V/495 = 1mV LTC1446L LSB = 2.5V/495 =.61mV Zero Scale Error (ZSE) The output voltage when the DAC is loaded with all zeros. Since this is a single supply part this value cannot be less than V. Integral Nonlinearity (INL) End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows : INL = [V OT V OS (V FS V OS )(Code/495)]/LSB V OT = the output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = ( V OT LSB)/LSB V OT = The measured voltage difference between two adjacent codes 7
OPERATIO LTC1446/LTC1446L Serial Interface The data on the input is loaded into the shift register on the rising edge of the clock. Data is loaded as one 24- bit word where the first 12 bits are for DAC A and the second 12 are for DAC B. For each 12-bit segment the MSB is loaded first. Data from the shift register is loaded into the DAC register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The buffered output of the 24-bit shift register is available on the D OT pin which swings from GND to V CC. Multiple LTC1446/LTC1446L s may be daisy-chained together by connecting the D OT pin to the pin of the next chip, while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC1446/LTC1446L include an internal voltage reference which is connected to each DAC. The LTC1446 has a full scale of 4.95V making 1LSB equal to 1mV. The LTC1446L has a full scale of 2.5V making 1LSB equal to.61mv. The LTC1446/LTC1446L rail-to-rail buffered outputs can source or sink 5mA when operating with a 5V supply while pulling to within 3mV of the positive supply voltage or ground. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 4Ω when driving a load to the rails. The buffer amplifiers can drive 1pF without going into oscillation. The output noise spectral density is 6nV/ Hz at 1kHz. 8
TYPICAL APPLICATIONS N This circuit shows how to use an LTC1446 and an LT 177 to make a wide bipolar output swing 12-bit DAC with an offset that can be digitally programmed. V OT A, which can be set by loading the appropriate digital code for DAC A, sets the offset. As this value changes, the transfer curve for the output moves up and down as illustrated in the graph below. A Wide Swing, Bipolar Output DAC with Digitally Controlled Offset 5V.1µF CLK V OT B 15V 5k µp LTC1446 CS/LD V CC GND 1k + LT177 V OT = 2 (V OT B V OT A) D OT V OT A 15V 5k 1k 8.19 V OT A 4.94 B C 4.96 A: V OT A V B: V OT A 2.48V 8.19 C: V OT A 4.95V 1446/46L F2 9
TYPICAL APPLICATIONS N This circuit shows how to use one LTC1446 to make an autoranging ADC. The microprocessor sets the reference span and the Common pin for the analog input by loading the appropriate digital code into the LTC1446. V OT A controls the Common pin for the analog inputs to the LTC1296 and V OT B controls the reference span by setting the REF + pin on the LTC1296. The LTC1296 has a Shutdown pin that goes low in shutdown mode. This will turn off the PNP transistor supplying power to the LTC1446. The resistor and capacitor on the LTC1446 outputs act as a lowpass filter for noise. An Autoranging 8-Channel ADC with Shutdown 22µF + 5V CS V CC CH µp D OT CLK LTC1296 CH7 COM REF + SSO REF 8 ANALOG INPT CHANNELS 74HC4 5k 5k 5V 2N396.1µF CLK V OT B 1Ω.1µF CS/LD LTC1446 V CC GND D OT V OT A 1Ω.1µF 1446/46L F3 1
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow.3) (LTC DWG# 5-8-151).4* (1.16) MAX 8 7 6 5.255 ±.15* (6.477 ±.381) 1 2 3 4.3.325 (7.62 8.255).45.65 (1.143 1.651).13 ±.5 (3.32 ±.127).9.15 (.229.381).325 +.25.15 +.635 8.255.381 ( ).65 (1.651) TYP.5 (.127) MIN.1 ±.1 (2.54 ±.254) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED.1 INCH (.254mm).125 (3.175) MIN.18 ±.3 (.457 ±.76).15 (.38) MIN N8 695 S8 Package 8-Lead Plastic Small Outline (Narrow.15) (LTC DWG # 5-8-161).189.197* (4.81 5.4) 8 7 6 5.228.244 (5.791 6.197).15.157** (3.81 3.988) 1 2 3 4.8.1 (.23.254).1.2 (.254.58) 45 8 TYP.53.69 (1.346 1.752).4.1 (.11.254).16.5.46 1.27 * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.152mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED.1" (.254mm) PER SIDE.14.19 (.355.483).5 (1.27) BSC SO8 695 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11
RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC1257 Single 12-Bit V OT DAC, Full Scale: 2.48V, V CC : 4.75V to 15.75V, 5V to 15V Single Supply, Complete V OT DAC in SO-8 Package Reference Can Be Overdriven up to 12V, i.e., FS Max = 12V LTC1451 Single Rail-to-Rail Output 12-Bit DAC, Low Power, Complete V OT DAC in SO-8 Package Full Scale: 4.95V, V CC : 4.5V to 5.5V Internal 2.48V Reference Brought Out to Pin LTC1452 Single Rail-to-Rail 12-Bit V OT Mulitplying DAC, V CC : 2.7V to 5.5V Low Power, Mulitplying V OT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package LTC1453 Single Rail-to-Rail 12-Bit V OT DAC, 3V, Low Power, Complete V OT DAC in SO-8 Package Full Scale: 2.5V, V CC : 2.7V to 5.5V LTC1454/LTC1454L Dual 12-Bit V OT DACs in a 16-Lead SO Package LTC1454: V CC = 4.5V to 5.5V, V OT = V to 4.95V with Added Functionality LTC1454L: V CC = 2.7V to 5.5V, V OT = V to 2.5V LTC1456 Single Rail-to-Rail Output 12-Bit DAC with Clear Pin Low Power, Complete V OT DAC in SO-8 Package Full Scale: 4.95V, V CC : 4.5V to 5.5V with Clear Pin LTC1458/LTC1458L Quad 12-Bit V OT DACs in 28-Lead SW and SSOP Packages LTC1458: V CC = 4.5V to 5.5V, V OT = V to 4.95V LTC1458L: V CC = 2.7V to 5.5V, V OT = V to 2.5V LTC1654 Dual 14-Bit DAC in SSOP Variable Speed, Variable Gain, 1LSB DNL LTC1661 Dual 1-Bit V OT DAC in MSOP Low Cost,.75LSB DNL LTC1662 Dual 1-Bit V OT DAC in MSOP ltra Low Power = 1.5µA Supply Current 12 Linear Technology Corporation 163 McCarthy Blvd., Milpitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 TELEX: 499-3977 1446lfa LT/LCG 7 2K REV A PRINTE SA LINEAR TECHNOLOGY CORPORATION 1996