EE247 Lecture 9 ADC Converters - ADC architectures - Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Sample-data comparators Offset cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page ADC Architectures Slope Converters Successive approximation Flash Folding Time-interleaved / parallel converter Residue type ADCs Two-step Pipeline Algorithmic Oversampled ADCs EECS 247 Lecture 9: Data Converters 24 H.K. Page 2
Residue Type ADC Partial Digital Output V IN coarse ADC (... 6 Bit) DAC Error S/H & Gain (optional) Quantization error output ( residuum ) enables cascading for higher resolution Great flexibility for stages: flash, oversampling ADC, Optional S/H enables parallelism (pipelining) Fast: one clock per conversion (with S/H), latency EECS 247 Lecture 9: Data Converters 24 H.K. Page 3 Pipelined ADC V IN Stage B Bits Stage 2 B 2 Bits Stage K B k Bits Digital Correction Logic Digital output up to (B + B 2 +... + B k ) Bits Approaches speed of flash, but much lower complexity One clock per conversion, but K clocks latency Efficient digital calibration possible Versatile: from 6Bits / MS/s to 4Bits / MS/s EECS 247 Lecture 9: Data Converters 24 H.K. Page 4
Algorithmic ADC Digital Output start of conversion Shift Register & Correction Logic V IN coarse ADC (... 6 Bit) DAC Error 2 B S/H Essentially same as pipeline, but a single stage is used for all partial conversions K clocks per conversion EECS 247 Lecture 9: Data Converters 24 H.K. Page 5 Oversampled ADC f s f s /M V IN H(z) Digital Decimation Filter Digital Output DAC Hard to comprehend easy to build Input is oversampled (M times faster than output rate) Reduces Anti-Aliasing filter requirements and capacitor size Accuracy independent of component matching Very high resolution achievable (> 2 Bits) EECS 247 Lecture 9: Data Converters 24 H.K. Page 6
Throughput Rate Comparison Resolution [Bit] 8 6 4 2 8 6 4 2 Flash, Pipeline~ to 2 Successive Approximation~B 2 nd Order -Bit Oversampled ~2 (.4B+) Serial ~2 B 2 3 4 5 Clock Cycles per Conversion EECS 247 Lecture 9: Data Converters 24 H.K. Page 7 Speed-Resolution Map [www.v-corp.com] EECS 247 Lecture 9: Data Converters 24 H.K. Page 8
High-Speed A/D Converters Flash Converter Comparator design considerations Binary Encoder Interpolation Folding Pipelined ADCs EECS 247 Lecture 9: Data Converters 24 H.K. Page 9 Flash Converter Very fast: only clock cycle per conversion R/2 V REF R V IN High complexity: 2 B - comparators R Encoder Digital Output R High input capacitance R R/2 EECS 247 Lecture 9: Data Converters 24 H.K. Page
Voltage Comparators + V in - + - V out ( Digital Output) Function: compare the instantaneous value of two analog signals Important features: Maximum clock rate f s settling time, slew rate, small signal bandwidth Resolution gain, offset Overdrive recovery Input capacitance (and linearity!) Power dissipation Common-mode rejection Kickback noise Ref: Prof. B. Wooley, Course notes EE35 Stanford University EECS 247 Lecture 9: Data Converters 24 H.K. Page Voltage Comparator Architectures Comparator architectures High gain amplifier with differential analog input & single-ended large swing output Output swing compatible with driving digital logic circuits Open-loop amplification no frequency compensation required Precise gain not required Latched comparators; in response to a strobe, input stage disabled & digital output stored in a latch till next strobe Two options for implementation : High-gain amplifier + simple digital latch Low-gain amplifier + a high-sensitivity latch Sample-data comparators S/H input Offset cancellation Pipelined stages EECS 247 Lecture 9: Data Converters 24 H.K. Page 2
Comparators w/ High-Gain Amplification Amplify V in (min) to V DD V in (min) determined by ADC resolution Example: 2-bit res. & full-scale input 2V LSB=.5mV For 2.5V output: 2.5V Av = =,.25mV V os < LSB EECS 247 Lecture 9: Data Converters 24 H.K. Page 3 Comparators w/ High-Gain Amplification f u =-MHz f =unity gain frequency, f = 3 db frequency f u fu GHz = = = khz A, V τ = =.6µ sec 2π f Too slow! Cascade of lower gain stages to broadband response EECS 247 Lecture 9: Data Converters 24 H.K. Page 4
Open Loop Cascade of Amplifiers The stages identical small-signal model for the cascades: For -stage only: EECS 247 Lecture 9: Data Converters 24 H.K. Page 5 Open Loop Cascade of Amplifiers For Cascade of N-stages: EECS 247 Lecture 9: Data Converters 24 H.K. Page 6
Open Loop Cascade of Amplifiers For A T (DC) =, Example : N = 3, f =GHz, A () = f N /3 N u (,) N T GHz /3 = 2 = 24MHz τ N = = 7nsec (.6µ s for -stage) 2π f 5τ = 35nsec Cascade of 3-stage speed 236 higher compared to -stage (constant overall gain & f u ) EECS 247 Lecture 9: Data Converters 24 H.K. Page 7 Open Loop Cascade of Amplifiers Offset Voltage Cascade of amplifiers Input-referred offset increases Choice of # of stages important Speed vs offset tradeoff Example: For 3-stage case with gain/stage ~22 Increase in offset ~ 4.5% EECS 247 Lecture 9: Data Converters 24 H.K. Page 8
Open Loop Cascade of Amplifiers Step Response Assuming linear behavior t EECS 247 Lecture 9: Data Converters 24 H.K. Page 9 Open Loop Cascade of Amplifiers Step Response Assuming linear behavior EECS 247 Lecture 9: Data Converters 24 H.K. Page 2
Open Loop Cascade of Amplifiers Delay/(C/g m ) Minimum total delay broad function of N Relationship between # of stages that minimize delay (N op ) and gain (V out /V in ) approximately: Delay/(C/g m ) N op =.xln(v out /V in ) +.79 for gain < Or gain of db (sqrt) per stage results in near optimum delay Ref: J.T. Wu, et al., A -MHz pipelined CMOS comparator IEEE Journal of Solid-State Circuits, vol. 23, pp. 379-385, December 988. EECS 247 Lecture 9: Data Converters 24 H.K. Page 2 Offset Cancellation Disadvantage of using cascade of amplifiers: Increased overall input-referred offset Sampled-data cascade of amplifiers V os can be cancelled Store on ac-coupling capacitors in series with amplifier stages Offset associated with a specific amplifier can be cancelled by storing it in series with either the input or the output of that stage EECS 247 Lecture 9: Data Converters 24 H.K. Page 22
Offset Cancellation Output Series Cancellation Amp modeled as ideal + V os (input referred) Store offset: S, S4 open S2, S3 closed V C =AxV OS EECS 247 Lecture 9: Data Converters 24 H.K. Page 23 Offset Cancellation Output Series Cancellation Amplify: S, S4 closed S2, S3 open V C =AxV OS Circuit requirements: Amp not saturate during offset storage High-impedance (C) load C c not discharged C c >> C L to avoid attenuation C c >> C switch offset due to charge injection EECS 247 Lecture 9: Data Converters 24 H.K. Page 24
Offset Cancellation Cascaded Output Series Cancellation Note: Extra offset cancellation phase required Overall speed compromised EECS 247 Lecture 9: Data Converters 24 H.K. Page 25 Offset Cancellation Cascaded Output Series Cancellation - S open, S2,3,4,5 closed V C =A xv os V C2 =A 2 xv os2 V C3 =A 3 xv os3 EECS 247 Lecture 9: Data Converters 24 H.K. Page 26
Offset Cancellation Cascaded Output Series Cancellation 2- S3 open Feedthrough from S3 offset on X Switch offset, ε 2 stored on C Since S4 remains closed, offset associated with ε 2 stored on C2 V X = ε 2 V C =A xv os - ε 2 V C2 =A 2 x(v os2 + ε 2 ) EECS 247 Lecture 9: Data Converters 24 H.K. Page 27 Offset Cancellation Cascaded Output Series Cancellation 3- S4 open Feedthrough from S4 offset on Y Switch offset, ε 3 stored on C2 Since S5 remains closed, offset associated with ε 3 stored on C3 V Y = ε 3 V C2 =A 2 x(v os2 + ε 2 ) - ε 3 V C3 =A 3 x(v os3 + ε 3 ) EECS 247 Lecture 9: Data Converters 24 H.K. Page 28
Offset Cancellation Cascaded Output Series Cancellation 4- S2 open, S closed, S5 open S closed & S2 open since input connected to low impedance source charge injection not of major concern Switch offset, ε 4 introduced due to S5 opening ε 4 not cancelled As shown in the following analysis, ε 4 referred to the input will be attenuated by the overall gain EECS 247 Lecture 9: Data Converters 24 H.K. Page 29 Offset Cancellation Cascaded Output Series Cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 3
Offset Cancellation Cascaded Output Series Cancellation Example: 3-stage open-loop differential amplifier with offset cancellation + output amplifier (see ref.) A Total (DC) = 2x 6 = 2dB Input-referred offset < 5µV Input-referred offset drift <.5µV Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid- State Circuits, vol. 3, pp. 499-53, August 978. EECS 247 Lecture 9: Data Converters 24 H.K. Page 3 Offset Cancellation Input Series Cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 32
Offset Cancellation Input Series Cancellation Store offset + -V C /A - Note: Amplifier has to be compensated for unity gain stability EECS 247 Lecture 9: Data Converters 24 H.K. Page 33 Amplify S2, S3 open S closed Offset Cancellation Input Series Cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 34
Offset Cancellation Cascaded Input Series Cancellation ε 2 opening of S4 charge injection Amplifier A offset fully cancelled Amplifier A2 offset attenuated by /A.A2 Error associated with opening of S4 charge injection attenuated by /A EECS 247 Lecture 9: Data Converters 24 H.K. Page 35 CMOS Comparators Cascade of Gain Stages Fully differential gain stages st order cancellation of switch feedthrough & charge injection offsets -Output series offset cancellation 2- Input series offset cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 36
CMOS Comparators Cascade of Gain Stages 3-Combined input & output series offset cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 37 CMOS Latched Comparators Comparator amplification need not be linear can use a latch regeneration Amplification + positive feedback EECS 247 Lecture 9: Data Converters 24 H.K. Page 38
CMOS Latched Comparators Latch can be modeled as a single-pole amp + positive feedback EECS 247 Lecture 9: Data Converters 24 H.K. Page 39 CMOS Latched Comparators Delay Normalized Latch Delay τ D (3-state amp)= 8.2(C/g m ) Compared to a 3-stage open-loop cascade of amps for equal gain of Latch faster by about x3 Only drawback high latch offset (typically - mv) Use preamp w/gain =- to reduce input-referred latch offset Or use offset cancellation EECS 247 Lecture 9: Data Converters 24 H.K. Page 4
Latched Comparator f s V i+ A v Latch D o+ V i- D o- Preamp Clock rate f s Resolution Overload recovery Input capacitance (and linearity!) Power dissipation Common-mode rejection Kickback noise EECS 247 Lecture 9: Data Converters 24 H.K. Page 4 Comparators Overdrive Recovery Linear model for a single-pole amplifier: U amplification after time t a During reset amplifier settles exponentially to its zero input condition with τ =RC Assume Vm maximum input normalized to /2lsb (=) Example: Worst case input/output waveforms Limit output voltage swing by. Passive clamp 2. Active restore 3. Low gain/stage EECS 247 Lecture 9: Data Converters 24 H.K. Page 42
Comparators Overdrive Recovery Limiting Output Clamp Adds parasitic capacitance Active Restore After outputs are latched Activate φ R & equalize output nodes EECS 247 Lecture 9: Data Converters 24 H.K. Page 43 CMOS Comparator Example Flash ADC: 8bits, +-/2LSB INL @ fs=5mhz (Vref=3.8V) No offset cancellation A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, JSSC June 985, pp. 775-9. EECS 247 Lecture 9: Data Converters 24 H.K. Page 44
Comparator with Auto-Zero I. Mehr and L. Singer, A 5-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications, JSSC July 999, pp. 92-2. EECS 247 Lecture 9: Data Converters 24 H.K. Page 45 Auto-Zero Implementation Ref:I. Mehr and L. Singer, A 55-mW, -bit, 4-Msample/s Nyquist-Rate CMOS ADC, JSSC March 2, pp. 38-25. EECS 247 Lecture 9: Data Converters 24 H.K. Page 46
Comparator Example Variation on Yukawa latch used w/o preamp No dc power when φ high Good for low resolution ADCs M & M2 added to vary comparator threshold To st order, for W=W2 & W=W2 V th latch = W/W x V R where V R =V R+ - V R- Ref: T. B. Cho and P. R. Gray, "A b, 2 Msample/s, 35 mw pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 3, pp. 66-72, March 995. EECS 247 Lecture 9: Data Converters 24 H.K. Page 47 Comparator Example Used in a pipelined ADC with digital correction no offset cancellation Note differential reference M7, M8 operate in triode region Preamp gain ~ Input buffers suppress kick-back Ref: S. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC,NO. 6, Dec. 987 EECS 247 Lecture 9: Data Converters 24 H.K. Page 48
Flash Converter Errors V REF R/2 R R R V IN Encoder Digital Output Comparator input: Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time R R/2 Comparator output: Sparkle codes ( ) Metastability EECS 247 Lecture 9: Data Converters 24 H.K. Page 49 Typical Flash Output Decoder Binary Output (negative) Thermometer to Binary decoder ROM EECS 247 Lecture 9: Data Converters 24 H.K. Page 5
Sparkle Codes Binary Output (negative) Correct Output: Actual Output: Erronous (comparator offset?) EECS 247 Lecture 9: Data Converters 24 H.K. Page 5 Sparkle Tolerant Encoder Binary Output (negative) Protects against a single sparkle. Ref: C. Mangelsdorf et al, A 4-MHz Flash Converter with Error Correction, JSSC February 99, pp. 997-2. EECS 247 Lecture 9: Data Converters 24 H.K. Page 52
X Meta Stability Binary Output (negative) Different gates interpret metastable output X differently Correct Output: or Actual Output: Solutions: Latches (high power) Gray encoding Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 996, pp. 32-4. EECS 247 Lecture 9: Data Converters 24 H.K. Page 53 Gray Encoding Thermometer Code Gray Binary T T 2 T 3 T 4 T 5 T 6 T 7 G 3 G 2 G B 3 B 2 B G = T T + T T G G 2 3 2 4 3 = T T = T 6 5 7 Each T i affects only one G i Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder EECS 247 Lecture 9: Data Converters 24 H.K. Page 54