LT Low Power V RS Dual Driver/Receiver with Capacitors FEATRES ESD Protection over ±kv Low Cost ses Small Capacitors: CMOS Comparable Low Power: mw Operates from a Single V Supply kbaud Operation for R L = k, C L = pf Baud Operation for R L = k, C L = pf Rugged Bipolar Design Outputs Assume a High Impedance State When Powered Down Absolutely No Latchup Available in Narrow SO Package APPLICATI O S Portable Computers Battery-Powered Systems Power Supply Generator Terminals Modems DESCRIPTIO The LT is a dual RS driver/receiver pair with integral charge pump to generate RS voltage levels from a single V supply. The circuit features rugged bipolar design to provide operating fault tolerance and ESD protection unmatched by competing CMOS designs. sing only external capacitors, the circuit consumes only mw of power and can operate to kbaud even while driving heavy capacitive loads. New ESD structures on the chip allow the LT to survive multiple ±kv strikes, eliminating the need for costly TransZorbs on the RS line pins. Driver outputs are protected from overload and can be shorted to ground or up to ±V without damage. During power-off conditions, driver and receiver outputs are in a high impedance state, allowing line sharing., LTC and LT are registered trademarks of Linear Technology Corporation. TransZorb is a registered trademark of General Instruments, GSI TYPICAL APPLICATI O LT V INPT V OT V OT DRIVER OTPT R L = k C L = pf Output Waveforms LOGIC INPTS LOGIC OTPTS S RS OTPT RS OTPT RS INPT RS INPT RECEIVER ROTPT C L = pf INPT LT TA LT TA
LT ABSOLTE AXI RATI GS (Note ) W W W Supply Voltage (V CC )... V V....V V....V Input Voltage Driver... V to V Receiver... V to V Output Voltage Driver... (V V) to (V V) Receiver....V to (V CC.V) Short-Circuit Duration V... sec V... sec Driver Output... Indefinite Receiver Output... Indefinite Operating Temperature Range LTC... C to C LTI... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR C V C C C V TR OT REC IN N PACKAGE -LEAD PLASTIC DIP TOP VIEW V CC GND TR OT REC IN REC OT TR IN TR IN REC OT S PACKAGE -LEAD PLASTIC SOIC T JMAX = C, θ JA = C/ W, θ JC = C/W (N) T JMAX = C, θ JA = C/ W, θ JC = C/W (S) Consult factory for Military grade parts. W ATIO ORDER PART NMBER LTCN LTCS LTIS ELECTRICAL CHARACTERISTICS (Note ) PARAMETER CONDITIONS MIN TYP MAX NITS Power Supply Generator V Output. V V Output. V Supply Current (V CC ) (Note ), T A = C ma ma Supply Rise Time C = C = C = C =. ms Oscillator Frequency khz Driver Output Voltage Swing Load = k to GND Positive.. V Negative.. V Logic Input Voltage Level Input Low Level (V OT = High).. V Input High Level (V OT = Low).. V Logic Input Current.V V IN.V µa Output Short-Circuit Current V OT = V ma Output Leakage Current Power Off V OT = ±V µa Data Rate R L = k, C L = pf kbaud R L = k, C L = pf kbaud Slew Rate R L = k, C L = pf V/µs R L = k, C L = pf V/µs Propagation Delay Output Transition t HL High to Low (Note ).. µs Output Transition t LH Low to High.. µs
ELECTRICAL CHARACTERISTICS (Note ) LT PARAMETER CONDITIONS MIN TYP MAX NITS Receiver Input Voltage Thresholds Input Low Threshold (V OT = High).. V Input High Threshold (V OT = Low).. V Hysteresis... V Input Resistance (Note ) kω Output Voltage Output Low, I OT =.ma.. V Output High, I OT = µa (V CC = V).. V Output Short-Circuit Current Sinking Current, V OT = V CC ma Sourcing Current, V OT = V ma Propagation Delay Output Transition t HL High-to-Low (Note ) ns Output Transition t LH Low-to-High ns The denotes specifications which apply over the full operating temperature range. Note : Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : Testing done at V CC = V, unless otherwise specified. Note : Supply current is measured as the average over several charge pump cycles. C = C = C = C =. All outputs are open, with all driver inputs tied high. Note : For driver delay measurements, R L = k and C L = pf. Trigger points are set between the driver s input logic threshold and the output transition to the zero crossing (t HL =.V to V and t LH =.V to V). Note : For receiver delay measurements, C L = pf. Trigger points are set between the receiver s input logic threshold and the output transition to standard TTL/CMOS logic threshold (t HL =.V to.v and t LH =.V to.v). Note : Tested at V IN = ±V. TYPICAL PERFOR A CE CHARACTERISTICS W PEAK OTPT VOLTAGE (V)......... Driver Maximum Output Voltage vs Load Capacitance DRIVERS LOADED k BAD k BAD k BAD LOAD CAPACITANCE (nf) PEAK OTPT VOLTAGE (V)....... Driver Minimum Output Voltage vs Load Capacitance DRIVERS LOADED k BAD k BAD k BAD LOAD CAPACITANCE (nf) DRIVER OTPT VOLTAGE (V) Driver Output Voltage R L = k V CC =.V V CC = V V CC =.V OTPT HIGH OTPT LOW V CC =.V V CC = V V CC =.V TEMPERATRE ( C) LT TPC LT TPC LT TPC
LT TYPICAL PERFOR A CE CHARACTERISTICS W THRESHOLD VOLTAGE (V).......... Receiver Input Threshold INPT HIGH INPT LOW SPPLY CRRENT (ma) Supply Current vs Data Rate DRIVERS ACTIVE R L = k C L = pf LEAKAGE CRRENT (µa) Driver Leakage in Shutdown V OT = V V OT = V. TEMPERATRE ( C) DATA RATE (kbaud). TEMPERATRE ( C) LT TPC LT TPC LT TPC Receiver Short-Circuit Current Driver Short-Circuit Current Slew Rate vs Load Capacitance SHORT-CIRCIT CRRENT (ma) ISC ISC SHORT-CIRCIT CRRENT (ma) ISC ISC SLEW RATE (V/µs) SLEW RATE SLEW RATE TEMPERATRE ( C) TEMPERATRE ( C) CAPACITANCE (nf) LTLT TPC LT TPC LT TPC V Compliance Curve V Compliance Curve V (µf) V () V (µf) V (V) V (V) V () LOAD CRRENT (ma) LOAD CRRENT (ma) LT TPC LT TPC
ESD PROTECTIO PI F CTIO S C, C, C, C (Pins,,, ): Commutating Capacitor Inputs. These pins require two external capacitors C : one from C to C and another from C to C. C may be deleted if a separate V supply is available and connected to pin C. V (Pin ): Positive Supply Output (RS Drivers). V V CC.V. This pin requires an external charge storage capacitor C, tied to ground or V CC. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V and V pins may be paralleled into common capacitors. V (Pin ): Negative Supply Output (RS Drivers). V (V CC V). This pin requires an external charge storage capacitor C. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V and V pins may be paralleled into common capacitors. TR OT, TR OT (Pin, ): Driver Outputs at RS Voltage Levels. Driver output swing meets RS levels for loads up to k. Slew rates are controlled for lightly loaded lines. Output current capability is sufficient for load conditions up to pf. Outputs are in a high impedance state when V CC = V. Outputs are fully shortcircuit protected from V V to V V. Applying LT higher voltages will not damage the device if the overdrive is moderately current limited. Short circuits on one output can load the power supply generator and may disrupt the signal levels of the other outputs. The driver outputs are protected against ESD to ±kv for human body model discharges. REC IN, REC IN (Pins, ): Receiver Inputs. These pins accept RS level signals (±V) into a protected terminating resistor. The receiver inputs are protected against ESD to ±kv for human body model discharges. Each receiver provides.v of hysteresis for noise immunity. Open receiver inputs assume a logic low state. REC OT, REC OT (Pins, ): Receiver Outputs with TTL/CMOS Voltage Levels. Outputs are fully short-circuit protected to ground or V CC with the power ON or OFF. TR IN, TR IN (Pins, ): RS Driver Input Pins. These inputs are TTL/CMOS compatible. Inputs should not be allowed to float. Tie unused inputs to V CC. GND (Pin ): Ground Pin. V CC (Pin ): V Input Supply Pin. This pin should be decoupled with a ceramic capacitor close to the package pin. Insufficient supply bypassing can result in low output drive levels and erratic charge pump operation. The RS line inputs of the LT have on-chip protection from ESD transients up to ±kv. The protection structures act to divert the static discharge safely to system ground. In order for the ESD protection to function effectively, the power supply and ground pins of the circuit must be connected to ground through low impedances. The power supply decoupling capacitors and charge pump storage capacitors provide this low impedance in normal application of the circuit. The only constraint is that low ESR capacitors must be used for bypassing and charge storage. ESD testing must be done with pins V CC, V, V and GND shorted to ground or connected with low ESR capacitors. ESD Test Circuit C V V CC V LT GND C TR OT RS LINE PINS C REC IN PROTECTED TO ±kv C REC OT V TR IN RS LINE PINS PROTECTED TO ±kv TR OT REC IN TR IN REC OT LT ESD TC
LT TYPICAL APPLICATIO S Isolated RS Driver/Receiver V IN = V ±% FROM SYSTEM Ω CTX- : L µh N Ω µf LT- µf V ±% µf I LIM V IN SW LT FB GND SW N.V k k µf ISOLATOR OTPT (DATA TO SYSTEM) V OT V CC OS IN LTC GND GND LT RS V CC ISOLATOR INPT (DATA FROM SYSTEM) V IN V CC IN OS LTC GND GND R X D X RS INPT RS OTPT ISOLATION BARRIER FLOATING GROND SYSTEM GROND LT TA Data Transmission Across Isolation Barrier ISOLATOR INPT RS INPT RS OTPT ISOLATOR OTPT TA TA
LT PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead PDIP (Narrow.) (LTC DWG # --).* (.) MAX. ±.* (. ±.).. (..). ±. (. ±.).. (..).. (..)...... ( ). (.) MIN. (.) MIN. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) TYP. ±. (. ±.) N S Package -Lead Plastic Small Outline (Narrow.) (LTC DWG # --)..* (..).. (..)..** (..).. (..).. (..) TYP.. (..).. (..).... * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..). (.) TYP S Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
LT TYPICAL APPLICATIO S Operation sing V and V Power Supplies V INPT LT V INPT V OT LOGIC INPTS RS OTPT RS OTPT LOGIC OTPTS S RS INPT RS INPT LT TA Sharing Capacitors V V CC TTL INPT LT V V RS OTPT V V CC TTL INPT LT V V RS OTPT TTL INPT RS OTPT TTL INPT RS OTPT TTL OTPT RS INPT TTL OTPT RS INPT TTL OTPT RS INPT TTL OTPT RS INPT C C C C C C C C LT TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTA/LTA V -Driver/-Receiver RS Transceivers Pin Compatible with LTA/LTA LTA/LTA V -Driver/-Receiver RS Transceivers Pin Compatible with LTA/LTA LT/LT V -Driver/-Receiver RS Transceivers IEC -- Level Compliance Linear Technology Corporation McCarthy Blvd., Milpitas, CA - () - FAX: () - www.linear-tech.com fa, sn LT/TP REV A K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION