http://www.sprnger.com/0-387-25742-x
Chapter 2 FAULT AND FAULT MODELLING 2.1 Introducton The rse of system-on-chp (SOC) technology has dramatcally boosted the mportance of analog crcutry, movng t more nto manstream ntegrated crcut (IC) desgn. Analog and dgtal crcuts are now beng ntegrated nto a SOC. Advances n deep sub-mcron technologes has fuelled the explosve ncrease n IC complexty. The smaller sze makes these chps more senstve to fabrcaton varatons and tolerance accumulatons. Thus there s a growng demand for fault tolerance, whch can be acheved not only by mprovng the relablty of the functonal unts, but also by an effcent fault detecton, solaton and accommodaton concept. Consequently, testng and fault dagnoss s becomng one of the major cost factors n the overall IC manufacturng expenses. It has been recognsed as a valuable means to (a) check system nstallaton and confguraton after mantenance actvtes, (b) ensure correct system functonalty at start-up, and (c) avod maskng and accumulaton of errors durng operaton. Avalablty of a system (or of redundant system components) can be sgnfcantly ncreased, f testng s employed to allow rapd dagnoss after a falure. In the context of fault dagnoss, a fault s understood as any knd of malfuncton n the system that leads to an unacceptable anomaly n the overall system performance. A fault n a system can be very costly n terms of loss of producton, equpment damage and economc setback. Faults are developed n a system due to normal wear and tear, desgn or manufacturng defects or mproper operaton leadng to stress beyond endurable lmts. In many cases degradaton n the performance of the system s sustaned for some duraton before t actually fals. In many other cases a system
24 fault dagnoss of analog ntegrated crcuts contnues to operate wth a faled component resultng n degraded performance. The varety of fault modes that can occur may be classfed as: 1. Abrupt (sudden) faults,.e., step-lke changes. 2. Incpent (slowly developng) faults, e.g., drft or bas. Typcally, abrupt faults play an mportant role n safety-crtcal applcatons (e.g. n power plants, transportaton systems and drug manufacturng systems, etc,), where a system falure have to be detected early enough so that dsastrous consequences arsng due to falures can be avoded by early system reconfguraton. On the other hand, ncpent faults are of major relevance n connecton wth mantenance problems where early detecton of worn out components s requred. In ths case faults are typcally small and not as easy to detect, but the detecton tme s of mnor mportance and may therefore be large. In the study of fault dagnoss the constructon of a fault dctonary usng fault smulaton technques are wdely used for choosng the test strategy. Some methodologes use schematcs as the startng pont to generate fault lsts n fault smulaton. For example, when a fault lst s generated, every component s ether shorted, or opened, shorted to power, shorted to ground n sngle fault stuaton, or a large number of dfferent fault combnatons are consdered n multple fault cases. The dsadvantage of dong so s that t neglects the physcal layout nformaton of the crcutry and hence t could generate some unrealstc faults n the lsts or a prohbtvely large fault lst. Therefore very often a sngle fault assumpton s made. Unfortunately such assumpton s often nvald. For nstance, a sngle cut lne across a PCB generates multple faults. One problem n schematc based fault generaton wthout layout nformaton s ts naccuracy n fault models. For example, n CMOS short crcut smulaton, a short between nodes should be a proper resstor between nodes nstead of zero resstance [1], especally n an ntegrated crcut [2][3]. Therefore, t s advantageous to study testng by relatng the system specfcatons to detals of the layout and process. It s necessary to nvestgate correlatons between fault models and physcal falures. Based on the probablty of the occurrence of physcal falures and the fault behavours caused by such falures, a realstc fault lst can be generated and the fault models can then be bult. Fantn and Morand have presented a revew on falure modes and mechansms for very large scale ntegraton (VLSI) ICs [4]. Falure mechansms for electronc components are presented brefly n the followng secton.
fault dagnoss of analog ntegrated crcuts 25 2.2 Falure modes n electronc components A falure mode s the effect by whch a falure s observed, whle a falure mechansm s the chemcal, physcal, or metallurgcal process, whch leads to component falure [5]. In electronc components, there exst dfferent falure modes such as open crcut, short crcut, degraded performance and functonal falures. Degradaton faults depend manly on varatons of certan parameters of the components used n a crcut from ts nomnal values. Ths may be due to manufacturng defects, process varatons, change n the envronment or ambent temperature and/or wear out due to agng. Functonal faults, on the other hand, are based on the fact that a crcut may contnue to functon, but some of ts performance specfcatons may le outsde ther acceptable ranges. For example, an amplfer may contnue to amplfy wth a very low gan. Broln [6] has summarsed the relatve occurrence of falure modes n some electronc components, whch are shown n Table 2-I. Table 2-I shows that most physcal falures are open and short faults, whch are comparatvely easer to detect than degradaton and functonal faults. For example, an amplfer may contnue to amplfy wth a very low gan. In prnted crcut boards (PCBs), approxmately 75% of faults occur at assembly, only 20% are component faults, and 5% are PCB faults [7]. An mportant applcaton of Table 2-I s to calculate test coverage and yeld estmaton. For nstance, f the open fault for a fxed resstor can be detected, 90% test coverage for that resstor s estmated. Further, faults n electronc components can be classfed nto followng three groups wth respect to ther orgn [8]: 1. Electrcal stress falures: Beng an event dependent falure mechansm, electrcal stress s a contnuous source of devce defects over product lfetme. It s most often caused by mproper handlng. 2. Intrnsc falures: The group of ntrnsc falures subsumes all crystal related defects. Snce such defects depend very much on the maturty of the manufacturng process, they most often lead to yeld loss or nfant mortalty, rarely to wear-out effects (gate-oxde wear-out and wear-out due to surface charge effects or onc contamnaton have been observed). Type and manfestaton of ntrnsc falures are determned by technology: Gate-oxde defects are specfc to metaloxde semconductor (MOS) devces by ther nature, whle current gan shfts are a typcal bpolar devce defect manfestaton. Performance degradaton s a long-term effect of ntrnsc falures. 3. Extrnsc falures: Extrnsc falures comprse all defects related to nterconnecton, passvaton and packagng. They can be classfed nto three categores wth respect to the tme of defect manfestaton:
26 fault dagnoss of analog ntegrated crcuts severe process defcences resultng n easy-to-detect errors (e.g., open bondng), wear-out effects affectng long term relablty (e.g., mosture-related falures) and radaton-related errors contnuously occurrng over product lfetme. Table 2-I: Relatve occurrence offalure modes n some electronc components [6]. components short % open % degradaton % functonal % dgtal, bpolar ICs 30 30 10 30 dgtal MOS ICs 20 10 30 40 lnear ICs 30 10 10 50 bpolar transstors 70 20 10 -- feld-effect transstors 80 10 10 -- dodes, general purpose 70 30 -- -- dodes, sneer 60 30 10 -- dodes, HF 80 20 -- -- SCRs 20 20 60 -- opto-electronc devces 10 50 40 -- resstors, fxed 90 10 -- -- resstors, varable 60 20 20 -- capactors, fol 80 10 10 -- capactors, metal fol 40 60 -- -- capactors, ceramc 50 40 10 -- capactors, tantalum, dry 60 20 20 -- capactors, alumnum, wet 20 10 70 -- cols 10 30 -- 60 relays 15 15 -- 70 crystals -- 80 20 -- The probablty of wear-out defects s strongly nfluenced by the package type. An apprecable percentage of feld falures due to packagng can be traced to mosture n the package. The wdely used plastc package exhbts the worst qualty. Due to ther low power dsspaton, CMOS devces are more susceptble to corroson than other devces. The order of mportance of the falure mechansms further depends on parameters lke devce sze,
fault dagnoss of analog ntegrated crcuts 27 maturty of the technology, and extent and effectveness of the screenng appled after producton. Wth a proporton of 58% [8], electrcal stress nduced defects play a domnant role n the feld falures. A vast majorty of falure mechansms s extremely temperature dependent. Hgh temperature or temperature cyclng, lead to sgnfcant ncrease n falure rate, the same apples for hgh supply voltage also. Table 2-II gves typcal examples for each of these groups, for a detaled dscusson, please refer to [8]. Table 2-II: Global classfcaton of component falures [8]. falure group relevant parameters tme dstrbuton of falures electrcal stress handlng contnuous ntrnsc technology predomnantly nfant but also wear-out process yeld loss extrnsc packagng wear-out, rarely nfant radaton contnuous An effectve fault model s a fundamental ssue for a successful analog test and dagnoss strategy. In the followng secton, an attempt has been made to provde an outlne of analog fault modellng. 2.3 Analog fault modellng The fault lst s the set of all modelled faults and the test generated by the test process should detect all modelled faults. Realstc analog fault models can be acheved by knowng the behavour of the crcut. In general, an analog IC under test can have the followng three outcomes: 1. Catastrophc (hard) falure: The crcut s not functonng at all. 2. Unacceptable performance degradaton: In ths case, the crcut s stll functonng, but some of ts performance specfcatons le outsde ther acceptable range. Performance degradaton s usually referred to as a soft falure. 3. Acceptable performance: The crcut s functonng and all ts performance parameters are wthn ther specfcaton ranges. In ths case, the crcut s sad to be correct. From above, faults n analog ICs are generally classfed n to the followng two categores [9]: Catastrophc (hard) faults: Catastrophc faults are all those changes to the crcut that cause the crcut to fal catastrophcally. These faults nclude shorts, opens or large varatons of a desgn parameter
28 fault dagnoss of analog ntegrated crcuts lke forward beta () n bpolar juncton transstors (BJTs) and wdth and length of MOS feld effect transstors (MOSFETs). Catastrophc faults are caused by major structural deformatons or extreme out-ofrange parameters and lead to falures that manfest themselves n a completely malfunctonng crcut. Electro-mgraton and partcle contamnaton phenomena occurrng n the conductng and metallsaton layers are the major causes of opens and brdgng shorts. Parametrc (soft) faults: Parametrc faults are those changes that cause performance degradaton of the crcut. These faults are due to the process fluctuatons. These faults nvolve parameters devatons from ther nomnal value that can consequently qut ther tolerance band. Parametrc faults are due to out-of-specfcaton parameter devatons and so depend on the acceptablty band defned by tolerances of process parameters. As analog faults are contnuous n mode they can take an nfnte number of values and so, the only dfference between catastrophc and parametrc faults depend on the concept of totally malfunctonng crcut. In addton, faults consdered catastrophc at one descrpton level may become parametrc at a hgher one. Further, a good knowledge of the probablty of occurrence of all possble defects s necessary for actual fault coverage estmaton by a test methodology. From the perspectve of physcal falure mechansms, changes to a crcut comes from a wde range of sources [10] such as manufacturng defects, process varatons, crcut and envronmental parastc, changes n the envronment or ambent temperature, and desgn errors/non-robustness. Numerous technques based on the catastrophc and/or parametrc fault models wth emphass on ether stmul desgn (.e., test generaton) [11][12] [13][14][15][16][17][18][19], or response analyss (.e., sgnature analyss for dervng the acceptance regon) [20][21][22][23] has been proposed. The works n [14][17][18][19] address the test generaton problem n the frequency doman for lnear tme-nvarant (LTI) crcuts. Snusodal stmul wth specfc frequency, whch maxmses the output dfference between the faulty and fault-free crcut are selected as the nput stmul. Specfcally parametrc devaton that could possbly mask the faults s consdered n the selecton of frequency [19]. A symbol based approach for dervng the test frequency s demonstrated n [17]. Methods of test generaton n tme doman are addressed n [12][13][15][16] whch derve statc or dynamc tme doman test stmul. Elsewhere, test generaton s formulated as a lnear [15], quadratc [13] or dynamc [16] programmng problem to maxmse the output dfference. These tme doman test generaton technques usually can be appled to both lnear and non-lnear crcuts. Technques usng the
fault dagnoss of analog ntegrated crcuts 29 tolerance range of devce parameters for analog crcut fault detecton are proposed n [20][21][22]. Fault-model based technques for AMS testng of [24][25][26] ncludes DC voltage/current and pseudorandom exctaton technques. In the DC technque, the DC output voltages/currents are used as sgnatures. Modellng of analog and mxed-sgnal ICs for testng and fault dagnoss usng standard test stmul generated for dgtal ICs have been reported n [27][28][29]. In the above studes, the faults are modelled mostly as open, short, and varable component values. However, component value changes are usually sgnfcant n these falure modes. As a result, a faulty value wth a value ten tmes larger or ten tmes smaller s a reasonable assumpton n generatng the fault lst. Open and short faults are only the extreme cases of these two. Therefore, f ten tmes larger or ten tmes smaller faults can be covered, the open and short faults can be detected also. In IC models, short and open should be consdered as resstve values accordng to the technology and process [30]. The nformaton provded n the lteratures can be used for makng test decsons, creatng fault models, generatng fault lsts, and calculatng fault coverage n fault smulaton. A comprehensve structured approach for testng and fault dagnoss of AMS crcuts and systems have not yet materalsed. The basc problem wth analog IC fault dagnoss s the absence of effcent fault models [31], component tolerances and non-lneartes. It s dffcult to arrve at a general fault model lke the stuck-at models for the dgtal crcuts. As descrbed above faults n analog ICs can be classfed nto two categores: catastrophc faults or hard faults parametrc faults or soft faults Nomnal Hard faults or catastrophc faults Fault-free Soft faults or parametrc faults Fgure 2.1: Taxonomy offaults.
30 fault dagnoss of analog ntegrated crcuts Therefore the taxonomy of analog faults can be represented as shown n Fgure 2.1. There s a regon of acceptable behavour around nomnal range. Beyond ths regon, there s crcut performance that does not meet desgn specfcaton, but does not cause complete crcut falure. Fnally there are faults that render the crcut noperable. Snce both hard faults and soft faults can take on nfntely many varetes, there are nfntely many analog faults. Consequently, we must choose a subset of faults, whch wll lead to the best possble fault lst. Snce 80-to-90 percent of analog faults nvolve shorted and open resstors, capactors, dodes and transstors [6], n ths study we have chosen the fault models of varous devces as shown n Fgure 2.2. Open faults are hard faults n whch the component termnals are out of contact wth the rest of the crcut creatng a hgh resstance at the ncdence of fault n the crcut. Addton of a hgh resstance n seres (e.g., RS 1MΩ) wth the component (e.g., resstor, capactor or dode) can smulate the open faults. Short faults, on the other hand, are a short between termnals of the component (effectvely shortng out the component from the crcut). A small resstor n parallel (e.g., RP 1 Ω) wth the component can smulate ths type of fault for resstors, capactors and dodes. RS R RESISTOR CAPACITOR DIODE BIPOLAR JUNCTION TRANSISTOR MOS TRANSISTOR Fgure 2.2: Fault models of resstor, capactor, dode and transstor. The BJT can have three open faults (at the base, collector and emtter termnals) and three short faults (between base-emtter, collector-base and collector-emtter). These open and short faults are emulated n the same manner usng three seres resstors RBB, RCC and REE for the open faults and three parallel resstors RBE, RCB and RCE respectvely as shown n Fgure 2.2. In addton, the BJT has two extreme out-of-range parametrc faults for the value of beta (β). A MOSFET has fve hard faults: two stuckopen faults at the source and dran, and three stuck-short faults between
fault dagnoss of analog ntegrated crcuts 31 source-dran, dran-gate and gate-source [32]. These stuck-open faults can be emulated usng a hgh resstance RS n seres and the stuck-short faults can be emulated usng a small resstance RP between the termnals usng the fault model as shown n Fgure 2.2. Wth ths set of fault models we obtan a standard set of faults. The total number of catastrophc faults n a BJT ntegrated crcut can be N = 2 ( R + C + D) + 8B N CF (2.1) and that n a MOS ntegrated crcut can be N = 2 ( R + C + D) + 5M N CF (2.2) where R = number of resstors, C = number of capactors, D = number of dodes, B = number of BJTs, and M = number of MOSFETs. In practcal crcuts, the soft faults are the most dffcult to model and test. The frst problem n the testng of soft faults n analog ICs s to decde on what knd of crcut component devatons from nomnal should be consdered faulty. Decdng on the tolerance s a major hurdle. The enormous fault lst s rendered manageable by quantsng the possble values that a crcut under fault can take. The fault free category ncludes all the values lyng n the range N ± σ, where N s the nomnal value and σ s the standard devaton from the nomnal value. A crcut component havng any value n ths range s consdered fault-free. If t maps to some value outsde ths nomnal range, t s consdered faulty. Moreover t could be faulty ether above or below the tolerance. Whle smulatng the bpolar analog ICs for fault condtons, these soft faults can be modelled usng a reduced set of SPICE parameters lke forward and reverse, juncton capactance, transport saturaton current, forward Early voltage, forward and reverse transt tme, etc. of the devces. Smlarly, for smulatng the MOS analog ICs for fault condtons, these soft faults can be modelled usng parameters lke channel length, channel wdth, saturaton current, threshold voltage, oxde thckness, etc. of the devces. 2.4 Approxmaton modellng of analog ntegrated crcuts As descrbed later n Chapter 4, one of the mportant concepts of fault dagnoss n analog ICs s the use of model-based observer scheme. The development of approxmaton models based on the physcal nformaton and data of the analog IC under test s the foremost goal of such a fault
32 fault dagnoss of analog ntegrated crcuts dagnoss methodology. Approxmaton models that can be used for modellng of falures n any dynamcal system may be any one of the varous types of mathematcal models avalable n the lterature [33]. Some mportant types of approxmaton models are gven below: 1. Polynomals: Polynomal approxmaton s the most extensvely studed approxmaton method. The class of polynomal functons of degree n s gven by n ˆ = ˆ f n ( z; ˆ) θ : θ z = 0 : ˆ θ R, ˆ θ n 0 (2.3) Polynomals are lnearly parametersed approxmators and accordng to the well-known Weerstrass theorem [33], for any functon f C[D] and any ε > 0, there exst a polynomal p fˆ n (for n arbtrarly large) such that sup z D f ( z) p( z) ε. In the specal case of n=1, the polynomal expanson reduces to a lnear system, whch consttutes the best-developed part of system theory. 2. Ratonal functons: Another type of approxmaton method s the ratonal functon approxmaton. In ths case n ˆ θ z = fˆ 0 n m z θ ϑ ˆ θ ˆ, ( ; ˆ,ϑˆ) : :, ϑ R m (2.4) ˆ ϑ z = = 0 wth the restrcton that the zeros of the denomnator polynomal are outsde the approxmaton regon. In general, ratonal functons have greater approxmaton power than polynomal functons, n the sense that wth the same number of parameters one s able to obtan better approxmaton accuracy [33]. Ratonal functons are nonlnearly parametersed approxmators. 3. Splne functons: Splne functons are examples of pecewse polynomal approxmators [34]. The man dea behnd splne functons s the partton of the approxmaton regon nto a fnte number of sub-regons va the use of knots. In each sub-regon a polynomal of degree at most n s used, wth the addtonal requrement that the overall functon s (n-1) tmes dfferentable. The most popular type of splne functons s cubc splnes where n=3,.e., cubc polynomal peces that are joned so that the overall functon s twce dfferentable. Splne functons wth fxed knots are
fault dagnoss of analog ntegrated crcuts 33 lnearly parametersed approxmators; however, splne functons wth varable knots become nonlnearly parametersed approxmators. 4. Artfcal neural networks (ANNs): ANNs are approxmaton methods based on models of bologcal sgnal actvty [35]. Although varous ANN models have been proposed, by far the most popular s the class of mult-layer ANNs wth sgmod-type actvaton functon. In the case of a two layer ANN fˆ n n ( z; ˆ, θ ˆ,ϕˆ) ϑ ϕ : = ˆ θ σ (ϑˆ ϑ z + ˆ ϕ ) : ˆ θ, ˆ ϑ ˆ, ϕ R = 1 (2.5) where, σ ( ) s the sgmod actvaton functon. Theoretcal works by several researchers have shown that such networks can unformly approxmate any functon f C[D] to any degree of accuracy (unversal approxmaton), provded n s suffcently large, or equvalently the network has suffcently large number of neurons. Mult-layer ANNs are nonlnearly parametersed approxmators. 5. Radal-bas-functon networks: Another class of neural networks that has attracted consderable attenton s the radal-bas-functon (RBF) network model. The output of the RBF network s of the form n ˆ ( z; ˆ) θ : = ˆ θ ω ( z) : ˆ θ R = f n 1 (2.6) where, ω s the output of the th bass functon. The Gaussan 2 2 functon ω ( z) : = exp( z c / σ ), where c and σ are the th centre and wdth respectvely, s usually chosen as the bass functon. RBF networks are also capable of unversal approxmaton. In many respects, the approxmaton propertes of RBF networks are smlar to those of splne functons. For example, f the centre and wdth are kept fxed then the RBF networks are lnearly parametersed approxmators; f they are allowed to vary then RBF networks become nonlnearly parametersed approxmators. 6. Adaptve fuzzy systems: The fuzzy logc paradgm [35] provdes another type of approxmator. Fuzzy systems approxmate functons by coverng ther graphs wth fuzzy patches or fuzzy rules of the form f antecedent condtons hold, then consequent condtons hold. The approxmaton ncreases n accuracy as the fuzzy patches ncrease n number and decrease n sze. In adaptve fuzzy systems
34 fault dagnoss of analog ntegrated crcuts each fuzzy rule s weghted by adjustable parameters or weghts. Fuzzy systems offer the possblty of usng lngustc nformaton, based for example on common sense or experts knowledge, for control of systems where a mathematcal model s hard to determne. To smplfy the notatons n the above approxmaton methods, the case of sngle-varable functons (z s a scalar) are consdered. The above lst of approxmators, although not complete, ncludes many of the approxmaton methods used for modellng of dynamcal systems. The frst three of the approxmators descrbed above are based on classcal approxmaton methods whle the rest have been proposed n the context of ntellgent control. The precedng dscusson ndcates that ANNs represent one class of onlne approxmators. Investgatons comparng neural networks wth other approxmaton models are stll at a prelmnary stage; however, from a system engneerng perspectve, ANNs possess several propertes that make them approprate for approxmaton of unknown systems, n the context of fault dagnoss. Some of these propertes are: Massve parallelsm, Fault tolerance, Possblty of analog hardware mplementaton, Convenent adaptaton capabltes and Good generalsaton features. Furthermore, ANNs have receved a great deal of research nterest n the past several years and two tutoral artcles [36][37] descrbe the varous types of ANNs that are mostly used. ANNs lead to solutons of problems n pattern recognton, assocatve memory, database retreval and process fault detecton and dentfcaton even n the followng envronment: Poorly defned models Nosy nputs Nonlnear systems The choce of network archtecture s growng. Hsu et al. [38] outlnes a comparson of fve dfferent ANN archtectures and have shown that the backward error propagaton (BEP) algorthm provdes the best results for the pattern classfcaton task. Many other workers have also had success usng the BEP network [39][40][41][42][43][44][45]. These researchers and others provde suffcent confdence n the advantages of the use of ANNs n fault dagnoss of analog ICs. An overvew of the ANN s presented n Appendx A.
fault dagnoss of analog ntegrated crcuts 35 2.5 Summary Ths chapter has presented fault and fault modellng n general and that of analog IC n partcular. Secton 2.1 gave an ntroducton to the subject. The defnton of the faults has been dscussed n ths secton. Ths secton also presented the fault mechansm. Secton 2.2 dscussed the falure modes n electronc components. A clear understandng of falure modes s mportant to avod any confuson n the development of analog fault modellng. Analog fault modellng was presented n secton 2.3. Both the catastrophc and parametrc faults of BJT and MOSFET have been consdered. Ths secton also dscussed the dfferent technques of fault modellng. Fault model of resstor, capactor, dode and transstors are covered here. Secton 2.4 dscussed some of the mportant approxmaton modellng of the analog ntegrated crcuts. Before begnnng the study of the followng chapters the reader may wsh to study the appendx A that presents an overvew of the ANN. It covers model of an artfcal neuron, the actvaton functon and the structure of an ANN. A good understandng of the ANN wll provde a frm foundaton for later chapters and subject materals. Exercses 2.1. What are the dfferent types of falure possble n an electronc component? How do the layout of an ntegrated crcut and ts packages affect falure of the devce? Why does the CMOS short crcut smulaton use a resstor nstead of zero resstance? 2.2. Count the possble number of catastrophc faults for the crcut of Fg. 2.3 2.3. Show that the nterest compounded annually over a partcular number of years on a prncpal could be expressed as a polynomal of the nterest rate per annum, r. The cumulatve ncrease n the prncpal, R, could be expressed wth an r 0 component ncluded. 2.4. The followng data has to be ftted n wth a quartc polynomal where the augmented prncpal s a polynomal functon of the nterest rate: Interest rate per annum (r) 3 4 5 6 7 8 9 10 Augmented Prncpal (R) 108 113 122 126 131 136 141 146
36 fault dagnoss of analog ntegrated crcuts Some uncertanty s added to the data because of the roundng off of R. Use least squares (LS) method to get the polynomal coeffcents. Fgure 2.3: Crcut dagram for Exercse 2.2. 2.5. Could the above data be ftted by a ratonal functon (equaton 2.4 of secton 2.4) havng less number of coeffcents than those of the polynomal approxmaton? [Try LS ft agan.] 2.6. (a) Try to approxmate the functon f (x) = x 4 on the nterval [0, 1] wth only one polynomal pece. [A possble cubc splne functon s 2x 3 x 2.] (b) Agan approxmate f (x) = x 4 on [0, 1], but ths tme use two polynomal peces so that x = [0, ½, 1], that s, use cubc splnes wth multple (two) knots. Is there any mprovement n the accuracy of representaton? 2.7. Plot the functon gven n problem 2.4. Create an artfcal neural network (ANN) wth one nput layer, one output layer and a hdden layer to approxmate the above functon. Choose proper weghts for
fault dagnoss of analog ntegrated crcuts 37 the lnks and bases for the neurons usng a tranng set and back propagaton algorthm (BEP). [Use MATLAB lbrary routne for the purpose.] 2.8. Gven below are 21 nputs P and assocated target ponts T: P = ( 1, 0.1, +1) T = ( 0.9602, 0.5770, 0.0729, 0.3771, +0.6405, +0.6600, +0.4609, +0.1336, 0.2013, 0.4344, 0.5000, 0. 3930, 0.1647, +0.0988, +0.3072, +0.3960, +0.3449, +0.1816. 0.0312, 0.2189, 0.3201) Defne a sutable radal bass functon (RBF) whch could be used to ft the above target ponts. Now create a radal bass network whch wll approxmate the functon defned by P and T. 2.9. Try fttng n lngustc varables to descrbe the data gven n problems 2.6 and 2.8 and defne correspondng rule bases to explan thebehavour of thedata. References [1] H. Walker and S.W. Drector, VLASIC: a catastrophc fault yeld smulator for ntegrated crcuts, IEEE Transacton on Computer-Aded Desgn of Integrated Crcuts and Systems, Vol. CAD-5, pp. 541-556, October 1986. [2] R.J.A. Harvey, A.M.D. Rchardson, E.M.F.G. Bruls and K. Baker, Analogue fault smulaton based on layout dependent fault models, Proceedngs, 1994 IEEE Internatonal Test Conference, pp. 641-649, October 1994. [3] T. Olbrch, J. Perez, I.A. Grout, A.M.D. Rchardson and C. Ferrer, Defect-orented vs schematc-level based fault smulaton for mxed-sgnal ICs, Proceedngs, 1996 IEEE Internatonal Test Conference, pp. 511-520, October 1996. [4] F. Fantn and C. Morand, Falure modes and mechansms for VLSI ICs - a revew, IEE Proceedngs - G, Crcuts, Devces and Systems, Vol. 132, pp. 74-81, June 1985. [5] F. Jensen, Electronc Component Relablty, John Wley & Sons Ltd., West Sussex, 1995. [6] A. Broln, Qualty and Relablty of Techncal Systems, Sprnger-Verlag, Berln, 1994. [7] F.J. Langley, Prnted Crcuts Handbook, Testng n Assembly, (Clyde F. Coombs, Jr., et al., eds.), McGraw-Hll Publshng Company, Inc., New York, pp. 21.1-21.26, [8] E. Amerasekera and F. Najm, Falure Mechansms n Semconductor Devces, 2nd edton, John Wley & Sons Ltd., West Sussex, 1997. [9] W. Maly, A.W. Strojwas and S.W. Drector, VLSI yeld predcton and estmaton: A unfed framework, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems, Vol. CAD-5, pp. 114-130, January 1986. [10] S.W. Drector, W. Maly and A.W. Strojwas, VLSI Desgn for Manufacturng: Yeld Enhancement, Kluwer Academc Publshers, The Netherlands, 1990. [11] P. Duhamel and J.C. Rault, Automatc test generaton technques for analog crcuts and systems: A revew, IEEE Transactons on Crcuts and Systems, Vol. CAS-26, pp. 441-440, July 1979.
38 fault dagnoss of analog ntegrated crcuts [12] M.J. Marlett and J.A. Abraham, DC_ITAP - an teratve analog crcut test generaton program for generatng DC sngle pattern test, Proceedngs, 1988 IEEE Internatonal Test Conference, pp. 839-844, October 1988. [13] S.J. Tas, Test vector generaton for lnear analog devces, Proceedngs, 1990 IEEE Internatonal Test Conference, pp. 592-597, October 1990. [14] N. Nag, A. Chatterjee, A. Balvada and J.A. Abraham, Fault-based automatc test generator for lnear analog crcuts, Dgest of Papers, IEEE/ACM Internatonal Conference on Computer-Aded Desgn (ICCAD-93), pp. 88-91, November 1993. [15] G. Devarayanadurg and M. Soma, Analytcal fault modelng and statc test generaton for analog crcuts, Dgest of Papers, IEEE/ACM Internatonal Conference on Computer-Aded Desgn (ICCAD-94), pp. 44-47, November 1994. [16] G. Devarayanadurg and M. Soma, Dynamc test sgnal desgn for analog ntegrated crcuts, Dgest of Papers, IEEE/ACM Internatonal Conference on Computer-Aded Desgn (ICCAD-95), pp. 627-630, November 1995. [17] W. Mao, Y. Lu, R.K. Gulat and R. Dandapan, Test generaton for lnear analog crcuts, Proceedngs, IEEE 1995 Custom Integrated Crcuts Conference, pp. 521-524, May 1995. [18] S. Mr, M. Lubaszewsk and B. Courtos, Fault-based ATPG for lnear analog crcuts wth mnmal sze multfrequency test sets, Journal of Electronc Testng: Theory and Applcaton, Vol. 9, pp. 42-57, August/October 1996. [19] A. Abderrahman, E. Cerny and B. Kamnska, Optmzaton-based multfrequency test generaton for analog crcuts, Journal of Electronc Testng: Theory and Applcatons, Vol. 9, pp. 59-73, August/October 1996. [20] L. Mlor and V. Vsvanathan, Detecton of catastrophc faults n analog ntegrated crcuts, IEEE Transactons on Computer Aded Desgn of Integrated Crcuts and Systems, Vol. 8, pp. 114-130, February 1989. [21] B.R. Epsten, M. Czgler and S.R. Mller, Fault detecton and classfcaton n lnear ntegrated crcuts: an applcaton of dscrmnaton analyss and hypothess testng, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems, Vol. 12, pp. 103-113, January 1993. [22] Z. Wang, G. Gelen and W. Sansen, Testng of analog crcuts based on power supply current montorng and dscrmnaton analyss, Proceedngs, 3rd Asan Test Symposum (ATS 94), pp. 126-131, November 1994. [23] J. Arguelles and S. Bracho, Sgnature analyss for fault detecton of mxed-sgnal ICs based on dynamc power-supply current, Journal of Electronc Testng: Theory and Applcaton, Vol. 9, pp. 89-107, August/October 1996. [24] C-Y. Pan, K-T. Cheng and S. Gupta, A comprehensve fault macro-model for Opamps, Dgest of Papers, IEEE/ACM Internatonal Conference on Computer- Aded Desgn (ICCAD-94), pp. 344-348, November 1994. [25] C-Y. Pan and K-T. Cheng, Pseudo-random testng and sgnature analyss for mxedsgnal crcuts, Dgest of Papers, IEEE/ACM Internatonal Conference on Computer- Aded Desgn (ICCAD-95), pp. 102-107, November 1995. [26] C-Y. Pan, K-T. Cheng and S. Gupta, Fault macro-modelng and a test strategy for Opamps, Journal of Electronc Testng: Theory and Applcaton, Vol. 9, pp. 225-235, December 1996. [27] M. Can, Modelng analog chps as f they are dgtal, Proceedngs, 2000 IEEE Autotestcon (IEEE Systems Readness Technology Conference), pp. 197-204, September 2000.
fault dagnoss of analog ntegrated crcuts 39 [28] D.S.S. Bello, R. Tangelder and H. Kerkhoff, Modelng a verfcaton test system for mxed-sgnal crcuts, IEEE Desgn & Test of Computers, Vol. 18, pp. 63-71, January-February 2001. [29] G. Chorbol and C. Morand, ADC modelng and testng, Proceedngs, 18th IEEE Instrumentaton and Measurement Technology Conference (IMTC 2001), Vol. 3, pp. 1992-1999, May 2001. [30] M. Sachdev, A realstc defect orented testablty methodology for analog crcuts, Journal of Electronc Testng: Theory and Applcatons, Vol. 6, pp. 265-276, June 1995. [31] N. Nag and J.A. Abraham, Herarchcal fault modelng for analog and mxed-sgnal crcuts, Dgest of Papers, 1992 IEEE VLSI Test Symposum (10 th Annversary, Desgn, Test and Applcaton: ASICs and System-on-a-Chp), pp. 96-101, Aprl 1992. [32] J. Galay, Y. Crouzet and M. Vergnault, Physcal versus logcal fault models MOS LSI crcuts: Impact on ther testablty, IEEE Transactons on Computers, Vol. C- 29, pp. 527-531, June 1980. [33] M.J.D. Powell, Approxmaton Theory and Methods, Cambrdge Unversty Press, Cambrdge, 1981. [34] L.L. Schumaker, Splne Functons: Basc Theory, John Wley & Sons, Inc., New York, 1981. [35] B. Kosko, Neural Networks and Fuzzy Systems: A Dynamcal Systems Approach to Machne Intellgence, Prentce-Hall, Inc., New Jersey, 1991. [36] R.P. Lppmann, An ntroducton to computng wth neural networks, IEEE ASSP Magazne, Vol. 4, pp. 4-22, Aprl 1987. [37] D.R. Hush and B.G. Horne, Progress n supervsed neural networks - what s new snce Lppmann, IEEE Sgnal Processng Magazne, Vol. 10, pp. 8-39, January 1993. [38] S-Y. Hsu, T. Masters, M. Olson, M. Tenoro and T. Grogan, Comparatve analyss of fve neural network models, Remote Sensng Revews, Vol. 6, pp. 319-329, January 1992. [39] M.S. Dawson and A.K. Fung, Neural networks and ther applcatons to parameter retreval and classfcaton, IEEE Geoscence and Remote Sensng Socety Newsletter, pp. 6-14, September 1993. [40] S. Nadu, E. Zaffou and T.J. McAvoy, Use of neural networks for sensor falure detecton n a control system, IEEE Control Systems Magazne, Vol. 10, pp. 49-55, Aprl 1990. [41] T. Sorsa and H.N. Kovo, Applcaton of artfcal neural networks n process fault dagnoss, Automatca, Vol. 29, pp. 843-849, July 1993. [42] B.J. Kagle, J.H. Murphy, L.J. Koos and J.R. Reeder, Mult-fault dagnoss of electronc crcut boards usng neural networks, Proceedngs, 3rd Internatonal Jont Conference on Neural Networks (IJCNN 90), Vol. 2, pp. 197-202, June 1990. [43] W. Wtanen, Sgnature analyss: a general neural network applcaton n process montorng, Presented at the SME Conference on Neural Network Applcatons for Manufacturng Product/Process Control, Aprl 1991. [44] R. Spna and S.J. Upadhyaya, Lnear crcut fault dagnoss usng neuromorphc analyzers, IEEE Transactons on Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, Vol. 44, pp. 188-196, March 1997. [45] Alok Barua, Prthvraj Kabsatpathy and Satyabroto Snha, A method to dagnose faults n analog ntegrated crcuts usng artfcal neural networks wth pseudorandom nose as stmulus, n Proceedngs of 10 th IEEE Internatonal Conference on Electroncs, Crcuts and Systems, Sharjah, U. A. E., December 14-17, 2003, pp. 356-359.