How is a PCB made? What determines impedance? John Steinar Johnsen ( Josse ) Sept 2009

Vi kan se hvor Bugatti har hentet inspirasjon fra Denne forsøkte å stikke av, men jeg hang meg på. JossePhoto

Manufacturing Processes for a Multi-layer PCB The following presentation covers the main processes during the production of a multi-layer PCB. Tracks under solder mask Via hole The diagrams which follow represent a section through a 6 layer PCB, as indicated in red. SMD Pad Section through PCB

Typical Layer Construction - 6 Layer PCB Copper Laminate Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) Layer build / stackup is one of the most important aspects of controlled impedance Many combinations of material thickness and copper weights can be used. PCB Fabricators manufacturing techniques vary

Inner Layer Processing Material Selection Copper Laminate (Dielectric) Layer 2 (Inner) Layer 3 (Inner) Core Selecting inner layer Core materials is very important when using embedded microstrip and offset stripline structures Inner layer Core materials are usually processed as Layer pairs

Laminating and Imaging of Internal Layers UV sensitive film is laminated over top and bottom surfaces of the Core Areas of the Core where no copper is required are left exposed Layer 2 (Inner) Core Does not effect impedance Layer 3 (Inner) The inner layer artwork is placed over the UV sensitive film and the film is exposed. Film is developed and the area where no copper is required is left exposed.

Etch Process - Remove Exposed Copper Copper Removed Layer 2 (Inner) Layer 3 (Inner) Core The etch process produces an etch back or undercut of the tracks. This can be specified by the W 1 / W 2 parameters This means that tracks will end up approximately 0.025 mm (0.001 ) thinner than the original design.

Remove Laminating Film Layer 2 (Inner) Core Does not effect impedance Layer 3 (Inner)

Completed Inner Layer Core All inner layer Core materials are processed as Layer Pairs prior to Bonding At this stage the Cores are inspected visually (AOI) and defective Cores rejected Sometimes a surface treatment is applied to the Cores to aid with the Bonding process Layer 2 (Inner) Core Does not effect impedance Layer 3 (Inner) The previous process is repeated on ALL innerlayers prior to final bonding.

Layer stackup Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) During the Bonding process press temperature and pressure have a great influence on substrate heights, which greatly affects impedance. It is important to use the Finished Post-Processed height when calculating Impedance

Layer stackup Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) During the Bonding process, press temperature and pressure have a great influence on substrate heights, which greatly affects impedance. It is important to use the Finished Post-Processed height when calculating Impedance

The press Cycle 1 -Resin melt and flow 2 -Resin cure 3 -Cool down

Bonding Heat Layer 1 (Outer) 1 -Resin melt and flow Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) Layer 1 (Outer) Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) During the Bonding process, press temperature and pressure have a great influence on substrate heights, which greatly affects impedance. It is important to use the Finished Post-Processed height when calculating Impedance

Bonding Multilayer Press Layer 1 (Outer) 2 -Resin cure Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) During the Bonding process, press temperature and pressure have a great influence on substrate heights, which greatly affects impedance. It is important to use the Finished Post-Processed height when calculating Impedance

3 -Cool down Bonding Multilayer Press Layer 2 (Inner) Layer 3 (Inner) Layer 4 (Inner) Layer 5 (Inner) Layer 6 (Outer) During the Bonding process, press temperature and pressure have a great influence on substrate heights, which greatly affects impedance. It is important to use the Finished Post-Processed height when calculating Impedance

Bonding Multilayer Press After Bonding, the thickness of the pressed laminat is controlled. If the thickness is not as expected, further process is stopped. Photo Robert Bürkle GmbH www.buerkle-gmbh.de

Drilling of Bonded Panel Copper Laminate Drilled Hole Layer 1 Layer 2 Layer 3 Layer 4 Drilling itself does not effect impedance Layer 5 Layer 6

Electroless Copper Process Addition of Copper to all Exposed Surfaces Copper Drilled Hole Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Electroless copper effects copper thickness on outer layers (T 1 ) Sometimes other solutions are used containing carbon, etc. Layer 6

Laminating and Imaging of External Layers UV sensitive film is laminated over top and bottom surfaces of PCB It is then exposed and developed, leaving an exposed image of the PCB pattern Layer 1 Layer 2 Layer 3 Does not effect impedance Layer 4 Layer 5 Layer 6 Copper

Electro-plating Process 1 Additional Copper to all Exposed Surfaces Laminated Film Plate Additional Copper Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 Electro-plating increases the copper thickness on outer layers (T 1 ) There will always be variations in the amount of copper added. This finished copper thickness should be used in structure calculations

Electro-plating Process 2 Add Tin over Exposed Copper Areas Laminated Film Additional Copper Tin Plating Layer 1 Layer 2 Layer 3 Does not effect impedance Layer 4 Layer 5 Layer 6

Electro-plating Process 3 Remove Laminated Film Laminated Film Removed Tin Plating Layer 1 Layer 2 Layer 3 Does not effect impedance Layer 4 Layer 5 Layer 6

Etch Process - Remove Exposed Copper Copper Removed Tin Plating Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Layer 6 The etch process produces an etch back or undercut of the tracks. This can be specified by the W 1 / W 2 parameters This means that tracks will end up approximately 0.025 mm (0.001 ) thinner than the original design.

Tin Strip - Remove Tin Plating Tin Plating Removed Layer 1 Layer 2 Layer 3 The removal of tin will slightly reduce the copper thickness (T 1 ) on the outer layers Layer 4 Layer 5 Layer 6

PCB is now complete except for surface finishes and panel routing Tracks Via Hole SMD Pad Layer 1 Layer 6 Tracks

Solder Mask Application - Curtain Coated Method Layer 1 Apply Liquid Photo-Imageable Resist, then dry Layer 6 Some PCB fabricators chose to check the impedance before the solder mask is added Structures can be checked in Normal and Coated mode Thickness of solder mask should be specified using C 1 and C 2

Solder Mask Application Image, Develop and Cure Layer 1 UV Image, Develop and Cure Does not effect impedance Layer 6

Surface Finish Process Layer 1 Apply Solder to Exposed Copper Areas Layer 6 Surface Finish (Tin / Lead / Gold / Silver) is usually only added to pads If board has no solder mask the thickness of finish should be added to T 1.

Component Notation SCL2 9624 Does not effect impedance

Routing (includes second stage drilling) Controlled Impedance coupons are routed from the panel Good controls are necessary to ensure that coupons can be matched to manufacturing panels

Process finished PCB and coupons for testing Coupons It is good practice to place TDR coupons in the X and Y axis of the manufacturing panel to ascertain any process variations due to spray patterns when using horizontal conveyorised equipment.

Process finished PCB and coupon for testing Controlled Impedance coupons are routed from the panel Controls are necessary to ensure that coupons can be matched to manufacturing panels this should be performed on trial panels prior to production ramp up.

Why as a designer do you need to discuss your design with your PCB fabricator? PCB manufacture is a process, it uses materials which are not ideal FR4 for example is a glass resin mix made of two substances with differing electrical properties. ( Er 4.2 ) Glass Er 6 Resin Er 3 (FR4) Resin Er < 3 (High performance laminates) PCB Manufacturers need to make small adjustments to designs to maximise yields

Why as a designer do you need to discuss your design with your PCB fabricator? Process varies from one fabricator to another. Press pressures temperatures may vary Supplier variations Prepreg and core may vary from one supplier to another.

DESIGN RULES Layer stack-up (Balanced build): In order to review for the balanced build, consider an imaginary line in the middle of the board. This will divide the board into upper and lower half. The copper layers in the top half of the board should match with the bottom half of the circuit board. The layer to layer spacing in the top half of the board should match with the bottom half of the board. The material used in the upper and lower half of the board should be the same to avoid warpage. The stack-up for hybrid circuits should be reviewed by design to design basis.

4-layer Originally 4-layer boards were constructed simply by bonding two doublesided laminates together. This method however is prone to bow and twist and, while the laminate costs are relatively cheap, processing costs are expensive and a tooling system is required for good registration at bonding. A natural follow on to this was the use of cap layers where a central core of laminate was used for the two inner layers and a single sided laminate was bonded each side of this to form the outer layers. The laminate costs of this construction are higher than the double-sided construction but the processing costs are less, and the need for tooling pins is reduced. The next stage in the evolution of 4-layer manufacture was to do away with the resin on the capping layers and to use copper foil. This meant that the core could be thicker, giving less possibility of bow and twist, and also resulted in a reduction in material cost. A further reduction in cost can be achieved by using a single ply of high resin content prepreg each side of the core. This will typically give a material cost reduction of more than 50% over the capping layer build, and a reduction of almost 20% over a typical build using two layers of prepreg on each side of the core.

The information on construction of 4-layers also holds true for 6-layer and above, a selection of possible builds for a 1.6 mm finished thickness and typical pricing is included for interest. The cost factors are for each layer type and are typical material costs only.

What to do when you need a stack up with impedance requirements: Additional information: - Final thickness 1.6mm Size: 110 x 70mm - Single ended 50 ohms, routing on L1, 2, 4, 7, 9 & 10-100 ohms differential routing on lay L4 and 7. - Prefered min track width is 0.127mm. Your Manufacturer will supply you a build.

What to do when you need a stack up with impedance requirements: (Cont d) Feed back from manufacturer should be: - Complete stack up, BOM. - Track width to use on the impedance traces - Space to use between the impedance traces - Calculation result Make your critical tracks visible and easy to find - Use a dedicated D-Code for these traces

What to do when you need a stack up with impedance requirements: (Cont d) On PCBs with critical signaling, you should know what you are doing when changing materials in a defined stack up. Technical on process: Electrical: Manufacturer will handle these issues As a designer you shall be aware of differences in the content (wowen glass and resin).

Effect of variables on impedance value. We can take a simple strip-line configuration, vary one element at a time, and calculate the resulting value.

Calculating impedance in PCBs with a mix of materials is nearly impossible. Please note that coverfilm on flex areas shall stopp 1-2mm inside the rigid area. This is due to risk for delamination, See next slide.

LAYER SPECIFICATION Tickness 1L Copper foil 35,0 Total 5 (7) rigid layers And 3 flex layers FR-4 CORE No flow 500,0 65,0 Coverlay 37,5 2L Base Cu 17,5 Base PI (Polyimide Adhesive) 41,0 Bonding Sheet 25,0 Coverlay 37,5 3L Base Cu 17,5 Base PI (Polyimide Adhesive) 94,0 4L Base Cu 17,5 Coverlay 37,5 No flow 65,0 FR-4 CORE 500,0 5L Copper foil 35,0

Calculated Impedance between L1-3 Er 3,5 & 4.5 96,4 ohms

Calculated Impedance between L2-3 Er 3,5 107,4 ohms

Calculated Impedance between L3-4 Er 3,5 & 3.4 104 ohms

Polar tools to assist in layer stackup: SB200a PCB Stackup design system

Polar tools to assist in impedance prediction: Si8000m Controlled impedance design system

Thanks to PolarInstruments Ltd www.polarinstruments.com

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