Understanding Thermal Characteristic of SOT-223 Package



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Application Note Neil Nien AN044 January 2016 Understanding Thermal Characteristic of SOT-223 Package Abstract For power ICs, the thermal parameters of different packages should be compliant with different applications and user s requirements, as well as determining the thermal limits of different types of packages for the spec. Thermal parameters, such as thermal resistance θja and θjc, are applied to determine thermal dissipation performance for integrated circuits. A low thermal resistance represents better thermal performance. A system that has a lower thermal resistance can dissipate more heat. This article illustrates the thermal dissipation of integrated circuits with, including thermal parameters and the internal structure. Finally, we will introduce the thermal analysis of PCB copper layout for. Table of Contents 1. General Thermal Theory of Integrated Circuits...2 2. SOT-223 Thermal Resistance Measurement...3 3. Thermal Characteristics of SOT-223 Package Structure...6 4. Conclusions... 10 AN044 2016 Richtek Technology Corporation 1

1. General Thermal Theory of Integrated Circuits The thermal resistance is a heat property of a temperature difference by an object, which is the reciprocal of thermal conductance. In the heat flow path of specific package, there exists many heat resistance, major relating with the materials of the silicon chip, molding compound, copper of lead-frame, die attachment, and so on. In Figure 1, it is a equivalent thermal resistance model of a specific package. For which, the series of resistance is defined as Eq.(1). T J T A θ JA T C θ JC Figure 1. Equivalent series of thermal resistances θja = θjc + θca (1) where, θjc is thermal resistance from junction to case. ( C/W) θca is thermal resistance from case to ambient. ( C/W) The key thermal parameter for ICs is junction temperature (TJ), which also determines stability of IC. Generally speaking, the IC datasheet will present the recommended operation temperature of junction. Since TJ cannot be measured directly, the Eq.(2) and Eq.(3) can be used for approach. In JEDEC 51 standard, the case temperature (TC) is defined at hottest position of the package surface and ambient temperature (TA) is defined for test environment temperature. TJ = TA + PD x θja (2) TJ = TC + PD x θjc (3),where θja is thermal resistance from junction to the ambient. ( C/W) θjc is thermal resistance from junction to the case. ( C/W) TJ is device junction temperature in the steady state test condition. ( C) TA is reference temperature for the ambient environment. ( C) TC is reference temperature for the case point. ( C) PD is power dissipation in the device. (W) AN044 2016 Richtek Technology Corporation 2

2. SOT-223 Thermal Resistance Measurement 2-1 Measurement Environment Following JEDEC 51-2 thermal measurement standard, θja should be measured by standardized environmental codidtion in the natural convection (air flow = 0 ft/min) at TA = 25 C. The standardized environmental codidtion is presented as Figure 2 (Dimensions in mm.). (a) Side view of the test enviromental (b) End view of the test enviromental Figure 2. Standardized environmental codidtion 2-2 Thermal Test Board Outline In JEDEC 51-3 and JEDEC 51-7 thermal measurement standard, the device under test is mounted on standard test boards, the detailed specifications of test board are presented as Figure 3 to Figure 6. For, a 4mm x 4mm copper area and 1/mm width copper wire is designed to dissipate the thermal flow. AN044 2016 Richtek Technology Corporation 3

Low effective thermal conductivity test board layout (single layer copper, refer to JEDEC 51-3) 76.2mm 1mm 14.3mm 4mm x 4mm copper 1m m 1mm 1.5mm Figure 3. Single layer top view drawing Copper 2 oz. thick FR4 1.6mm Figure 4. Single layer PCB sectional drawing AN044 2016 Richtek Technology Corporation 4

High effective thermal conductivity test board layout (Four-Layers Copper, Refer to JEDEC 51-7) 76.2mm 1mm 114.3mm 4mm x 4mm copper 1m m 1mm 1.5mm Figure 5. Four layers top view drawing Copper 2 oz. thick FR4 1 oz. thick 100% 1 oz. thick 100% 1.6mm Figure 6. Four layers PCB sectional drawing AN044 2016 Richtek Technology Corporation 5

2-3 SOT-223 Thermal resistance Base on JEDEC 51-3 and JEDEC 51-7 measurement methods, the thermal resistance of, θja and θjc, can be estimated in fixed power dissipaton and ambient temperature conditions.the mesurement result are shown as below : Power Dissipation, PD @ TA = 25 C, TJ = 125 C SOT-223 ----------------------------------------------------------------------------------------------------------------- 0.741W Package Thermal Resistance SOT-223, JA ----------------------------------------------------------------------------------------------------------- 135 C/W SOT-223, JC ----------------------------------------------------------------------------------------------------------- 15 C/W 3. Thermal Characteristics of SOT-223 Package Structure 3-1 SOT-223 Package Structure Material Characteristics Base on Eq.(2), the lower resistance means that the junction temperature will be lower in the same power dissipation and ambient temperature, and the thermal conductivity of package material will dominate the thermal resistance of package. Therefore, the utilizes high thermal conductance of lead frame to decrease the thermal resistance. The internal structure is shown in Figure 7, and the physical dimension parameters and material properties of the components used in this model are summarized in Table 1. compound die cooper gold wire die attach Pad & lead frame Figure 7. SOT-223 Top and section transparent view drawing AN044 2016 Richtek Technology Corporation 6

Table 1. Physical dimension parameters and material properties COMPONET DIMENSION Compound Size (mm) 3.5 x 6.5 x 1.8 Die Size (mm) 0.700 x 0.700 Die Thickness (mil) 12 Die Attach Thickness (mil) 0.4 Pad Size (mm) 2.50 x 3.00 Leadframe Thickness (mm) 0.305 PCB Thickness (oz.) 2 THERMAL CONDUCTIVITY (W/m C) Compound 0.847 Die 140 Die Attach 2.5 Pad & Leadframe 284 FR-4 0.3 Copper 385 Solder 51 In Figure 8, it is very specificaly difference of structure between SOT-223 and other packages. In, the die, thermal soure, is directly connected to exposed lead frame, and the major thermal flow can be conducted through the exposed lead frame to PCB trace and ambient. However, other packages only use gold wires to connect the die and the lead frame. That makes thermal resistance of SOT-223 smaller than other packages. As a result, we can use this characteristic to improve the thermal performance by designing the PCB copper layout on SOT-223 package. VIN 3 1 2 3 1 2 3 3 2 1 VOUT VIN GND 1 2 GND VOUT SOT-23-3 GND VIN (TAB) SOT-223 VOUT GND VIN (TAB) SOT-89 VOUT TO-92 connect Figure 8. s transparent view drawing AN044 2016 Richtek Technology Corporation 7

Thermal Resistance ( C/W) Understanding Thermal characteristic of 3-2 Thermal Performance Enhancerment of SOT-223 Package Beacuse of the structure of, the thermal resistance can be improved by adding copper area under the exposed lead frame. Figure 9 shows the relationship between the copper area and the thermal resistance θja. When IC is mounted to the standard footprint (16mm 2 ), the thermal resistance θja is 135 C/W, adding copper area of pad to 100mm 2 under the package reduces the θja to 107 C/W. Even further, increasing the copper area of pad to 2500mm 2 reduces the θja to 50 C/W. 160 140 120 100 80 60 40 20 0 0 400 800 1200 1600 2000 2400 2800 3200 3600 Copper Area (mm 2 ) Figure 9. SOT-223 thermal resistance θ JA. vs. PCB copper area As shown in Figure 9, we can also find the SOT-223 maximum power dissipation improvement by different copper area design at ambient temperature TA = 25 C operation. AN044 2016 Richtek Technology Corporation 8

Maximum Power Dissipation (W) Maximum Power Dissipation (W) Understanding Thermal characteristic of 2.5 2 1.5 1 0.5 0 0 400 800 1200 1600 2000 2400 2800 3200 3600 Copper Area (mm 2 ) Figure 10. Maximum power dissipation P D. vs. PCB copper area For the s, the de-rating curves in Figure 11 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. 2.4 2.2 2.0 1.8 1.6 Copper Area : 3600mm 2 900mm 2 100mm 2 16mm 2 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature ( C) Figure 11. De-rating curves for s AN044 2016 Richtek Technology Corporation 9

4. Conclusions According to the above discussion of thermal resistance and junction temperature, it was found that the thermal resistance affects dissipative heat of the system. We must follow the maximum power dissipation (power limit) and maximum junction to ambient thermal resistance requirements. If the selected package can t satisfy the requirement of thermal resistance restrictions, PCB layout needs to be improved to keep IC junction temperature below 125 C. Hence, for high power IC series products with a variety of power dissipations, adding proper copper area is essential. This article provides a general thermal concept for. Many estimations and generalizations have been used. Please refer to these information as a generally approximation of required board copper area. If customers need further thermal information on any system level design, please contact us. Next Steps Richtek Newsletter Subscribe Richtek Newsletter Richtek Technology Corporation 14F, No. 8, Tai Yuen 1 st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: 886-3-5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. AN044 2016 Richtek Technology Corporation 10