Thin Film Chip Resistors and Arrays for High Temperature Applications Up to +230 C

Transcription

1 CARTS USA 2010, New Orleans, Louisiana, March 15-18, 2010 Thin Film Chip Resistors and Arrays for High Temperature Applications Up to +230 C By Dr. Claude Flassayer Vishay Sfernice ABSTRACT With their outstanding stability, Vishay/Sfernice thin film resistors have been successfully used for decades in high-temperature applications such as drilling well equipment, aeronautics (aircraft braking systems) and, more recently, automotive electronic systems. The demands in these applications are growing more and more stringent, not only in terms of ambient temperatures up to +230 C, but also regarding density of power dissipation and reliability. In order to cope with these severe requirements, a great deal of attention must be paid to controlling the junction and solder joint temperatures. Most of this task falls to the system designers, but we, as a component supplier, need to provide them with input relevant to resistors. The aim of this paper is to provide design engineers with methods and data which are necessary to tightly control these temperatures, and therefore get the best from Vishay/Sfernice thin film bare and SMD chips. In this paper, we will discuss thermal models and comparisons between various types of PCBs and how they affect overall performance. In addition, we will explore the importance of the type of assembly method used (soldering, gluing, etc.), present a new approach for derating curves, and show stability figures versus junction temperatures. INTRODUCTION Vishay/Sfernice thin film resistors were developed in the early 80s under the trademark Ultrafilm, and have undergone constant improvement since that time. They have been widely used in high-precision and highstability applications, including stringent military equipment, working in the -55 C/+155 C temperature range. Ultrafilm resistors have also been used for decades in well logging equipment, which is exposed to higher and higher ambient temperatures up to +230 C. The Ultrafilm technology consists of: 99.5% pure alumina substrate Doped NiCr sputtered alloy Ni barrier for reflow soldering or Al pads for Al wire bonding Silicon oxy-nitride passivation Design, thermal treatments, and stabilization bakes to minimize the K parameter (as defined in this paper) and resistance drift contributors Favorite metallization for reflow: NiCr as adherence layer, thick Ni layer, and a thin Au layer. This combination of layers is efficient for HMP (high melting point alloy) Ultrafilm thin film technology offers huge advantages to designers, not only in terms of stability, but also in terms of ohmic value range amplitude, miniaturization, integration, and packaging versatility. RESISTANCE DRIFT CONTRIBUTORS Resistance drifts can be split into two categories: reversible and irreversible drifts. Reversible drifts are: Pure temperature-induced drift Equal to (R0 x TCR x (Tj - T0)) R0 = Ohmic value at + 20 C TCR = Temperature coefficient of resistance

2 Tj = Junction temperature T0 = Reference temperature, generally + 20 C Thermocouple-induced voltages (EMF) Proportional to thermal gradients and therefore strongly Tj dependent Voltage induced by noise (thermal noise) Proportional to the root square of Tj Irreversible drifts are: Assembly-process-induced drifts All the more important since HMP solder alloys are required for high-temperature applications. The solder joint temperature withstanding can be at least 40 C above Tj Long-term exposure to steady temperature and applied power (load life) Induced drifts are roughly exponentially Tj dependent Thermal gradients due to thermal shock, temperature cycling, and power on/off cycles Induced drifts depend on the extreme temperatures, and therefore on Tj Electromagnetic pulse loading The higher the Tj, the more detrimental they are Another drift contributor is the voltage induced resistance drift Equal to R0 x VCR x V VCR = Voltage coefficient of resistance V = Applied voltage For thin film resistors, VCR is about 0.01 ppm/v. For most applications where the applied voltage is just a few volts, this drift is generally insignificant. As we can see, these main drifts are highly Tj dependent. RESISTANCE DRIFT ANALYSIS As a leader in the ultra-high-precision and stability resistor marketplace, Vishay has a unique expertise in the design of resistors which minimize all these Tj-induced drifts. Therefore, these resistors can withstand higher and higher Tj without experiencing unacceptable drifts. In this field, the reference is still Foil technology, but our Ultrafilm thin film technology shows performances which are approaching that of Foil resistors. In such high-performance resistors, providing that the datasheet instructions are followed, most of the drifts mentioned above will not be significant in regard to the precision which is requested for high-temperature applications. Typically overall end of life drifts are around 1 %, compared to 0.05 % compulsory drifts in typical applications. Therefore, we can focus on: The pure temperature-induced reversible drift Equal to (R0 x TCR x (Tj - T0) The long-term exposure to steady temperature and applied power non-reversible drift (load life) With Ultrafilm resistors, the resistance versus temperature curve is flat enough to guarantee a TCR less than 15 ppm/ C in the overall temperature range of 55 C to C. Therefore, the maximum relevant reversible drift, with a 200 C Tj - T0, will be about 0.3 %. The load-life drift depends on Tj. We will thoroughly address this drift later on in this paper, but want to point out right now how important the contribution of the assembly engineers is when it comes to tightly controlling Tj, and consequently the performances of our resistors. DATA RELEVANT TO DRIFT VERSUS Tj The well-known Arrhenius relation is not applicable for high-temperature applications. It is not the focus of this paper to discuss the Arrhenius relation, and readers are kindly invited to refer to (1). Fortunately, we have learned from experience that there are alternative methods for drift evaluation. Our favorite method is based on two facts.

3 The load-life drift depends not only on Tj, but also on the way Tj is obtained. As explained later on, Tj = Ta + (Pd x Rth ja), where: Tj is the temperature of the resistive layer, or junction Ta is the ambient temperature around the PCB Pd is the power dissipation of the resistor Rth ja is the thermal resistance between the resistive layer and the ambient A given Tj can be achieved through different combinations of Ta and Pd. In theory there are as many drifts as combinations. Fortunately, this is simplified with our resistors. The total drift dr can be split into the pure induced-temperature exposure drift drpt and the electric-field-induced drift drfi, which can be expressed as drfi = KxE². K is a parameter that depends on technology and design. All our expertise consists of minimizing this K parameter. Providing that the power dissipations mentioned in our datasheets are not exceeded, drfi can be neglected, which is the first fact. Confirmation of this fact can be seen on the figure High temperature storage versus time sample #2, curve With Pd. With our thin film resistors, the drift for a given Tj is proportional to t n, where t = exposure time and n < 0.4. This means that the corresponding curves flatten quickly. This is the second fact, which is demonstrated on the following set of curves. Taking into account these two facts, the drifts at a given Tj can be predicted by way of a pure temperature exposure, at Ta = Tj, for reasonable times of at least 168 hours. This type of information is available from our manufacturing records, namely special stabilization bakes drift data. Here we are confirming these stability figures on a quality assurance test basis. The following experimental curves are relevant to two random quality assurance tests.

4 The following table shows maximum drifts Vishay/Sfernice can guarantee to our customers for various Tj. These maximum drifts are higher than the ones shown in the previous curves to provide safety margins even in the worst design cases. 185 C 200 C 215 C 230 C Maximum drift at 1000 hours 800 ppm 1500 ppm 3500 ppm 5000 ppm Maximum drift at 4000 hours 1800 ppm 3500 ppm 5000 ppm 7000 ppm Maximum drift at 8000 hours 3500 ppm 4500 ppm 6000 ppm 8000 ppm All the above figures concern absolute drifts. These temperature-induced drifts can be drastically reduced using resistor networks or arrays. On such devices, matching which is achieved through construction can lead to ratio drifts somewhere between two to five times lower than the absolute drifts. THERMAL MODEL In this paper, we are mainly dealing with two types of surface-mounted resistors: Wraparound chip resistors and arrays that can be assembled by solder reflow or conductive glues Bare chip resistors and networks intended to be wire bonded Lead Film resistor Solder Wraparound chip resistor Solder pad Tj Rth spa Ta PCB Al Pads Film resistor Solder or glue Solder pad Bare chip Tj Rth spa Ta PCB

5 In miniaturized surface-mounted components, the heat generated within the resistor is removed to the surrounding environment in the following way: Conduction from the resistive layer, or junction, through the body of the chip to the solder pads Spreading by conduction within the PCB Convection from the PCB to the ambient The components are so small compared to the PCB that heat removal from direct convection and/or radiation from the resistor body is just ignored. Below is a very simple but well recognized model where: Tj is the temperature of the resistive layer, or junction Ta is the ambient temperature around the PCB Tsp is the temperature of the solder pad, underneath the solder joint. It is almost equal to solder joint temperature Pd is the power dissipation of the resistor Rth ja is the thermal resistance between the resistive layer and the ambient is the thermal resistance between the resistive layer and the solder joint Rth spa is the thermal resistance between the solder joint and the ambient Rth spa takes into account the conduction within the PCB and the convection from the PCB to the ambient Component manufacturers can only take care of, so they are very careful regarding the choice of material, resistor pattern, and terminations. They are also keen on improving the thermal stability of their resistors. The result is that resistors can withstand higher and higher temperatures without undergoing significant drifts, and the Tj limitation is pushed away. The control of all others parameters, namely Ta, Pd, and Rth spa, are addressed by the customer s assembly designers. Designers have to take into consideration the PCB material, the thickness and the layout of the copper tracks, the cooling system, and the interaction between surrounding components. Their designs are more and more computer aided, which is the only way to face the increasingly stringent requirements of new electronic equipment in terms of miniaturization, density of power dissipation, temperature exposure, and reliability. A poor thermal management might induce: Melting of the solder joints Lack of reliability of the solder joints Loss of PCB performance, even burn out Loss of chip resistor performance, mainly due to high reversible or irreversible drifts This is why thermal management by the assembly designer is so important. THERMAL DATA In order to allow customers to use the above thermal model, we shall provide them with: for standard parts and enlarged terminations parts Experimental data relevant to chip resistors of standard sizes mounted on various PCBs. These PCBs have been chosen to be representatives of the standard and the best cases in terms of thermal resistance. This information is mainly offered to help designers who cannot calculate thermal resistance by themselves, or to help them complete their CAD approach. Meaning of the abbreviations for the data below are: A PCB 1.6-mm thick, double sided, 35-μm thick copper (minimum), and at least 50 % copper coverage on both sides PCB MCu A PCB 1.6-mm thick, double sided, 70-μm thick copper (minimum), and at least 80 % copper coverage on both sides

6 MCM Alumina substrates with thick film metallization and at least 50 % conductor coverage. It is equivalent to MCu for the thermal dissipation. Enlarged wraparounds (W/A) are equipped with bottom metallization covering their backside, with the exception of a 0.5-mm width insulation path. Standard Wraparound (W/A) Enlarged Wraparound (W/A) The following tables show the thermal resistances relevant to various combinations of components and PCBs. Soldered STD W/A Soldered Enlarged W/A Glued STD W/A Wire Bonding on Back Side Soldered Chip Resistor

7 Wire Bonding on Back Side Glued Chip Resistor DERATING CURVE Usual Datasheet Derating Curve P(W) Pn Pd 70 Ta Tc T( C) Pn = Nominal power and it is defined by benchmarking. This is almost the same for a given size whatever the supplier Tc = The highest limit of the temperature range. For example, C for the extended military range Pd gives the maximum allowed power dissipation for a Ta lower than Tc The truncation at + 70 C is historical and totally arbitrary These Pd values are not sustained by any thermal design considerations. They are very conservative and prevent design engineers from receiving the full capabilities of the resistors Meaningful Derating Curve P(W) -1/Rth Pd Ta Tc T( C)

8 This derating curve is a representation of a basic thermal model: Tc = Ta + Rth x Pd Tc = Temperature to be controlled Ta = Ambient temperature Pd = Maximum allowed power dissipation Rth = Thermal resistance between point c at temperature Tc, and the ambient It can be written: Pd = (Tc - Ta)/Rth. This thermal model gives the maximum allowed Pd for a given Ta, and a specified thermal path characterized by Rth. Such a derating curve is used to control Tj, and in this case one considers Tj as Tc, and Rth ja as Rth. It can also be used to control Tsp (temperature of the solder pad), which is also of premium importance. In this case Tsp = Tc and Rth = Rth spa. Per the table: Rth ja = 52 C/W A P 2010 on a MCu PCB Rth ja = 95 C/W A P 2010 on a scu PCB There are different ways to use this derating curve. Providing Tj max = C, the maximum power dissipation of the resistor at Ta = C will be: 0.57 W for Rthp= 52 C/W This is the best assembly 0.32 W for Rthp= 95 C/W This is the standard assembly From the same derating curve one can see that a 0.32-W power dissipation on the best assembly (Rth ja = 52 C/W) will limit Tj at C, and therefore decrease the resistance drift thoroughly. As an example, looking at the table giving the maximum drifts, and focusing on 1000 hours of time exposure, one can calculate a factor of improvement equal to 1.42 = 5000/3500.

9 Rth ja = 67 C/W A P 0603 on a MCu PCB Rth ja = 200 C/W A P 0603 on a scu PCB Providing Tj max = C, the maximum power dissipation of the resistor at Ta = C will be: W for Rthp = 67 C/W This is the best assembly 0.15 W for Rthp = 200 C/W This is the standard assembly CONCLUSION From an analysis of the temperature-induced drifts, we have pointed out some specific features of our thin film resistors that give them advantages for high-temperature applications : The reversible drift contributors others than TCR are negligible. With TCR less then 15ppm/ C, as specified, this drift can be limited at 0.3 % for ambient temperatures as high as C The irreversible drifts other than the load-life drift are negligible. This drift depends on Tj, whichever way Tj is reached; by pure ambient temperature or the sum of ambient temperature and power dissipation (Tj = Ta + Rth ja x Pd). This is valid providing some Pd limitations given in the datasheets From an analysis of actual stability data and drifts versus time for various temperatures, it is obvious that even for Tj as high as C, drifts are under control and rather predictable from manufacturing data processes. To help assembly designers keep Tj under control, we have worked out a thermal model and have shown the thermal resistance figures necessary to use this model. From there we defined and displayed some derating curves, which illustrate how good thermal management leads to load-life drift minimization. The next step will be to improve our design and process in order to push away the C Tj limitation. In parallel we will promote integrated resistive networks, like our chip arrays, for high-temperature applications. They will provide customers with an even higher level of integration and outstanding ratio drifts that are two to five times lower than absolute drifts mentioned in this paper. REFERENCES (1) High-Temperature Electronics Edited by Randall Kirshman, IEEEPress