Optiization of a Piezoelectric Crystal Driver Stage using Syste Siulations Jonny Johansson Lulel University of Technology 97 87 Lulel, Sweden Abstract Using SPICE, successful efforts have previously been ade in odeling piezoelectric devices and their functionality. In this paper the piezoelectric device is siulated together with MOS transistor odels. The design of a CMOS piezoelectric crystal driver stage is presented. Measureents on a anufactured chip verify the chosen design approach and the perforance predicted by the siulations. In the work, achieving sall silicon area while aintaining axiu possible output ultrasound pulse aplitude has been a key criterion. The driver stage has been ipleented using a.6 p CMOS process. Measureents and siulations have been perfored using PZ27 crystals without backing. Results clearly show that the perforance of a coplete syste coprising both piezoelectric and electronical devices can be predicted with good accuracy using the proposed SPICE siulation approach. I. INTRODUCTION In the area of ultrasound pulse generation, two ain routes are present in the literature. One is dealing with integrating coplete ultrasound devices including the active eleent into very sall units [ [3]. The other concerns generation of ultrasound pulses without regarding size or power consuption for the pulse generation electronics [4] [6]. However, the area of iniaturization of pulse electronics for use with standard ultrasound crystals is sparsely exploited. The work in this paper is aied at creating a design ethod for driver electronics for ASIC integration, and showing that siulations can be used to predict the perforance of a coplete syste. The design of a CMOS piezoelectric crystal driver stage is presented. SPICE odels for the piezoelectric crystal and the acoustic aterials have been used in siulations together with seiconductor odels and data fro the ASIC anufacturer, allowing optiization of the coplete syste. Measureents on a anufactured chip verify the chosen design approach and the perforance predicted by the siulations. An iportant aspect during the design work has been to iniize the consued silicon area while aintaining axiu possible ultrasonic output signal aplitude. The resulting circuit is intended to be used as a block in a coplete ixed ode ASIC for ultrasound transission, receiving and signal conditioning.. DESIGN Design environent The design and siulations have been ade using the Cadence IC 4.43 design fraework. Siulations used the Cadence Spectre siulation engine. The target process for the ipleentation of the design is a.6 p CMOS process. Ultrasound device The SPICE odels used in the work are those presented by van Deventer [7]. The ultrasound device is a PZ27 piezoceraic disc anufactured by Ferroper, Denark. The disc has a diaeter of 6 and a thickness of 487 p, giving a fundaental frequency of 4 MHz corresponding to a period tie T of 25 ns. It has been of interest to verify the design approach using different capacitive transducer loads. Thus, siulations and easureents have been carried out for one single disc and for two discs connected in parallel. In both cases, the discs are glued with cyanoacrylate glue to a 5 thick plate of PMMA. No backing aterial is used for the crystals. The axiu peaktopeak aplitude for 78363655//$. 2 IEEE 2 IEEE ULTRASONICS SYMPOSIUM 49
PMMA Air?=? L Figure : Circuit used for syste siulations. the echo received fro the PMMAair interface has been used as a easure of output pulse aplitude. According to van Deventer [7], the resistive part in the transission line odel of PMMA, odelling the acoustic attenuation, is frequency dependent. However, this is not odelled, but the paraeters are calculated at the resonance frequency of the crystal. Coparisons between easureents and siulations on the PMMA odel also clearly show that high frequency coponents in a transitted signal are attenuated ore in reality than in the siulations. To create a firstorder odel of this effect, all received signals for the siulations in this work are easured after passing a first order low pass filter with a corner frequency of 4kHz. Design considerations The driver is designed to be integrated into a larger standard CMOS design. Thus, ephasis has been ade to avoid external coponents and to keep the silicon area inial. Also, in the.6 p process used, available power supply is restricted to +5V. In achieving axiu output signal aplitude while holding these constraints, the shape of the excitation pulse applied to the crystal is decisive. As the design is focused on pulse aplitude rather than on short pulse tie, it was decided to use a single square wave excitation pulse with a pulse tie of half the crystal oscillating period tie [6]. Also, the fall and rise ties of the discharging and charging of the crystal are iportant in getting axiu aplitude fro the ultrasound pulse. The choice of large driving transistors can decrease the ties giving a higher output aplitude. On the other hand, this consues chip area and increases the load on the preceding transistor stage as well as on the crystal. Siulations of the PZ27 crystal driven by a pulse source with adjustable fall and rise ties, show that setting the ties to / of the crystal resonance 5 2 IEEE ULTRASONICS SYMPOSIUM
frequency period tie gives axiu pulse aplitude fro the crystal while avoiding to use faster transitions than necessary. The driver stage is designed to be controlled by an external pulse source. One pair of pushpull transistors is used as ain output transistors to give good control of rise and fall behaviour. In order to achieve good receiving conditions for the returned echo, the output transistors are autoatically set to high ipedance after the pulse has been sent. Circuit functionality This section gives a qualitative description of the circuit. The coplete circuit is shown in figure. All transistors are iniu length (.6 p), with widths as given in the figure. There are two ain driving transistors, N3 for discharging and P7 for charging. The starting state for the crystal is charged, being held by P3. N3 is controlled directly by the input via two inverters, while P7 is controlled by the input signal AND gated with the output crystal voltage. Thus, for P7 to be able to conduct, both the input and the output should be low. One pulse operation is described below:. The US crystal is held at V, via the P channel transistor P3. P7 and N3 are blocked. 2. When a positive pulse is applied to the input, the crystal is rapidly discharged via transistor N3. P7 is still blocked. 3. As the input voltage returns to ground, N3 blocks and P3 again starts to slowly charge the crystal. Also, P7 starts to conduct and rapidly charges the crystal up to V,>,. 4. As Vc again reaches VD,, P7 is blocked and the pulse cycle is copleted. Transistor diensioning As discussed above, the driving transistors N3 and P7 should be diensioned to achieve rise and fall ties less than T/, where T is the period tie of the crystal resonance frequency. To get a starting point for the diensioning, an approxiate forula for charging tie was used. This was derived fro approxiating the transistor characteristic at axiu gate voltage with two straight lines as shown in figure 2. VDd2 Approxiate characteristics Siulated characteristics VDD Figure 2: Approxiation of transistor characteristics. The static crystal capacitance Co is then discharged to 5% of V,, within the tie ' SA7 where lh,t is the saturation current for the transistor used. For given tf and C,,, the approxiation gives a conservative value of This is useful as it helps to account for process variations. Using the given Z,& for the chosen CMOS process, the required transistor widths for a single 6 PZ27 crystal are calculated to 3.4 for N3 and 6.8 for P7. For two parallel crystals C, is doubled giving the widths of 6.8 for N3 and 3.6 for P7. The input ipedance of the driver stage when receiving an echo signal fro the crystal is decided by transistor P3. Thus, the width of P3 is chosen to give dynaic ipedance in the conducting state that is larger than the crystal ipedance at the resonance frequency. Transistors P2, N2 and N6 are diensioned to be able to drive the gates of the driving transistors N3 and P7 with at least a rise/fall tie of T/. Here, the resulting iniu values were ultiplied by a factor of 5 to iprove the balance in the inverter chain and reduce switching losses for lower loads than the target crystal [8]. The size of transistor P6 is ade sall in order to prolong the turn off tie for P7 so that the charging of C, will be fully copleted before P7 is turned off. The inverter P/N and the NAND gate P4/P5/N4/N5 are diensioned with iniu size transistors, having the P channel devices 2 ties the N channel devices to achieve balanced perforance. "DS 2 IEEE ULTRASONICS SYMPOSIUM 5
.s.8.6 % g.4. I 2.2 I 2 3 6 8 N3 transistor width I Figure 3: Siulation using ideal coponents showing relative echo aplitude vs. transistor width. s.2.8 $.6 5.4. * 2.2...,...... Dual crystals lo N3 transistor width / Figure 4: Siulation using ideal coponents showing relative echo aplitude vs. transistor width.. SIMULATIONS Ideal driver odel As a starting point, siulations were ade on one driver stage where the widths of the driving transistors N3 and P7 were varied. The ratio P7/N3 was kept constant at 2 to keep balanced perforance. Siulations were ade using typical transistor perforance for the chosen process, and no internal or external parasitics were included at this tie. Results for single and dual crystals are shown in figures 3 and 4. The aplitudes on the yaxis are noralized at N3= for the curves individually. To verify the siulations, it was desirable to easure on a range of transistor widths as shown in figure 3. Thus, it was decided to ipleent the driver stages with three different sizes (2/4, Id2 and O.S/l) for the output transistors N3P7. Each anufactured die contains 2 each of the above entioned sizes. In order to achieve larger widths for easureents several stages and dies are connected in parallel. Siulating the anilfnctured chip Siulations were also ade using a odel for the driver stage including parasitic capacitance extracted fro the actual chip layout. Also package parasitics and external wiring parasitics were included. In order to achieve different output transistor widths different nuber of drivers were connected in parallel as also done during easureents. Results fro the siulations are shown in figure 5 for the single crystal and in figure 6 for the dual crystals. Due to changes in the loading of the crystal when several stages are connected in parallel, the resulting curve has been divided into sections dependant on the nuber of transistor stages used. Loading on the crystal when receiving an echo stes fro the pull up transistor P3 and the different parasitics entioned above. IV. MEASUREMENTS Measureents were ade on the fabricated chip for a total output transistor width up to 9 for N3, corresponding to 8 for P7. Different nuber of driver stages were used in parallel to achieve different total output transistor widths. Results fro the easureents are presented in figure 7 for the single crystal and in figure 8 for the dual crystal. The curves have been divided into sections dependant on the nuber of driver stages used as discussed for the siulations above. 52 2 IEEE ULTRASONICS SYMPOSIUM
I.2... 4 I..8... E 2.6... Q).;.4 62.2...... 4... I *Five stages or 2 4 6 8 Total N3 transistor width /,;.4... e:.2...... 2 4 6 8 Total N3 transistor width / 4. I.2 3.8.6 Figure 5: Siulation on a single crystal using a nonideal electronic odel showing noralized echo aplitude as function of transistor width. 2.6.5.4 2.2 Figure 7: Measureent on a single crystal showing noralized echo aplitude as function of transistor width.... *Three stages +Four stages Five stages 2 4 6 8 2 4 6 8 Total N3 transistor width I Total N3 transistor width / Figure 6: Siulation on dual crystals using a nonideal electronic odel showing noralized echo aplitude as function of transistor width. Figure 8: Measureent on dual crystals showing noralized echo aplitude as function of transistor width. V. DISCUSSION Siulations The results fro the siulations with ideal electronic odels (fig. 3) show a peak in echo aplitude around the 2 transistor width for both the single and dual crystals, after which a slight drop takes place. One possible explanation to this behaviour is that the Q of the LCR parallel oscillation circuit fored by the crystal and N3 is dependent on the transistor width. For sall transistor width the dynaic ipedance in conducting state for the transistor is high leading to a high Q during the excitation pulse. As the width increases the Q value decreases and settles to a value decided by the crystal. The peak is not seen in the siulations where parasitic effects are taken into account (fig. 5, 6). This is likely due to the parasitic L, R and C lowering the Q of the circuit fro the start. In these siulations a slight drop in echo aplitude can be observed as ore driver stages are connected. The axiu output aplitude stabilises as the width passes 3 for the single crystal (fig. 5) and 6 for the dual crystal (fig. 6). The ideal siulations (fig. 3, 4) show a gradual increase in echo aplitude fro 3 transistor width up to for the single crystal and 5 for the dual crystal. After these points the echoes decrease (fig. 4). This is due to the fact that the load capacitance presented by the drains of N3 and P7 is increasing. In the siulations where parasitics are 2 IEEE ULTRASONICS SYMPOSIUM 53
included (fig. 5, 6), the gradual increase in the range 3 to can not be seen. Probable cause for this difference is that the load capacitance in these cases are dependent also on pads and the aount of etal used in the chip, giving a higher value than for the drain on the transistors only. Measureents The easureents for the single crystal (fig. 7) show a higher dependence on the nuber of stages used than what is seen in the siulations. Probably this is due to the parasitics not being correctly estiated in the siulations. However, easureents and siulations show a fair agreeent in the dependence on transistor width if the load influence is excluded. For the dual crystal the easureents presented in figure 8 show that the load influence is saller, which is to be expected as the source ipedance for the parallel crystals is half of the source ipedance for a single crystal. For the dual crystal, easureents and siulations agree well in the dependence on transistor width. Design Results fro both siulations and easureents suggest that the calculated widths give ore than 9% of axiu possible output aplitude for a 5V pushpull configuration, providing the nuber of driver stages used is kept inial. Also, using the calculated widths, a argin of 52% is provided before a drop in output aplitude takes place. This will account for process variations in the anufacturing of the chip. For the single crystal, using two 2 driver stages gives a transistor area saller than. 2, excluding pads and etal interconnections. VI. CONCLUSIONS Syste siulations using SPICE odels for the piezoelectric crystal together with MOS transistor odels have been used with very proising results, in the design of a CMOS driver circuit for piezoelectric crystals. The circuit has been anufactured using a.6 p CMOS process. Measureents on the anufactured chip verify the chosen design strategy and the perforance predicted by the siulations. The results show that siulations can be used to optiize the perforance of a coplete syste coprising both piezoelectric and electronical devices. This indicates that a purely siulation based design strategy can be proposed based on the findings. 2 [3 [4 VII. REFERENCES J.V. Hatfield et al, An integrated ultieleent array transducer for ultrasound iaging, Sensors and Actuators A, 442, pp. 6773, 994. W.C. Black and D.N. Stephens, CMOS Chip for Invasive Ultrasound Iaging, IEEE Journal of Solid State Circuits, Vol. 29, No., pp. 38387, Noveber 994. C Kuratli and Q Huang, A Fully Integrated Selfcalibrating TransitterReceiver IC for an Ultrasound Presence Detector Microsyste, IEEE Journal of Solid State Circuits, Vol. 33, pp. 83284, No. 6, June 998. R.Y. Liu, The design of electric excitations for the foration of desired teporal responses of highly efficient transducers, Acoustical Iaging, Vol. 2, pp. 29335, 982. S.S. Muhlen, Design of an optiized highpower ultrasonic transducer, IEEE 99 Ultrasonics Syposiu Proceedings, 3 vol. pp. 63634, 99. H.W. Persson, Electric excitation of ultrasound transducers for short pulse generation, Ultrasound in Med. & Biol., Vol. 7, pp. 285 29, 98. J.A. van Deventer et al, PSpice siulation of ultrasonic systes, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 47, No. 4, pp. 424, July 2. J. M. Rabaey, Digital Integrated Circuits, New Jersey: Prentice Hall, 996, ch. 4, pp. 243. 54 2 IEEE ULTRASONICS SYMPOSIUM