CD7BMS December 199 CMOS Dual J-K Master-Slave Flip-Flop Features Pinout High Voltage Type (V Rating) Set - Reset Capability CD7BMS TOP VIEW Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either High or Low Medium Speed Operation - 1MHz (typ.) Clock Toggle Rate at Standardized Symmetrical Output Characteristics Q Q OCK RESET K 1 3 5 1 15 1 13 1 VDD Q1 Q1 OCK 1 RESET 1 1% Tested For Quiescent Current at V J 11 K1 Maximum Input Current of 1µA at 1V Over Full Package-Temperature Range; - 1nA at 1V and +5 o C SET VSS 7 1 9 J1 SET 1 Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - V at VDD = -.5V at VDD = 15V Functional Diagram 5V, and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices Applications SET 1 J1 K1 OCK1 1 11 13 9 F/F1 VDD 1 15 1 Q1 Q1 Registers, Counters, Control Circuits RESET1 SET 1 7 Description J 1 Q CD7BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD13B dual D type flip-flop. K OCK RESET 5 3 F/F VSS Q The CD7BMS is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flipflop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input. The CD7BMS is supplied in these 1-lead outline packages: Braze Seal DIP HT Frit Seal DIP H1E Ceramic Flatpack HW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1--INTERSIL or 31-7-713 Copyright Intersil Corporation 1999 7-7 File Number 33
Specifications CD7BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD)............... -.5V to +V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs.............-.5V to VDD +.5V DC Input Current, Any One Input........................±1mA Operating Temperature Range................ to +15 o C Package Types D, F, K, H Storage Temperature Range (TSTG)........... -5 o C to +15 o C Lead Temperature (During Soldering)................. +5 o C At Distance 1/1 ± 1/3 Inch (1.59mm ±.79mm) from case for 1s Maximum Reliability Information Thermal Resistance................ θ ja θ jc Ceramic DIP and FRIT Package..... o C/W o C/W Flatpack Package................ 7 o C/W o C/W Maximum Package Power Dissipation (PD) at +15 o C For TA = to +1 o C (Package Type D, F, K)...... 5mW For TA = +1 o C to +15 o C (Package Type D, F, K).....Derate Linearity at 1mW/ o C to mw Device Dissipation per Output Transistor............... 1mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature.............................. +175 o C TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = V, VIN = VDD or GND 1 +5 o C - µa +15 o C - µa VDD = 1V, VIN = VDD or GND 3 - µa Input Leakage Current IIL VIN = VDD or GND VDD = 1 +5 o C -1 - na +15 o C -1 - na VDD = 1V 3-1 - na Input Leakage Current IIH VIN = VDD or GND VDD = 1 +5 o C - 1 na +15 o C - 1 na VDD = 1V 3-1 na Output Voltage VOL15 VDD = 15V, No Load 1,, 3 +5 o C, +15 o C, - 5 mv Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1,, 3 +5 o C, +15 o C, 1.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT =.V 1 +5 o C.53 - ma Output Current (Sink) IOL1 VDD =, VOUT =.5V 1 +5 o C 1. - ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +5 o C 3.5 - ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1 +5 o C - -.53 ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1 +5 o C - -1. ma Output Current (Source) IOH1 VDD =, VOUT = 9.5V 1 +5 o C - -1. ma Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +5 o C - -3.5 ma N Threshold Voltage VNTH VDD =, ISS = -1µA 1 +5 o C -. -.7 V P Threshold Voltage VPTH VSS = V, IDD = 1µA 1 +5 o C.7. V Functional F VDD =.V, VIN = VDD or GND 7 +5 o C VOH > VOL < V VDD = V, VIN = VDD or GND 7 +5 o C VDD/ VDD/ VDD = 1V, VIN = VDD or GND A +15 o C VDD = 3V, VIN = VDD or GND B Input Voltage Low VIL VDD = 5V, VOH >.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, - 1.5 V (Note ) Input Voltage High (Note ) VIH VDD = 5V, VOH >.5V, VOL <.5V 1,, 3 +5 o C, +15 o C, 3.5 - V Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VIL VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V 1. All voltages referenced to device GND, 1% testing being implemented.. Go/No Go test with limits applied to inputs. 1,, 3 +5 o C, +15 o C, - V 1,, 3 +5 o C, +15 o C, 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is.5v max. 7-71
Specifications CD7BMS TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE 1, ) SUBGROUPS TEMPERATURE MIN MAX UNITS Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +5 o C - 3 ns Clock To Q, Q TPLH1 1, 11 +15 o C, - 5 ns Propagation Delay TPLH VDD = 5V, VIN = VDD or GND 9 +5 o C - 3 ns Set To Q Reset To Q 1, 11 +15 o C, - 5 ns Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +5 o C - ns Set To Q, Reset To Q 1, 11 +15 o C, - 5 ns Transition Time TTLH VDD = 5V, VIN = VDD or GND 9 +5 o C - ns TTHL 1, 11 +15 o C, - 7 ns Maximum Clock Input F VDD = 5V, VIN = VDD or GND 9 +5 o C 3.5 - MHz Frequency 1, 11 +15 o C, 3.5/1.35 - MHz NOTES: 1. VDD = 5V, = 5pF, RL = K. and +15 o C limits guaranteed, 1% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = 5V, VIN = VDD or GND 1,, +5 o C - 1 µa +15 o C - 3 µa VDD =, VIN = VDD or GND 1,, +5 o C - µa +15 o C - µa VDD = 15V, VIN = VDD or GND 1,, +5 o C - µa +15 o C - 1 µa Output Voltage VOL VDD = 5V, No Load 1, +5 o C, +15 o C, - 5 mv Output Voltage VOL VDD =, No Load 1, +5 o C, +15 o C, Output Voltage VOH VDD = 5V, No Load 1, +5 o C, +15 o C, Output Voltage VOH VDD =, No Load 1, +5 o C, +15 o C, - 5 mv.95 - V 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT =.V 1, +15 o C.3 - ma. - ma Output Current (Sink) IOL1 VDD =, VOUT =.5V 1, +15 o C.9 - ma 1. - ma Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, +15 o C. - ma. - ma Output Current (Source) IOH5A VDD = 5V, VOUT =.V 1, +15 o C - -.3 ma - -. ma Output Current (Source) IOH5B VDD = 5V, VOUT =.5V 1, +15 o C - -1.15 ma - -. ma Output Current (Source) IOH1 VDD =, VOUT = 9.5V 1, +15 o C - -.9 ma - -1. ma 7-7
Specifications CD7BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, +15 o C - -. ma - -. ma Input Voltage Low VIL VDD =, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, - 3 V Input Voltage High VIH VDD =, VOH > 9V, VOL < 1V 1, +5 o C, +15 o C, Propagation Delay Clock To Q, Q Propagation Delay Set To Q, Reset To Q Propagation Delay Set To Q, Reset To Q Transition Time Maximum Clock Input Frequency Toggle Mode Input TR, TF = 5ns Minimum Data Setup Time Minimum Set or Reset Pulse Width Minimum Clock Pulse Width TPHL1 TPLH1 7 - V VDD = 1,, 3 +5 o C - 13 ns VDD = 15V 1,, 3 +5 o C - 9 ns TPLH VDD = 1,, 3 +5 o C - 13 ns VDD = 15V 1,, 3 +5 o C - 9 ns TPHL3 VDD = 1,, 3 +5 o C - 17 ns VDD = 15V 1,, 3 +5 o C - 1 ns TTHL VDD = 1,, 3 +5 o C - 1 ns TTLH VDD = 15V 1,, 3 +5 o C - ns F VDD = 1,, 3 +5 o C - MHz VDD = 15V 1,, 3 +5 o C 1 - MHz TS VDD = 5V 1,, 3 +5 o C - ns VDD = 1,, 3 +5 o C - 75 ns VDD = 15V 1,, 3 +5 o C - 5 ns TW VDD = 5V 1,, 3 +5 o C - 1 ns VDD = 1,, 3 +5 o C - ns VDD = 15V 1,, 3 +5 o C - 5 ns TW VDD = 5V 1,, 3 +5 o C - 1 ns VDD = 1,, 3 +5 o C - ns VDD = 15V 1,, 3 +5 o C - ns Clock Input Rise Or Fall TR VDD = 5V 1,, 3, +5 o C - 5 µs Time (Note 5) TF VDD = 1,, 3, +5 o C - 5 µs VDD = 15V 1,, 3, +5 o C - µs Input Capacitance CIN 1, +5 o C - 7.5 pf NOTES: 1. All voltages referenced to device GND.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. = 5pF, RL = K, Input TR, TF < ns.. If more than one unit is cascaded in a parallel clocked operation, tr should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load. MIN MAX UNITS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD VDD = V, VIN = VDD or GND 1, +5 o C - 7.5 µa 7-73
Specifications CD7BMS N Threshold Voltage VNTH VDD =, ISS = -1µA 1, +5 o C -. -. V N Threshold Voltage VTN VDD =, ISS = -1µA 1, +5 o C - ±1 V Delta P Threshold Voltage VTP VSS = V, IDD = 1µA 1, +5 o C.. V P Threshold Voltage VTP VSS = V, IDD = 1µA 1, +5 o C - ±1 V Delta Functional F VDD = 1V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND 1 +5 o C VOH > VDD/ Propagation Delay Time TPHL TPLH NOTES: TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE 1. All voltages referenced to device GND.. = 5pF, RL = K, Input TR, TF < ns. VOL < VDD/ VDD = 5V 1,, 3, +5 o C - 1.35 x +5 o C Limit 3. See Table for +5 o C limit.. Read and Record MIN MAX UNITS V ns TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +5 O C PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ±.µa Output Current (Sink) IOL5 ± % x Pre-Test Reading Output Current (Source) IOH5A ± % x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD-3 METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) 1% 5 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 1% 5 1, 7, 9 IDD, IOL5, IOH5A Interim Test (Post Burn-In) 1% 5 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 5 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 1% 5 1, 7, 9 IDD, IOL5, IOH5A PDA (Note 1) 1% 5 1, 7, 9, Deltas Final Test 1% 5, 3, A, B, 1, 11 Group A Sample 55 1,, 3, 7, A, B, 9, 1, 11 Group B Subgroup B-5 Sample 55 1,, 3, 7, A, B, 9, 1, 11, Deltas Subgroups 1,, 3, 9, 1, 11 Subgroup B- Sample 55 1, 7, 9 Group D Sample 55 1,, 3, A, B, 9 Subgroups 1, 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-3 TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup 55 1, 7, 9 Table 1, 9 Table 7-7
CD7BMS TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -.5V 5kHz 5kHz Static Burn-In 1 1,, 1, 15 3-13 1 Note 1 Static Burn-In 1,, 1, 15 3-7, 9-13, 1 Note 1 Dynamic Burn- -, 7-9, 1 5,, 1, 11, 1 1, 1, 15 3, 13 In Note Irradiation 1,, 1, 15 3-7, 9-13, 1 Note 3 NOTE: 1. Each pin except VDD and GND will have a series resistor of 1K ± 5%, VDD = 1V ±.5V. Each pin except VDD and GND will have a series resistor of.75k ± 5%, VDD = 1V ±.5V 3. Each pin except VDD and GND will have a series resistor of 7K ± 5%; Group E, Subgroup, sample size is dice/wafer, failures, VDD = ±.5V Logic Diagram RESET *(1) J *(1) K *5(11) p TG n MASTER p TG n SLAVE Q (1) Q 1(15) p TG n p TG n SET *7(9) VDD *3(13) OCK * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS LOGIC DIAGRAM AND TRUTH TABLE FOR CD7BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS) TRUTH TABLE PRESENT STATE NEXT STATE INPUTS OUTPUT OUTPUTS J K S R Q * Q Q 1 X 1 X 1 1 X 1 X 1 1 1 X X X No Change X X 1 X X 1 X X 1 X X 1 X X 1 1 X X 1 1 Logic 1 = High Level Logic = Low Level * = Level change X = Don t care 7-75
CD7BMS Typical Performance Characteristics OUTPUT LOW (SINK) CURRENT (IOL) (ma) 3 5 15 1 5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V OUTPUT LOW (SINK) CURRENT (IOL) (ma) 15. 1.5 1. 7.5 5..5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 5V 5 1 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 1 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE. MINIMUM N OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15-1 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V -5-1 -15 - -5-3 OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15-1 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V - -15V -5-1 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (ma) FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS DISSIPATION PER DEVICE (PD) (µw) 1 1 3 1 1 1 CD = 15pF = 5pF SUPPLY VOLTAGE (VDD) = 15V INPUT tr = tf = ns 1 1 3 1 1 5 1 1 7 INPUT FREQUENCY (fi) (Hz) FIGURE 5. TYPICAL POWER DISSIPATION vs FREQUENCY 5V FIGURE. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tphl, tplh) (ns) 5 15 1 5 SUPPLY VOLTAGE (VDD) = 5V 15V 1 LOAD CAPACITANCE () (pf) FIGURE. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (OCK OR SET TO Q, OCK OR RESET TO Q) 7-7
CD7BMS Typical Performance Characteristics (Continued) PROPAGATION DELAY TIME (tphl, tplh) (ns) 5 15 1 5 SUPPLY VOLTAGE (VDD) = 5V 15V OCK FREQUENCY (f) (MHz) 3 5 15 1 5 trl tf = 5ns = 5pF 1 LOAD CAPACITANCE () (pf) FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE (SET TO Q, OR RESET TO Q) 5 1 15 SUPPLY VOLTAGE (VDD) (V) FIGURE. TYPICAL MAXIMUM OCK FREQUENCY vs SUPPLY VOLTAGE (TOGGLE MODE) Chip Dimensions and Pad Layout METALLIZATION: PASSIVATION: BOND PADS: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (1-3 inch) Thickness: 11kÅ 1kÅ, AL. 1.kÅ - 15.kÅ, Silane. inches X. inches MIN DIE THICKNESS:.19 inches -.1 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 77