Outline. Lecture 3. Basics. Logical vs. physical memory. 8086 physical memory. x86 byte ordering



Similar documents
Faculty of Engineering Student Number:

Computer Organization and Architecture

(Refer Slide Time: 00:01:16 min)

Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2

Byte Ordering of Multibyte Data Items

Lecture 7: Machine-Level Programming I: Basics Mohamed Zahran (aka Z)

Instruction Set Architecture (ISA)

MACHINE INSTRUCTIONS AND PROGRAMS

1 The Java Virtual Machine

An Introduction to Assembly Programming with the ARM 32-bit Processor Family

BCD (ASCII) Arithmetic. Where and Why is BCD used? Packed BCD, ASCII, Unpacked BCD. BCD Adjustment Instructions AAA. Example

612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap Famiglie di processori) PROBLEMS

Traditional IBM Mainframe Operating Principles

8086 Microprocessor (cont..)

Intel 8086 architecture

ASSEMBLY LANGUAGE PROGRAMMING (6800) (R. Horvath, Introduction to Microprocessors, Chapter 6)

8. MACROS, Modules, and Mouse

MICROPROCESSOR AND MICROCOMPUTER BASICS

CPU Organisation and Operation

Connecting AMD Flash Memory to a System Address Bus

Computer Architecture Lecture 3: ISA Tradeoffs. Prof. Onur Mutlu Carnegie Mellon University Spring 2013, 1/18/2013

CPU Organization and Assembly Language

Instruction Set Architecture. or How to talk to computers if you aren t in Star Trek

Machine Programming II: Instruc8ons

Unpacked BCD Arithmetic. BCD (ASCII) Arithmetic. Where and Why is BCD used? From the SQL Server Manual. Packed BCD, ASCII, Unpacked BCD

MACHINE ARCHITECTURE & LANGUAGE

Microprocessor & Assembly Language

a storage location directly on the CPU, used for temporary storage of small amounts of data during processing.

The x86 PC: Assembly Language, Design, and Interfacing 5 th Edition

1 Classical Universal Computer 3

The 80x86 Instruction Set

ASSEMBLY PROGRAMMING ON A VIRTUAL COMPUTER

CHAPTER 6 TASK MANAGEMENT

CHAPTER 7: The CPU and Memory

Computer Organization and Assembly Language

MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 20: Stack Frames 7 March 08

M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

LSN 2 Computer Processors

Computers. Hardware. The Central Processing Unit (CPU) CMPT 125: Lecture 1: Understanding the Computer

Complete 8086 instruction set

How To Write Portable Programs In C

2) Write in detail the issues in the design of code generator.

Chapter 5 Instructor's Manual

Exceptions in MIPS. know the exception mechanism in MIPS be able to write a simple exception handler for a MIPS machine

Section 44. CPU with Extended Data Space (EDS)

Let s put together a Manual Processor

Comp 255Q - 1M: Computer Organization Lab #3 - Machine Language Programs for the PDP-8

Chapter 7D The Java Virtual Machine

The Linux Virtual Filesystem

TIMING DIAGRAM O 8085

Computer Organization. and Instruction Execution. August 22

Topics. Introduction. Java History CS 146. Introduction to Programming and Algorithms Module 1. Module Objectives

Central Processing Unit (CPU)

Chapter 9 Computer Design Basics!

DNA Data and Program Representation. Alexandre David

Embedded Systems. Review of ANSI C Topics. A Review of ANSI C and Considerations for Embedded C Programming. Basic features of C

An Overview of Stack Architecture and the PSC 1000 Microprocessor

PART B QUESTIONS AND ANSWERS UNIT I

A3 Computer Architecture

plc numbers Encoded values; BCD and ASCII Error detection; parity, gray code and checksums

ROC Protocol Specifications Manual

Property of ISA vs. Uarch?

IA-32 Intel Architecture Software Developer s Manual

Reduced Instruction Set Computer (RISC)

Intel Hexadecimal Object File Format Specification Revision A, 1/6/88

EE361: Digital Computer Organization Course Syllabus

Record Storage and Primary File Organization

Writing an 8086 emulator in Python

Syscall 5. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Chapter 2 Topics. 2.1 Classification of Computers & Instructions 2.2 Classes of Instruction Sets 2.3 Informal Description of Simple RISC Computer, SRC

About the Tutorial. Audience. Prerequisites. Copyright & Disclaimer

Section 1.4 Place Value Systems of Numeration in Other Bases

Instruction Set Architecture

Motorola 8- and 16-bit Embedded Application Binary Interface (M8/16EABI)

PC Assembly Language. Paul A. Carter

We r e going to play Final (exam) Jeopardy! "Answers:" "Questions:" - 1 -

Computer Gateway Specification and Technical Data

PROBLEMS (Cap. 4 - Istruzioni macchina)

Memory Systems. Static Random Access Memory (SRAM) Cell

Assembly Language Tutorial

Systems Design & Programming Data Movement Instructions. Intel Assembly

Fast Arithmetic Coding (FastAC) Implementations

Overview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX

The Design of the Inferno Virtual Machine. Introduction

8085 INSTRUCTION SET

Computer Systems Structure Main Memory Organization

An Introduction to the ARM 7 Architecture

MICROPROCESSOR. Exclusive for IACE Students iacehyd.blogspot.in Ph: /422 Page 1

X86-64 Architecture Guide

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC Microprocessor & Microcontroller Year/Sem : II/IV

The Hexadecimal Number System and Memory Addressing

Modbus RTU Communications RX/WX and MRX/MWX

Hardware Assisted Virtualization

Instruction Set Design

Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University

ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-17: Memory organisation, and types of memory

A s we saw in Chapter 4, a CPU contains three main sections: the register section,

S7 for Windows S7-300/400

Hexadecimal Object File Format Specification

Transcription:

Outline Lecture 3 bout Memory ddressing memory Data types MOV instruction ddressing modes Instruction format Dr. Dimitrios S. Nikolopoulos SL/UIU Basics Logical vs. physical memory Memory in the x processors is byte-addressable Whenever we present an address to the address bus, we specify the location of a byte in memory Byte is the basic memory unit It is possible to retrieve/store more than one bytes with a single memory access -bit words, consecutive bytes 3-bit doublewords, consecutive bytes Logical memory is the view of memory seen by the programmer large byte-addressable array of bytes We can read/write bytes, words or doublewords We do not worry about how data is fetched from memory, we only see the result of the memory access as,, or bytes Physical memory The physical organization of memory cells, which is not visible to the programmer The unit of access to physical memory is equal to the width of the data bus.g. bits in, 3 bits in 3 and later physical memory x byte ordering ven Bank F 9 7 D 9 B F 9 7 7 D 5 33 3 55 B Read a byte of address : result= Read a word from address : result=b Read a doubleword from address : result=55b Memory locations and contain and B But a word access from address returns B x uses little endian byte order The requested address () points to the lower order byte of the result The higher order byte of the result is taken from the next higher sequential address () Data Bus (5:) Data Bus (7:)

Byte ordering Little endian vs. big endian In big endian ordering the higher order byte of the result is retrieved from the requested address Used in many UNIX servers Byte ordering is a property of the architecture ven Bank F 9 7 D 9 B F 9 7 7 D 5 33 3 55 B When we read from word data(5:)=b,data(7:)= Bytes as presented in the data bus are in the right order! This is an aligned memory access Data Bus (5:) Data Bus (7:) ven Bank F 9 7 D 9 B F 9 7 7 D 5 33 3 55 B Data Bus (5:) Data Bus (7:) What if read a word from address? It is a valid memory access, you can always read from odd addresses Result should be B But the bytes in the data bus are not aligned data(5:)=b,data(7:)= Whenever we read more than one bytes from memory the bytes presented in the address bus must be aligned according to the architecture byte ordering If we read a word from address, the byte in address must be stored in the higher order byte of the data bus and the byte in address in the lower order byte of the data bus years ago I had to do that by hand But you don t have to do it anymore, the processor takes care of it Data Types Do we have to worry about unaligned memory accesses? Yes, if you want your program to run fast! In an unaligned memory access the processor has to Read odd byte (one memory access) Read even byte (second memory access) lign the two bytes (some overhead in the hardware) In an aligned memory access the processor just Reads even byte (one memory access) ligned access is at least twice as fast Integer numbers Bits, Nibbles, Bytes, Words, Doublewords Signed/unsigned Floating point numbers Different format than integers Text 7-bit SII characters (letters, characters) -bit SII encoding allows for more graphical symbols Strings: sequences of characters Documents: collection of strings

Data Types Data Types rrays Sequences of numbers, characters Files Images (.jpg,.gif,.tiff, ) Video (MPG,.avi, Quicktime, ) udio (.wav,.mp3, ) verything is managed as a sequence of bytes stored in the memory of your computer! The data type actually depends on the way you access and use these bytes! ven Bank F 9 7 D 9 B F 9 7 7 D 5 33 3 55 B Data Bus (5:) Data Bus (7:) signed/unsigned -bit integers signed/unsigned -bit words signed/unsigned 3-bit doublewords n incomprehensible string Instructions and operands Real vs. protected mode Protected mode at a glance In real mode we address the first megabyte of memory (h-fh), we are limited to a -bit address bus and -bit registers In protected mode we can address Gigabytes of memory using 3-bit address bus and 3-bit registers Used in and higher Memory accessing based on segmentation Segments can be considered as protected regions of memory Somehow more more complex address translation mechanism Still segment:offset, segment is -bit, offset can be -bit or 3-bit Segment field used as pointer to a segment table that contains the starting address of the segment in physical memory You are not allowed to modify the segment table in user mode but you can in privileged mode, e.g. if writing an operating system Using segments The MOV instruction Logical partitioning of your program Original SP SS:BP SS:SP S:IP DS:DI DS:SI Memory Used stack Unused stack ode (your program) Data (variables) SS S DS Move data From memory to a register From a register to memory From a register to another register Never from memory to memory! Syntax MOV destination, source Destination and source can be registers or memory addresses defined in different ways which we call addressing modes 3

ddressing modes ddressing modes, the fastest! MOV X, BX MOV L, BL MOV DX, SI MOV DS, BX Remember, source/destination must be of equal size Load a value to a register MOV X, 3h Direct MOV X, [3h] Move data from a memory location to a register 3h is a displacement within the data segment DS Indirect (base relative, or indexed) MOV X,[BX] MOV X,[BP] MOV X,[SI] MOV X,[DI] Displacement is put in a register BX, SI, DI define displacements in the data segment BP defines a displacement in the stack segment ddressing modes How do I learn all this? Base plus index (base relative indexed) MOV X, [BX+DI] MOV X, [BX+SI] Base can be BX or BP, index SI or DI relative MOV X, [BX+3h] on the left can be BX, BP, SI, or DI Base relative plus index MOV X, [BX+DI+3h] ll you have to remember is this table BX SI BP DI DISP Pick or item from each of the columns, just make sure you end up with at least one item Never pick two items from the same column 7 valid addressing modes ddressing mode examples ddressing mode examples Instruction omment ddressing Mode Memory ontents Instruction omment ddressing Mode Memory ontents MOV X, BX Move to X the -bit value in BX 9 D MOV [X], X Move to the memory location pointed to by DS:X the value in X Direct 3 lsb msb DT MOV X, DI Move to X the -bit value in DI 9 F MOV X, [DI] Move to X the -bit value pointed to by DS:DI Indexed B 5 MOV H, L Move to L the -bit value in X MOV [DI], X Move to address DS:DI the -bit value in X Indexed 9 5 MOV H, h Move to H the -bit value H B DT MOV X, [BX] Move to X the -bit value pointed to by DS:BX Indirect B 7 MOV X, 3h Move to X the value 3h B 3 DT MOV [BX], X Move to the memory address DS:BX the -bit value stored in X Indirect 9 7 MOV X, ONST Move to X the constant defined as ONST B lsb msb DT MOV [BP], X Move to memory address SS:BP the -bit value in X Indirect 9 MOV X, X Move to X the address or offset of the variable X B lsb msb DT MOV X, TB[BX] Move to X the value in memory at DS:BX + TB Relative B 7 lsb msb DISP MOV X, [3h] Move to X the value at memory location 3h Direct 3 DISP MOV TB[BX], X Move value in X to memory address DS:BX + TB Relative 9 7 lsb msb DISP MOV X, [X] Move to X the value in memory location DS:X Direct lsb msb DISP MOV X, [BX + DI] Move to X the value in memory at DS:BX + DI Base Plus Index B

ddressing mode examples Machine language Instruction MOV [BX + DI], X MOV X, [BX + DI + 3h] MOV word [BX + DI + 3h], 57h omment Move to the memory location pointed to by DS:X the value in X Move word in memory location DS:BX + DI + 3h to X register Move immediate value 57h to memory location BX + DI + 3h ddressing Mode Base Plus Index Base Rel Plus Index Base Rel Plus Index Memory ontents 9 B 3 7 3 7 5 DISP verything (instructions, operands, data) is translated to bytes stored in memory You need to be able to interpret the meaning of these bytes to debug your programs In particular, we need to learn the format of instructions so that we can interpret the bytes that correspond to instructions in memory x instructions are complex, they vary in size from byte to 3 bytes Generic instruction format Instruction Basics Opcode Mode Displacement Data/ No operands xample: N DT w/-bit data xample: MOV L, 5 DT w/-bit data xample: MOV X, 3h DISP DISP DISP DISP w/-bit displacement xample: J +5 w/-bit displacement xample: MOV L, [3h] w/mode register to register xample: MOV L, H w/mode & -bit displacement xample: MOV [BX + ], X w/mode & -bit displacement xample: MOV [BX+3], X ach instruction can have only one operand that points to a memory location The sizes of the operands of an instruction must match The mode byte encodes which registers are used by the instruction If the data size used is ambiguous you have to specify it! MOV BYT [BX], h MOV [BX], WORD h natomy of an instruction Opcode Mode Displacement Data/ natomy of an instruction Opcode Mode Displacement Data/ D W OD MOD RG R/M Opcode contains the type of instruction we execute plus two special bits, D and W The mode byte is used only in instructions that use register addressing modes and encodes the source and destination for instructions with two operands D stands for direction and defines the data flow of the instruction D=, data flows from RG to R/M D=, data flows from R/M to RG W stands for the size of data W=, byte-sized data W=, word (in real mode) or double-word sized (in protected mode) D W OD MOD RG R/M MOD field specifies the addressing mode no displacement -bit displacement, sign extended -bit displacement R/M is a register, register addressing mode If MOD is,, or, the R/M field selects one of the memory addressing modes 5

s in the RG and R/M fields xample ode W= (Byte) W= (Word) W= (DWord) L X X L X X DL DX DX BL BX BX H SP SP H BP BP DH SI SI BH DI DI onsider the instruction Bh binary Opcode -> MOV D= data goes from R/M to RG W= data is word-sized MOD=, register addressing RG= destination, R/M= source MOV BP, SP ode W= W= W= L X X L X X DL DX DX BL BX BX H SP SP H BP BP DH SI SI BH DI DI MOD Displacement addressing If MOD is,, or R/M has an entirely different meaning xamples: No displacement FUNTION -bit sign-extended displacement -bit displacement R/M is a register (register addressing mode) If MOD= and R/M= mode is [DI] If MOD= and R/M= mode is [DI+33h] If = and R/M= modes is [DI+33h] R/M ode Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX xample Instruction 5h Opcode -> MOV D=, data flows from R/M to RG W=, -bit argument MOD= (no displacement) RG= (DL) RG= ([DI] addressing mode) MOV DL, [DI] ode W= W= W= L X X L X X DL DX DX BL BX BX H SP SP H BP BP DH SI SI BH DI DI R/M ode Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX Direct ddressing Mode Direct ddressing MOD is always R/M is always RG encodes the register to/from we take data as usual Third byte contains the lower-order bytes of the displacement, fourth byte contains the high order byte of the displacement xample: Opcode -> MOV W= (byte-sized data) D= data flows from RG MOD, RG= (DL), R/M= Low-order byte of displacement High-order byte of displacement MOV [h], DL ode W= W= W= L X X L X X DL DX DX BL BX BX H SP SP H BP BP DH SI SI BH DI DI

Oops addressing R/M= points to BP when MOD=! What happens with MOV DL, [BP] No displacement, MOD= [BP] addressing mode, R/M= Hack MOV DL,[BP+] MOD= (-bit displacement) R/M= This also means that MOV [BP] instructions are at least three bytes long (there is always a displacement even if it is ) MOV WORD [BX+h], 3h OD W MOD R/M Byte Byte Displacement-low Displacement-high Byte 3 Byte Data-low Data-high Byte 5 Byte R/M ode Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX Segment MOV instructions Different opcode Segments are selected by setting the RG field RG ode Segment reg. S S SS DS FS GS xample MOV BX, S Opcode MOD= (register addressing) RG= (S) R/M= (BX) B Try the examples with MOV MP due Wednesday 5. p.m. 7