REV 0 WAFER FABRICATION FLOWCHART CMOS PROCESS



Similar documents
Titre: Required Information For Submitting Databases to TELEDYNE DALSA Design & Product Support.

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

Winbond W2E512/W27E257 EEPROM

AN900 APPLICATION NOTE

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

Introduction to Semiconductor Manufacturing Technology. Chapter 1, Introduction. Hong Xiao, Ph. D.

Facility Rates & Expense Caps

Historical production of rigid PCB s

Winbond W971GG6JB-25 1 Gbit DDR2 SDRAM 65 nm CMOS DRAM Process

How to Build a Printed Circuit Board. Advanced Circuits Inc 2004

Chapter 11 PVD and Metallization

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Fabrication and Manufacturing (Basics) Batch processes

III. Wet and Dry Etching

Chapter 10 CVD and Dielectric Thin Film

A Laboratory Approach to Semiconductor Process Technology

SPECIFICATION Aluminum Module Frames. Allowed anodization before fabrication for clear frames.

How compact discs are made

CHAPTER 5. OVERVIEW OF THE MANUFACTURING PROCESS

Good Boards = Results

Figure 1 Wafer with Notch

INTRODUCTION: PURPOSE:

ADVANCED WAFER PROCESSING WITH NEW MATERIALS. ASM International Analyst and Investor Technology Seminar Semicon West July 15, 2015

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process

Chapter 1 Introduction to The Semiconductor Industry 2005 VLSI TECH. 1

Implementation Of High-k/Metal Gates In High-Volume Manufacturing

INTRODUCTION TO ION IMPLANTATION Dr. Lynn Fuller, Dr. Renan Turkman Dr Robert Pearson

Parameter Min. Typ. Max. Units. Frequency Range GHz. Minimum Insertion Loss db. Dynamic 38 GHz 26 db

AMD AXDA3000DKV4D Athlon TM XP Microprocessor Structural Analysis

Advanced VLSI Design CMOS Processing Technology

ELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication

Semiconductor doping. Si solar Cell

The Road to 450 mm Semiconductor Wafers Ira Feldman

Damage-free, All-dry Via Etch Resist and Residue Removal Processes

Process Specification for the Anodizing of Aluminum Alloys

Neuere Entwicklungen zur Herstellung optischer Schichten durch reaktive. Wolfgang Hentsch, Dr. Reinhard Fendler. FHR Anlagenbau GmbH

h e l p s y o u C O N T R O L

FLEXIBLE CIRCUITS MANUFACTURING

PIDG FASTON Receptacles and Tabs

Development of High-Speed High-Precision Cooling Plate

How To Implant Anneal Ion Beam

Lapping and Polishing Basics

Silicon-On-Glass MEMS. Design. Handbook

Comparison study of FinFETs: SOI vs. Bulk Performance, Manufacturing Variability and Cost

IHSS-N1 WELDED HONEYCOMB CORE SPECIFICATION. Generated: Sergiy Papyshev Engineering. Approved: Don Prysi Manufacturing. Approved: Merzuk Ramic Quality

Intel Q3GM ES 32 nm CPU (from Core i5 660)

To meet the requirements of demanding new

1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.

Chapter 12. Chemical Mechanical Polishing

Photolithography. Class: Figure Various ways in which dust particles can interfere with photomask patterns.

QUALITY CONTROL MANUAL

1700V Bi-Mode Insulated Gate Transistor (BIGT) on Thin Wafer Technology

Quartz Glass. Tubes and Rods

INF4420. Outline. Layout and CMOS processing technology. CMOS Fabrication overview. Design rules. Layout of passive and active componets.

COATED CARBIDE. TiN. Al 2 O 3

Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

ARMSTRONG MOLD GRAPHITE DIE CASTING DIVISION

Periodic Table, Valency and Formula


VLSI Fabrication Process

Flex Circuit Design and Manufacture.

Injection moulding and modelling on a micro scale

Grad Student Presentation Topics PHGN/CHEN/MLGN 435/535: Interdisciplinary Silicon Processing Laboratory

For Touch Panel and LCD Sputtering/PECVD/ Wet Processing

RELIABILITY ASSURANCE RELIABILITY ASSURANCE PROGRAM

Wafer Placement Repeatibility and Robot Speed Improvements for Bonded Wafer Pairs Used in 3D Integration

8-bit Atmel Microcontrollers. Application Note. Atmel AVR211: Wafer Level Chip Scale Packages

Etching Etch Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between

Miniaturizing Flexible Circuits for use in Medical Electronics. Nate Kreutter 3M

1. Photon Beam Damage and Charging at Solid Surfaces John H. Thomas III

Sheet Resistance = R (L/W) = R N L

Supplier Quality. Assurance Provisions. Manual. SQAP-001 Rev. E

HCF4001B QUAD 2-INPUT NOR GATE

Solar Photovoltaic (PV) Cells

Wafer Bumping & Wafer Level Packaging for 300mm Wafer

Rapid Prototyping and Development of Microfluidic and BioMEMS Devices

Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

1. Single sided PCB: conductors on only one surface of a dielectric base.

AC coupled pitch adapters for silicon strip detectors

italtec PRINTED CIRCUITS EQUIPMENT PRINTED CIRCUITS EQUIPMENT Insulator machines Echting machines Special equipment and machines

Processing Procedures for CYCLOTENE 4000 Series Photo BCB Resins DS2100 Puddle Develop Process

A Study of Haze Generation as Thin Film Materials

Advanced Technologies and Equipment for 3D-Packaging

Coating Thickness and Composition Analysis by Micro-EDXRF

Deposition of Silicon Oxide, Silicon Nitride and Silicon Carbide Thin Films by New Plasma Enhanced Chemical Vapor Deposition Source Technology

ISOTROPIC ETCHING OF THE SILICON NITRIDE AFTER FIELD OXIDATION.

Tableting Punch Performance Can Be Improved With Precision Coatings

the runnerless types of molds are explained post molding operations are described the basic methods of applied decoration methods are examined

Manufacturing, Supply & Quality Plan for Tower Bolts. SL Tower Bolt Market Penetration

Spectroscopic Ellipsometry:

Introduction. Development of the AQEC Standard

SPECIFICATIONS FOR BOON EDAM TOMSED MODEL TUT-65TMB

Package Trends for Mobile Device

Measurement & Analytics Measurement made easy

SILICON SOLAR CELLS FOR TANDEM HIGH-EFFICIENCY SOLAR CELLS (VHESC)

SURFACE FINISHES. Technical Webinar DELIVERING QUALITY SINCE 1952.

Transcription:

WAFER FABRICATION FLOWCHART INCOMING Vendor: Product: Package: Location of Wafer Fab: Assembly: Final Test: Q.C. Test: Source Accept Test: Quality Contact: Linear Technology Corporation CMOS Products All Package Types Linear Technology Corp., Milpitas, CA./ Camas, WA Linear Technology Corporation, Penang, Malaysia or any approved assembly subcontractor Naib Girn, LTC Milpitas, CA (408) 432-1900 Ext. 2519 QUALITY AND GATE MANUFACTURING PROCESS QUALITY MONITOR / SURVEILLANCE REWORK /TEST INCOMING RAW MATERIAL WAFERS : SCRATCHES, PITS, HAZE, CRATERS, DIMPLES, CONTAMINATION 1 X 1.0% AQL TO 2.5 AQL LEVEL 1 OXYGEN/CARBON MEUREMENT IVITY / CONDUCTIVITY INFRARED SPECTROMETER MAGNETRON V/I METER S/S=2, S/S=2, DIMENSIONAL CALIPERS 2.5% AQL, LEVEL 1 THICKNESS AND TAPER/BOW DIAL THICKNESS GAGE 2.5% AQL, LEVEL 1 ORIENTATION BREAK TEST S/S=1. EACH BATCH RETICLE, C.D. MEUREMENTS EACH PLATE CHEMICALS GES INITIAL TARGETS OXIDE THICKNESS NANOSPEC 3 WAFERS / CYCLE P-WELL MK MK HF 100X PRE IMT P-WELL IMT IMT DOSE CHECK THERMAWAVE 2 WAFERS/LOT P-WELL DRIVE LINEAR TECHNOY CORPORATION PAGE 1 OF 5

/TEST STRIP ALL OXIDE HF OXIDE THICKNESS NANOSPEC 2 WAFERS /LOT PAD NITRIDE NITRIDE NITRIDE THICKNESS NANOSPEC 3 WAFERS/CYCLE ACTIVE MK ETCH DIMENSIONS 400X P FIELD IMT MK MK HF 400X BORON FIELD IMT IMT DOSE CHECK THERMAWAVE 2 WAFERS / LOT 100X N-FIELD IMT MK MK HF UV 100X PHOS FIELD IMT IMT DOSE CHECK THERMAWAVE 2 WAFERS / LOT 100X LOCOS OXIDE PLMA NITRIDE STRIP ETCH (100%) 20X CMOS CAP MK MK HF DIMENSIONS 100X CAP IMT IMT DOSE CHECK THERMAWAVE 2 WAFERS / LOT 100X ETCH PAD OXIDE HF OXIDE THICKNESS NANOSPEC 1 WAFER /CYCLE LINEAR TECHNOY CORPORATION PAGE 2 OF 5

/TEST GATE OXIDE P CH OXIDE THICKNESS NONOSPEC 3 WAFERS/CYCLE N CH VTP IMT MK MK HF 100X BORON VT IMT IMT DOSE CHECK THEMAWAVE 2 WAFERS/LOT 100X 100% OF THE WAFERS POLY POLY THICKNESS NANOSPEC 2 WAFERS/CYCLE NODE BACK ETCH MK MK RF PLMA AND HF SINKER PRE 100% <10 DEFECTS PER WAFER RS (OHMS/SQ) 4 POINT PROBE 2 TEST WAFERS PER RUN CMOS GATE MK MK RF PLMA AND HF 100X NODE P+ IMT MK MK 100X P+ S/D IMT IMT DOSE CHECK THERMAWAFE 2 WAFERS/LOT 100X N+ IMT MK MK 100X N+ S/D IMT IMT DOSE CHECK THERMAWAVE 2 WAFERS/LOT 100X LINEAR TECHNOY CORPORATION PAGE 3 OF 5

/TEST SOURCE DRAIN REOX P+ N+ LPOE LPOE LPCVD LPOE THICKNESS NANOSPEC 3 WAFERS/CYCLE CMOS GETTER RS (OHMS/SQ) 4 POINT PROBE 2 TEST WAFERS PER RUN CMOS CONTACT MK MK HF UV 100X ALUMINUM SPUTTER MACHINE <5 DEFECTS PER WAFER 100% RS (OHMS/SQ) 4 POINT PROBE 2 TEST CHIP/CYCLE CMOS METAL MK MK METAL ENCHANT BATH FINAL INSPECT DIMENSIONS 2 200X 1000X DIMENSIONS MEURE 2 WAFERS PER RUN LOT, ACCEPT ON 0 FAILURES ALLOY ANNEAL 100% <10 DEFECTS PER WAFER LPOM PSIVATION LPCVD 100%, MORE THAN 2 COLOR CHANGE IS FAIL 10X 3 WAFERS/CYCLE <3 DEFECTS/PER LPOM THICKNESS NANOSPEC 3 WAFERS/CYCLE PHOSPHOROUS CONCENTRATION 10:1 HF ETCH RATE 3 WAFERS/CYCLE LINEAR TECHNOY CORPORATION PAGE 4 OF 5

/TEST PEN PECVD NITRIDE 100%, MORE THAN 2 COLOR CHANGE IS FAIL 10X 3 WAFERS/CYCLE <5 DEFECTS/PER PEN THICKNESS NANOSPEC 3 WAFERS/CYCLE INDEX OF REFRACTION ELIPSOMETER 3 WAFERS/CYCLE PAD MK MK RF PLMA ETCH AND HF FINAL INSPECT 100X OF THE WAFER ELECTRICAL TEST LOMAC PARAMETRIC ANALYZER 100% BACKLAP DISCO N/A N/A N/A BACKSIDE GOLD BACKSIDE METALLIZATION UN-AIDED EYE 100% SEM STEP COVERAGE 2 PHOTOS SCANNING ELECTRON CMOS = 1 WAFER PER WEEK GENERAL METAL 1 PHOTO NWELL & PWELL = 1 WAFER EVERY RUN LINEAR TECHNOY CORPORATION PAGE 5 OF 5