1 Boolen Logic Such simple things, And we mke of them something so complex it defets us, Almost. John Ashery (. 1927), Americn poet Every digitl device e it personl computer, cellulr telephone, or network rer is sed on set of chips designed to store nd process informtion. Although these chips come in different shpes nd forms, they re ll mde from the sme uilding locks: Elementry logic gtes. The gtes cn e physiclly implemented in mny different mterils nd friction technologies, ut their logicl ehvior is consistent cross ll computers. In this chpter we strt with one primitive logic gte Nnd nd uild ll the other logic gtes from it. The result is rther stndrd set of gtes, which will e lter used to construct our computer s processing nd storge chips. This will e done in chpters 2 nd 3, respectively. All the hrdwre chpters in the ook, eginning with this one, hve the sme structure. Ech chpter focuses on well-defined tsk, designed to construct or integrte certin fmily of chips. The prerequisite knowledge needed to pproch this tsk is provided in rief Bckground section. The next section provides complete Specifiction of the chips strctions, nmely, the vrious services tht they should deliver, one wy or nother. Hving presented the wht, susequent Implementtion section proposes guidelines nd hints how the chips cn e ctully implemented. A Perspective section rounds up the chpter with concluding comments importnt topics tht were left from the discussion. Ech chpter ends with technicl Project section. This section gives step-y-step instructions for ctully uilding the chips on personl computer, using the hrdwre simultor supplied with the ook. This eing the first hrdwre chpter in the ook, the Bckground section is somewht lengthy, feturing specil section on hrdwre description nd simultion tools.
8 Chpter 1 1.1 Bckground This chpter focuses on the construction of fmily of simple chips clled Boolen gtes. Since Boolen gtes re physicl implementtions of Boolen functions, we strt with rief tretment of Boolen lger. We then show how Boolen gtes implementing simple Boolen functions cn e interconnected to deliver the functionlity of more complex chips. We conclude the ckground section with description of how hrdwre design is ctully done in prctice, using softwre simultion tools. 1.1.1 Boolen Alger Boolen lger dels with Boolen (lso clled inry) vlues tht re typiclly leled true/flse, 1/0, yes/no, on/off, nd so forth. We will use 1 nd 0. A Boolen function is function tht opertes on inry inputs nd returns inry puts. Since computer hrdwre is sed on the representtion nd mnipultion of inry vlues, Boolen functions ply centrl role in the specifiction, construction, nd optimiztion of hrdwre rchitectures. Hence, the ility to formulte nd nlyze Boolen functions is the first step towrd constructing computer rchitectures. Truth Tle Representtion The simplest wy to specify Boolen function is to enumerte ll the possile vlues of the function s input vriles, long with the function s put for ech set of inputs. This is clled the truth tle representtion of the function, illustrted in figure 1.1. The first three columns of figure 1.1 enumerte ll the possile inry vlues of the function s vriles. For ech one of the 2 n possile tuples v 1...v n (here n ¼ 3), the lst column gives the vlue of f ðv 1...v n Þ. Boolen Expressions In ddition to the truth tle specifiction, Boolen function cn lso e specified using Boolen opertions over its input vriles. The sic Boolen opertors tht re typiclly used re And (x And y is 1 exctly when oth x nd y re 1) Or (x Or y is 1 exctly when either x or y or oth re 1), nd Not (Not x is 1 exctly when x is 0). We will use common rithmetic-like nottion for these opertions: x y (or xy) mens x And y, x þ y mens x Or y, nd x mens Not x. To illustrte, the function defined in figure 1.1 is equivlently given y the Boolen expression f ðx; y; zþ ¼ðx þ yþz. For exmple, let us evlute this expression on the
9 Boolen Logic x y z fðx; y; zþ 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0 Figure 1.1 Truth tle representtion of Boolen function (exmple). inputs x ¼ 0, y ¼ 1, z ¼ 0 (third row in the tle). Since y is 1, it follows tht x þ y ¼ 1 nd thus 1 0 ¼ 1 1 ¼ 1. The complete verifiction of the equivlence etween the expression nd the truth tle is chieved y evluting the expression on ech of the eight possile input comintions, verifying tht it yields the sme vlue listed in the tle s right column. Cnonicl Representtion As it turns, every Boolen function cn e expressed using t lest one Boolen expression clled the cnonicl representtion. Strting with the function s truth tle, we focus on ll the rows in which the function hs vlue 1. For ech such row, we construct term creted y And-ing together literls (vriles or their negtions) tht fix the vlues of ll the row s inputs. For exmple, let us focus on the third row in figure 1.1, where the function s vlue is 1. Since the vrile vlues in this row re x ¼ 0, y ¼ 1, z ¼ 0, we construct the term xyz. Following the sme procedure, we construct the terms xyz nd xyz for rows 5 nd 7. Now, if we Or-together ll these terms (for ll the rows where the function hs vlue 1), we get Boolen expression tht is equivlent to the given truth tle. Thus the cnonicl representtion of the Boolen function shown in figure 1.1 is f ðx; y; zþ ¼ xyz þ xyz þ xyz. This construction leds to n importnt conclusion: Every Boolen function, no mtter how complex, cn e expressed using three Boolen opertors only: And, Or, nd Not. Two-Input Boolen Functions An inspection of figure 1.1 revels tht the numer of Boolen functions tht cn e defined over n inry vriles is 2 2 n. For exmple, the sixteen Boolen functions spnned y two vriles re listed in figure 1.2. These functions were constructed systemticlly, y enumerting ll the possile 4-wise comintions of inry vlues in the four right columns. Ech function hs conventionl
10 Chpter 1 Function x 0 0 1 1 y 0 1 0 1 Constnt 0 0 0 0 0 0 And x y 0 0 0 1 x And Not y x y 0 0 1 0 x x 0 0 1 1 Not x And y x y 0 1 0 0 y y 0 1 0 1 Xor x y þ x y 0 1 1 0 Or x þ y 0 1 1 1 Nor x þ y 1 0 0 0 Equivlence x y þ x y 1 0 0 1 Not y y 1 0 1 0 If y then x xþ y 1 0 1 1 Not x x 1 1 0 0 If x then y x þ y 1 1 0 1 Nnd x y 1 1 1 0 Constnt 1 1 1 1 1 1 Figure 1.2 All the Boolen functions of two vriles. nme tht seeks to descrie its underlying opertion. Here re some exmples: The nme of the Nor function is shorthnd for Not-Or: Tke the Or of x nd y, then negte the result. The Xor function shorthnd for exclusive or returns 1 when its two vriles hve opposing truth-vlues nd 0 otherwise. Conversely, the Equivlence function returns 1 when the two vriles hve identicl truth-vlues. The If-x-then-y function (lso known s x! y, or x Implies y ) returns 1 when x is 0 or when oth x nd y re 1. The other functions re self-explntory. The Nnd function (s well s the Nor function) hs n interesting theoreticl property: Ech one of the opertions And, Or, nd Not cn e constructed from it, nd it lone (e.g., x Or y ¼ðx Nnd xþ Nnd ðy Nnd yþ. And since every Boolen function cn e constructed from And, Or, nd Not opertions using the cnonicl representtion method, it follows tht every Boolen function cn e constructed from Nnd opertions lone. This result hs fr-reching prcticl implictions: Once we hve in our disposl physicl device tht implements Nnd, we cn use mny copies of this device (wired in certin wy) to implement in hrdwre ny Boolen function.
11 Boolen Logic 1.1.2 Gte Logic A gte is physicl device tht implements Boolen function. If Boolen function f opertes on n vriles nd returns m inry results (in ll our exmples so fr, m ws 1), the gte tht implements f will hve n input pins nd m put pins. When we put some vlues v 1...v n in the gte s input pins, the gte s logic its internl structure should compute nd put f ðv 1...v n Þ. And just like complex Boolen functions cn e expressed in terms of simpler functions, complex gtes re composed from more elementry gtes. The simplest gtes of ll re mde from tiny switching devices, clled trnsistors, wired in certin topology designed to effect the overll gte functionlity. Although most digitl computers tody use electricity to represent nd trnsmit inry dt from one gte to nother, ny lterntive technology permitting switching nd conducting cpilities cn e employed. Indeed, during the lst fifty yers, reserchers hve uilt mny hrdwre implementtions of Boolen functions, including mgnetic, opticl, iologicl, hydrulic, nd pneumtic mechnisms. Tody, most gtes re implemented s trnsistors etched in silicon, pckged s chips. In this ook we use the words chip nd gte interchngely, tending to use the term gtes for simple chips. The vilility of lterntive switching technology options, on the one hnd, nd the oservtion tht Boolen lger cn e used to strct the ehvior of ny such technology, on the other, is extremely importnt. Bsiclly, it implies tht computer scientists don t hve to worry physicl things like electricity, circuits, switches, relys, nd power supply. Insted, computer scientists cn e content with the strct notions of Boolen lger nd gte logic, trusting tht someone else (the physicists nd electricl engineers less their souls) will figure how to ctully relize them in hrdwre. Hence, primitive gte (see figure 1.3) cn e viewed s lck ox device tht implements n elementry logicl opertion in one wy or nother we don t cre how. A hrdwre designer strts from such primitive gtes nd designs more complicted functionlity y interconnecting them, leding to the construction of composite gtes. And Or in Not Figure 1.3 Stndrd symolic nottion of some elementry logic gtes.
12 Chpter 1 Gte interfce Gte implementtion c And And If ==c=1 then =1 else =0 c And Figure 1.4 Composite implementtion of three-wy And gte. The rectngle on the right defines the conceptul oundries of the gte interfce. Primitive nd Composite Gtes Since ll logic gtes hve the sme input nd put semntics (0 s nd 1 s), they cn e chined together, creting composite gtes of ritrry complexity. For exmple, suppose we re sked to implement the 3-wy Boolen function Andð; ; cþ. Using Boolen lger, we cn egin y oserving tht c ¼ð Þc, or, using prefix nottion, Andð; ; cþ ¼AndðAndð; Þ; cþ. Next, we cn use this result to construct the composite gte depicted in figure 1.4. The construction descried in figure 1.4 is simple exmple of gte logic, lso clled logic design. Simply put, logic design is the rt of interconnecting gtes in order to implement more complex functionlity, leding to the notion of composite gtes. Since composite gtes re themselves reliztions of ( possily complex) Boolen functions, their side ppernce (e.g., left side of figure 1.4) looks just like tht of primitive gtes. At the sme time, their internl structure cn e rther complex. We see tht ny given logic gte cn e viewed from two different perspectives: externl nd internl. The right-hnd side of figure 1.4 gives the gte s internl rchitecture, or implementtion, wheres the left side shows only the gte interfce, nmely, the input nd put pins tht it exposes to the side world. The former is relevnt only to the gte designer, wheres the ltter is the right level of detil for other designers who wish to use the gte s n strct off-the-shelf component, with pying ttention to its internl structure. Let us consider nother logic design exmple tht of Xor gte. As discussed efore, Xorð; Þ is 1 exctly when either is 1 nd is 0, or when is 0 nd is 1. Sid otherwise, Xorð; Þ ¼OrðAndð; NotðÞÞ; AndðNotðÞ; ÞÞ. This definition leds to the logic design shown in figure 1.5. Note tht the gte interfce is unique: There is only one wy to descrie it, nd this is normlly done using truth tle, Boolen expression, or some verl specific-
13 Boolen Logic Xor And Or 0 0 0 0 1 1 1 0 1 1 1 0 And Figure 1.5 Xor gte, long with possile implementtion. tion. This interfce, however, cn e relized using mny different implementtions, some of which will e etter thn others in terms of cost, speed, nd simplicity. For exmple, the Xor function cn e implemented using four, rther thn five, And, Or, nd Not gtes. Thus, from functionl stndpoint, the fundmentl requirement of logic design is tht the gte implementtion will relize its stted interfce, in one wy or nother. From n efficiency stndpoint, the generl rule is to try to do more with less, tht is, use s few gtes s possile. To sum up, the rt of logic design cn e descried s follows: Given gte specifiction (interfce), find n efficient wy to implement it using other gtes tht were lredy implemented. This, in nutshell, is wht we will do in the rest of this chpter. 1.1.3 Actul Hrdwre Construction Hving descried the logic of composing complex gtes from simpler ones, we re now in position to discuss how gtes re ctully uilt. Let us strt with n intentionlly nïve exmple. Suppose we open chip friction shop in our home grge. Our first contrct is to uild hundred Xor gtes. Using the order s downpyment, we purchse soldering gun, roll of copper wire, nd three ins leled And gtes, Or gtes, nd Not gtes, ech contining mny identicl copies of these elementry logic gtes. Ech of these gtes is seled in plstic csing tht exposes some input nd put pins, s well s power supply plug. To get strted, we pin figure 1.5 to our grge wll nd proceed to relize it using our hrdwre. First, we tke two And gtes, two Not gtes, nd one Or gte, nd mount them on ord ccording to the
14 Chpter 1 figure s ly. Next, we connect the chips to one nother y running copper wires mong them nd y soldering the wire ends to the respective input/put pins. Now, if we follow the gte digrm crefully, we will end up hving three exposed wire ends. We then solder pin to ech one of these wire ends, sel the entire device (except for the three pins) in plstic csing, nd lel it Xor. We cn repet this ssemly process mny times over. At the end of the dy, we cn store ll the chips tht we ve uilt in new in nd lel it Xor gtes. If we (or other people) re sked to construct some other chips in the future, we ll e le to use these Xor gtes s elementry uilding locks, just s we used the And, Or, nd Not gtes efore. As the reder hs proly sensed, the grge pproch to chip production leves much to e desired. For strters, there is no gurntee tht the given chip digrm is correct. Although we cn prove correctness in simple cses like Xor, we cnnot do so in mny relisticlly complex chips. Thus, we must settle for empiricl testing: Build the chip, connect it to power supply, ctivte nd dectivte the input pins in vrious configurtions, nd hope tht the chip puts will gree with its specifictions. If the chip fils to deliver the desired puts, we will hve to tinker with its physicl structure rther messy ffir. Further, even if we will come up with the right design, replicting the chip ssemly process mny times over will e time-consuming nd error-prone ffir. There must e etter wy! 1.1.4 Hrdwre Description Lnguge ( HDL) Tody, hrdwre designers no longer uild nything with their re hnds. Insted, they pln nd optimize the chip rchitecture on computer worksttion, using structured modeling formlisms like Hrdwre Description Lnguge, or HDL (lso known s VHDL, where V stnds for Virtul ). The designer specifies the chip structure y writing n HDL progrm, which is then sujected to rigorous ttery of tests. These tests re crried virtully, using computer simultion: A specil softwre tool, clled hrdwre simultor, tkes the HDL progrm s input nd uilds n imge of the modeled chip in memory. Next, the designer cn instruct the simultor to test the virtul chip on vrious sets of inputs, generting simulted chip puts. The puts cn then e compred to the desired results, s mndted y the client who ordered the chip uilt. In ddition to testing the chip s correctness, the hrdwre designer will typiclly e interested in vriety of prmeters such s speed of computtion, energy consumption, nd the overll cost implied y the chip design. All these prm-
15 Boolen Logic eters cn e simulted nd quntified y the hrdwre simultor, helping the designer optimize the design until the simulted chip delivers desired cost/performnce levels. Thus, using HDL, one cn completely pln, deug, nd optimize the entire chip efore single penny is spent on ctul production. When the HDL progrm is deemed complete, tht is, when the performnce of the simulted chip stisfies the client who ordered it, the HDL progrm cn ecome the lueprint from which mny copies of the physicl chip cn e stmped in silicon. This finl step in the chip life cycle from n optimized HDL progrm to mss production is typiclly sourced to compnies tht specilize in chip friction, using one switching technology or nother. Exmple: Building Xor Gte As we hve seen in figures 1.2 nd 1.5, one wy to define exclusive or is Xorð; Þ ¼OrðAndð; NotðÞÞ; AndðNotðÞ; ÞÞ. This logic cn e expressed either grphiclly, s gte digrm, or textully, s n HDL progrm. The ltter progrm is written in the HDL vrint used through this ook, defined in ppendix A. See figure 1.6 for the detils. Explntion An HDL definition of chip consists of heder section nd prts section. The heder section specifies the chip interfce, nmely the chip nme nd the nmes of its input nd put pins. The prts section descries the nmes nd topology of ll the lower-level prts (other chips) from which this chip is constructed. Ech prt is represented y sttement tht specifies the prt nme nd the wy it is connected to other prts in the design. Note tht in order to write such sttements legily, the HDL progrmmer must hve complete documenttion of the underlying prts interfces. For exmple, figure 1.6 ssumes tht the input nd put pins of the Not gte re leled in nd, nd those of And nd Or re leled, nd. This API-type informtion is not ovious, nd one must hve ccess to it efore one cn plug the chip prts into the present code. Inter-prt connections re descried y creting nd connecting internl pins, s needed. For exmple, consider the ottom of the gte digrm, where the put of Not gte is piped into the input of susequent And gte. The HDL code descries this connection y the pir of sttements Not(...,=not) nd And(=not,...). The first sttement cretes n internl pin (ound wire) nmed not, feeding into it. The second sttement feeds the vlue of not into the input of n And gte. Note tht pins my hve n unlimited fn. For exmple, in figure 1.6, ech input is simultneously fed into two gtes. In gte
16 Chpter 1 in not And w1 Or in not And w2 HDL progrm (Xor.hdl) Test script (Xor.tst) Output file (Xor.) /* Xor (exclusive or) gte: If <> =1 else =0. */ CHIP Xor { IN, ; OUT ; PARTS: Not(in=, =not); Not(in=, =not); And(=, =not, =w1); And(=not, =, =w2); Or(=w1, =w2, =); } lod Xor.hdl, put-list,, ; set 0, set 0, evl, put; set 0, set 1, evl, put; set 1, set 0, evl, put; set 1, set 1, evl, put; 0 0 0 0 1 1 1 0 1 1 1 0 Figure 1.6 HDL implementtion of Xor gte. digrms, multiple connections re descried using forks. In HDL, the existence of forks is implied y the code. Testing Rigorous qulity ssurnce mndtes tht chips e tested in specific, replicle, nd well-documented fshion. With tht in mind, hrdwre simultors re usully designed to run test scripts, written in some scripting lnguge. For exmple, the test script in figure 1.6 is written in the scripting lnguge understood y the hrdwre simultor supplied with the ook. This scripting lnguge is descried fully in ppendix B. Let us give rief description of the test script from figure 1.6. The first two lines of the test script instruct the simultor to lod the Xor.hdl progrm nd get redy to
17 Boolen Logic print the vlues of selected vriles. Next, the script lists series of testing scenrios, designed to simulte the vrious contingencies under which the Xor chip will hve to operte in rel-life situtions. In ech scenrio, the script instructs the simultor to ind the chip inputs to certin dt vlues, compute the resulting put, nd record the test results in designted put file. In the cse of simple gtes like Xor, one cn write n exhustive test script tht enumertes ll the possile input vlues of the gte. The resulting put file (right side of figure 1.6) cn then e viewed s complete empiricl proof tht the chip is well designed. The luxury of such certitude is not fesile in more complex chips, s we will see lter. 1.1.5 Hrdwre Simultion Since HDL is hrdwre construction lnguge, the process of writing nd deugging HDL progrms is quite similr to softwre development. The min difference is tht insted of writing code in lnguge like Jv, we write it in HDL, nd insted of using compiler to trnslte nd test the code, we use hrdwre simultor. The hrdwre simultor is computer progrm tht knows how to prse nd interpret HDL code, turn it into n executle representtion, nd test it ccording to the specifictions of given test script. There exist mny commercil hrdwre simultors on the mrket, nd these vry gretly in terms of cost, complexity, nd ese of use. Together with this ook we provide simple (nd free!) hrdwre simultor tht is sufficiently powerful to support sophisticted hrdwre design projects. In prticulr, the simultor provides ll the necessry tools for uilding, testing, nd integrting ll the chips presented in the ook, leding to the construction of generl-purpose computer. Figure 1.7 illustrtes typicl chip simultion session. 1.2 Specifiction This section specifies typicl set of gtes, ech designed to crry common Boolen opertion. These gtes will e used in the chpters tht follow to construct the full rchitecture of typicl modern computer. Our strting point is single primitive Nnd gte, from which ll other gtes will e derived recursively. Note tht we provide only the gtes specifictions, or interfces, delying implementtion detils until susequent section. Reders who wish to construct the specified gtes in HDL re encourged to do so, referring to ppendix A s needed. All the gtes cn e uilt nd simulted on personl computer, using the hrdwre simultor supplied with the ook.
18 Chpter 1 simultor controls test script HDL progrm current pin vlues typicl simultion step put file Figure 1.7 A screen shot of simulting n Xor chip on the hrdwre simultor. The simultor stte is shown just fter the test script hs completed running. The pin vlues correspond to the lst simultion step ( ¼ ¼ 1). Note tht the put file generted y the simultion is consistent with the Xor truth tle, indicting tht the loded HDL progrm delivers correct Xor functionlity. The compre file, not shown in the figure nd typiclly specified y the chip s client, hs exctly the sme structure nd contents s tht of the put file. The fct tht the two files gree with ech other is evident from the sttus messge displyed t the ottom of the screen.
19 Boolen Logic 1.2.1 The Nnd Gte The strting point of our computer rchitecture is the Nnd gte, from which ll other gtes nd chips re uilt. The Nnd gte is designed to compute the following Boolen function: Nndð; Þ 0 0 1 0 1 1 1 0 1 1 1 0 Through the ook, we use chip API oxes to specify chips. For ech chip, the API specifies the chip nme, the nmes of its input nd put pins, the function or opertion tht the chip effects, nd n optionl comment. Chip nme: Nnd Inputs:, Outputs: Function: If ==1 then =0 else =1 Comment: This gte is considered primitive nd thus there is no need to implement it. 1.2.2 Bsic Logic Gtes Some of the logic gtes presented here re typiclly referred to s elementry or sic. At the sme time, every one of them cn e composed from Nnd gtes lone. Therefore, they need not e viewed s primitive. Not The single-input Not gte, lso known s converter, converts its input from 0 to 1 nd vice vers. The gte API is s follows: Chip nme: Not Inputs: in Outputs: Function: If in=0 then =1 else =0.
20 Chpter 1 And The And function returns 1 when oth its inputs re 1, nd 0 otherwise. Chip nme: And Inputs:, Outputs: Function: If ==1 then =1 else =0. Or The Or function returns 1 when t lest one of its inputs is 1, nd 0 otherwise. Chip nme: Or Inputs:, Outputs: Function: If ==0 then =0 else =1. Xor The Xor function, lso known s exclusive or, returns 1 when its two inputs hve opposing vlues, nd 0 otherwise. Chip nme: Xor Inputs:, Outputs: Function: If =/ then =1 else =0. Multiplexor A multiplexor (figure 1.8) is three-input gte tht uses one of the inputs, clled selection it, to select nd put one of the other two inputs, clled dt its. Thus, etter nme for this device might hve een selector. The nme multiplexor ws dopted from communictions systems, where similr devices re used to serilize (multiplex) severl input signls over single put wire. Chip nme: Mux Inputs:,, sel Outputs: Function: If sel=0 then = else =.
21 Boolen Logic sel sel 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 Mux 0 1 1 1 1 0 1 0 1 1 1 1 sel Figure 1.8 on the left. Multiplexor. The tle t the top right is n revited version of the truth tle sel 0 in 0 1 0 in in DMux sel Figure 1.9 Demultiplexor. Demultiplexor A demultiplexor (figure 1.9) performs the opposite function of multiplexor: It tkes single input nd chnnels it to one of two possile puts ccording to selector it tht specifies which put to chose. Chip nme: DMux Inputs: in, sel Outputs:, Function: If sel=0 then {=in, =0} else {=0, =in}. 1.2.3 Multi-Bit Versions of Bsic Gtes Computer hrdwre is typiclly designed to operte on multi-it rrys clled uses. For exmple, sic requirement of 32-it computer is to e le to compute (it-wise) n And function on two given 32-it uses. To implement this opertion, we cn uild n rry of 32 inry And gtes, ech operting seprtely
22 Chpter 1 on pir of its. In order to enclose ll this logic in one pckge, we cn encpsulte the gtes rry in single chip interfce consisting of two 32-it input uses nd one 32-it put us. This section descries typicl set of such multi-it logic gtes, s needed for the construction of typicl 16-it computer. We note in pssing tht the rchitecture of n-it logic gtes is siclly the sme irrespective of n s vlue. When referring to individul its in us, it is common to use n rry syntx. For exmple, to refer to individul its in 16-it us nmed dt, we use the nottion dt[0], dt[1],..., dt[15]. Multi-Bit Not An n-it Not gte pplies the Boolen opertion Not to every one of the its in its n-it input us: Chip nme: Not16 Inputs: in[16] // 16-it pin Outputs: [16] Function: For i=0..15 [i]=not(in[i]). Multi-Bit And An n-it And gte pplies the Boolen opertion And to every one of the n it-pirs rryed in its two n-it input uses: Chip nme: And16 Inputs: [16], [16] Outputs: [16] Function: For i=0..15 [i]=and([i],[i]). Multi-Bit Or An n-it Or gte pplies the Boolen opertion Or to every one of the n it-pirs rryed in its two n-it input uses: Chip nme: Or16 Inputs: [16], [16] Outputs: [16] Function: For i=0..15 [i]=or([i],[i]).
23 Boolen Logic Multi-Bit Multiplexor An n-it multiplexor is exctly the sme s the inry multiplexor descried in figure 1.8, except tht the two inputs re ech n-it wide; the selector is single it. Chip nme: Mux16 Inputs: [16], [16], sel Outputs: [16] Function: If sel=0 then for i=0..15 [i]=[i] else for i=0..15 [i]=[i]. 1.2.4 Multi-Wy Versions of Bsic Gtes Mny 2-wy logic gtes tht ccept two inputs hve nturl generliztion to multiwy vrints tht ccept n ritrry numer of inputs. This section descries set of multi-wy gtes tht will e used susequently in vrious chips in our computer rchitecture. Similr generliztions cn e developed for other rchitectures, s needed. Multi-Wy Or An n-wy Or gte puts 1 when t lest one of its n it inputs is 1, nd 0 otherwise. Here is the 8-wy vrint of this gte: Chip nme: Or8Wy Inputs: in[8] Outputs: Function: =Or(in[0],in[1],...,in[7]). Multi-Wy/ Multi-Bit Multiplexor An m-wy n-it multiplexor selects one of mnit input uses nd puts it to single n-it put us. The selection is specified y set of k control its, where k ¼ log 2 m. Figure 1.10 depicts typicl exmple. The computer pltform tht we develop in this ook requires two vritions of this chip: A 4-wy 16-it multiplexor nd n 8-wy 16-it multiplexor:
24 Chpter 1 sel[1] sel[0] 0 0 0 1 1 0 c 1 1 d c d 4-wy Mux,,c,d nd re ech 16-it wide sel[1] sel[0] Figure 1.10 4-wy multiplexor. The width of the input nd put uses my vry. Chip nme: Mux4Wy16 Inputs: [16], [16], c[16], d[16], sel[2] Outputs: [16] Function: If sel=00 then = else if sel=01 then = else if sel=10 then =c else if sel=11 then =d Comment: The ssignment opertions mentioned ove re ll 16-it. For exmple, "=" mens "for i=0..15 [i]=[i]". Chip nme: Mux8Wy16 Inputs: [16],[16],c[16],d[16],e[16],f[16],g[16],h[16], sel[3] Outputs: [16] Function: If sel=000 then = else if sel=001 then = else if sel=010 =c... else if sel=111 then =h Comment: The ssignment opertions mentioned ove re ll 16-it. For exmple, "=" mens "for i=0..15 [i]=[i]". Multi-Wy/ Multi-Bit Demultiplexor An m-wy n-it demultiplexor (figure 1.11) chnnels single n-it input into one of m possile n-it puts. The selection is specified y set of k control its, where k ¼ log 2 m. The specific computer pltform tht we will uild requires two vritions of this chip: A 4-wy 1-it demultiplexor nd n 8-wy 1-it multiplexor, s follows.
25 Boolen Logic sel[1] sel[0] c d 0 0 in 0 0 0 0 1 0 in 0 0 1 0 0 0 in 0 1 1 0 0 0 in in sel[1] 4-wy DMux sel[0] Figure 1.11 4-wy demultiplexor. Chip nme: DMux4Wy Inputs: in, sel[2] Outputs:,, c, d Function: If sel=00 then {=in, =c=d=0} else if sel=01 then {=in, =c=d=0} else if sel=10 then {c=in, ==d=0} else if sel=11 then {d=in, ==c=0}. Chip nme: DMux8Wy Inputs: in, sel[3] Outputs:,, c, d, e, f, g, h Function: If sel=000 then {=in, =c=d=e=f=g=h=0} else if sel=001 then {=in, =c=d=e=f=g=h=0} else if sel=010...... else if sel=111 then {h=in, ==c=d=e=f=g=0}. 1.3 Implementtion Similr to the role of xioms in mthemtics, primitive gtes provide set of elementry uilding locks from which everything else cn e uilt. Opertionlly, primitive gtes hve n off-the-shelf implementtion tht is supplied externlly. Thus, they cn e used in the construction of other gtes nd chips with worrying their internl design. In the computer rchitecture tht we re now eginning
26 Chpter 1 to uild, we hve chosen to se ll the hrdwre on one primitive gte only: Nnd. We now turn to lining the first stge of this ottom-up hrdwre construction project, one gte t time. Our implementtion guidelines re intentionlly prtil, since we wnt you to discover the ctul gte rchitectures yourself. We reiterte tht ech gte cn e implemented in more thn one wy; the simpler the implementtion, the etter. Not: The implementtion of unry Not gte from inry Nnd gte is simple. Tip: Think positive. And: Once gin, the gte implementtion is simple. Tip: Think negtive. Or/ Xor: These functions cn e defined in terms of some of the Boolen functions implemented previously, using some simple Boolen mnipultions. Thus, the respective gtes cn e uilt using previously uilt gtes. Multiplexor/ Demultiplexor: gtes. Likewise, these gtes cn e uilt using previously uilt Multi-Bit Not/And/Or Gtes: Since we lredy know how to implement the elementry versions of these gtes, the implementtion of their n-ry versions is simply mtter of constructing rrys of n elementry gtes, hving ech gte operte seprtely on its it inputs. This implementtion tsk is rther oring, ut it will crry its weight when these multi-it gtes re used in more complex chips, s descried in susequent chpters. Multi-Bit Multiplexor: The implementtion of n n-ry multiplexor is simply mtter of feeding the sme selection it to every one of n inry multiplexors. Agin, oring tsk resulting in very useful chip. Multi-Wy Gtes: Implementtion tip: Think forks. 1.4 Perspective This chpter descried the first steps tken in n pplied digitl design project. In the next chpter we will uild more complicted functionlity using the gtes uilt here.
27 Boolen Logic Although we hve chosen to use Nnd s our sic uilding lock, other pproches re possile. For exmple, one cn uild complete computer pltform using Nor gtes lone, or, lterntively, comintion of And, Or, nd Not gtes. These constructive pproches to logic design re theoreticlly equivlent, just s ll theorems in geometry cn e founded on different sets of xioms s lterntive points of deprture. The theory nd prctice of such constructions re covered in stndrd textooks digitl design or logic design. Through the chpter, we pid no ttention to efficiency considertions such s the numer of elementry gtes used in constructing composite gte or the numer of wire crossovers implied y the design. Such considertions re criticlly importnt in prctice, nd gret del of computer science nd electricl engineering expertise focuses on optimizing them. Another issue we did not ddress t ll is the physicl implementtion of gtes nd chips using the lws of physics, for exmple, the role of trnsistors emedded in silicon. There re of course severl such implementtion options, ech hving its own chrcteristics (speed, power requirements, production cost, etc.). Any nontrivil coverge of these issues requires some ckground in electronics nd physics. 1.5 Project Ojective Implement ll the logic gtes presented in the chpter. The only uilding locks tht you cn use re primitive Nnd gtes nd the composite gtes tht you will grdully uild on top of them. Resources The only tool tht you need for this project is the hrdwre simultor supplied with the ook. All the chips should e implemented in the HDL lnguge specified in ppendix A. For ech one of the chips mentioned in the chpter, we provide skeletl.hdl progrm (text file) with missing implementtion prt. In ddition, for ech chip we provide.tst script file tht tells the hrdwre simultor how to test it, long with the correct put file tht this script should generte, clled.cmp or compre file. Your jo is to complete the missing implementtion prts of the supplied.hdl progrms. Contrct When loded into the hrdwre simultor, your chip design (modified.hdl progrm), tested on the supplied.tst file, should produce the puts listed in the supplied.cmp file. If tht is not the cse, the simultor will let you know.
28 Chpter 1 Tips The Nnd gte is considered primitive nd thus there is no need to uild it: Whenever you use Nnd in one of your HDL progrms, the simultor will utomticlly invoke its uilt-in tools/uiltin/nnd.hdl implementtion. We recommend implementing the other gtes in this project in the order in which they pper in the chpter. However, since the uiltin directory fetures working versions of ll the chips descried in the ook, you cn lwys use these chips with defining them first: The simultor will utomticlly use their uilt-in versions. For exmple, consider the skeletl Mux.hdl progrm supplied in this project. Suppose tht for one reson or nother you did not complete this progrm s implementtion, ut you still wnt to use Mux gtes s internl prts in other chip designs. This is not prolem, thnks to the following convention. If our simultor fils to find Mux.hdl file in the current directory, it utomticlly invokes uilt-in Mux implementtion, pre-supplied with the simultor s softwre. This uiltin implementtion Jv clss stored in the uiltin directory hs the sme interfce nd functionlity s those of the Mux gte descried in the ook. Thus, if you wnt the simultor to ignore one or more of your chip implementtions, simply move the corresponding.hdl files of the current directory. Steps We recommend proceeding in the following order: 0. The hrdwre simultor needed for this project is ville in the tools directory of the ook s softwre suite. 1. Red ppendix A, sections A1 A6 only. 2. Go through the hrdwre simultor tutoril, prts I, II, nd III only. 3. Build nd simulte ll the chips specified in the projects/01 directory.