Programming of Microcontrollers in Assembly Language

Brno University of Technology Programming of Microcontrollers in Assembly Language Microprocessor Techniques and Embedded Systems Lecture 2 Dr. Tomas Fryza

Contents Basic Architectures in Microprocessor Techniques Von Neumann, Harvard, CISC, RISC Development of Microcontrollers Applications Assembler Directives Programming Model Types of Instructions AVR Source Code Example

Princeton versus Harvard In 1970s U.S. government asked Princeton and Harvard universities to come up with a computer architecture (used in computing tables of Naval Artillery shell distances for varying elevations and environmental conditions). Two basic conceptions: Von Neumann (chief scientist s name in Princeton univ.), Harvard. Von Neumann architecture: computer with common memory for storing the control program as well as variables and other data structures, three fundamental parts of every computers: CPU, memory, I/O, internal structure is independent to the computer task (i.e. computer is controlled by software), program is executed in sequential way (current instruction is defined by Program Counter), memory is divided to constant blocks; indexes of these blocks are used as addresses.

Harvard Architecture Harvard conception used separate memory banks for program storage, the processor stack, and variable RAM. The Harvard architecture was largely ignored until the late 1970s. The Harvard architecture executes instructions in fewer instruction cycles than the Von Neumann architecture, because of a much greater amount of instruction parallelism is possible in Harvard architecture. Instruction fetches can take place during previous instruction execution and not wait for either a finish of instruction execution or have to stop the processor s operation while the next instruction is being fetched. I.e. the current instruction was fetched during the previous instruction s execution. This allows the instruction to execute in only one instruction cycle.

Separate Memory Conception of Harvard Architecture (ATmega16) Figure: Memory space for 8-bit MCU ATmega16. Program memory is Flash type. Data memory is SRAM (Static Random Access Memory): 32 general purpose registers, 64 I/O registers, internal/external memory RAM. Date memory is also EEPROM type (Electrically Erasable Programmable Read-Only Memory).

CISC versus RISC There are two basic types of processor designed philosophies: CISC (Complex Instruction Set Computer), RISC (Reduced Instruction Set Computer). In the 1970s and early 1980s, processors predominantly followed the CISC designed. The current trend is to use the RISC philosophy. One factor of the popularity of CISC in the 1970s was the high price (mid-1970s: 16 KB $500) and small capacity of memory. So there was a need to minimize the amount of memory required to store a program. CISC systems use complex instructions (e.g. instruction that copies an element from one array to another and automatically updates both array subscripts). RISC systems use only simple instructions (e.g. adding of two integers). Required operands are in the processor s internal registers, not in the main memory.

CISC Processors Table: Percent occurrence of operation types in common source codes. Operation Percent occurrence Memory loading 27.3 % Conditional jump 13.7 % Memory storing 9.8 % P 50.8 % Values comparison 6.2 % Address loading 6.1 % Subtraction 4.5 % Character insert 4.1 % Addition 3.7 % P 75.4 %

RISC Processor Instruction Set Op code (instruction structure) of instruction ADD Rd, Rr (Rd=Rd+Rr): 0000 11rd dddd rrrr d {0; 31} 1st operand, result r {0; 31} 2nd operand Op code of instruction INC Rd (Rd=Rd+1): 1001 010d dddd 0011 d {0; 31} 1st operand, result

Development of Microcontrollers Applications There are three basic methods how to program the target applications for a MCU: First approach is to write an entire code in C language. The using of high-level language brings to user the fast development possibilities and high code portability. With taking advantage of effective optimizing tools of development environment, the compiled application could be optimized by speed and/or size criteria. The opposite approach uses the programming in low-level assembly language by particular MCU instructions. By assembly programming approach, the absolute control of program flow and the functional units loading is guaranteed. Combination of both assembly and C code approaches. The microprocessor is controlled by program, i.e. by succession of instructions stored in binary form. Instructions are stored in program memory (Flash type in AVRs); all instructions are read and executed in sequential (successive) order. In microprocessor technique, instructions contains double information: (1) What kind of operation should be executed (op code), (2) Operands address. Each type of microcontrollers use different instruction set, i.e. there is no single instruction set for all manufactured microcontrollers.

Source Code Translation Figure: Process of source code translation. Control unit of microcontroller works with instructions in binary form machine language (16-bit words for AVRs). Compose applications in machine code is extremely ineffective, complicated, illegible the assembly code is used. Process of translation into machine language is supported by assembler replace each instruction with binary succession according the defined rules.

Source Code Example Registers 1.include <m16def_mod.inc> ; i n c l u d e m o d i f i e d d e s c r i p t i o n f i l e f o r ATmega16 2 3 l d i r16, 0 x0a ; r16 = 0a ( hex ) 4 l d i r17, 12 ; r17 = 12 ( dec ) 5 6 mov r18, r16 ; r18 < r16 7 add r18, r17 ; r18 = r18 + r17 8 sub r16, r17 ; r16 = r16 r17 9 10 loop : ; f o r e v e r l o o p 11 rjmp loop ; jump to loop l a b e l

Programming in Assembly Language Program stored in program memory is commonly displayed in hexadecimal system. Source code could contains 4 types of entry: (1) [label:].directive [operands] [; comments] (2) [label:] instruction [operands] [; comments] (3) ; comments (4) empty line Notation [ ] represents optional entry. Label is a symbolic identification of memory position ends by colon.

Assembler Directives (for AVRs) (1) [label:].directive [operands] [; comments] Assembler-Directives control the assembler process and do not create any own code. The leading dot must be in column 1 of the line. Most frequent using of directives: Specifying memory type for code storing (.cseg,.dseg,...), Macro definition (.macro,.endmacro), Variable definition (.def,.equ,.set), Files including (.include),... Directive Description --------------------------------------------------------------------------.byte Byte allocation in data segment (SRAM memory).cseg Assemble to the program segment (Flash memory).db Inserts one or more constant bytes in the code segment.def Register definition.device Defines the type of the target processor.dseg Assemble to the data segment (SRAM).dw Insert a binary word in the code segment.endmacro End of the macro.equ Defines a symbol and sets its value.eseg Assemble to the EEPROM-segment.exit End of the assembler-source code (stops the assembling process).include Inserts the content of another source code file.list Switches the listing to the.lst-file on.listmac Macros will be listed in the.lst-file.macro Beginning of the macro.nolist Switches the output to the.lst-file off.org Defines the address, where the assembler assembles to.set Fixes the value of a symbol

Part of Definition File m16def mod.inc 1 ; ***** S p e c i f y D e v i c e 2.device ATmega16 3 4 ; ***** I /O R e g i s t e r D e f i n i t i o n s 5.equ SREG =$3f 6.equ SPH =$3e 7.equ SPL =$3d 8.equ OCR0 =$3c 9.equ GICR =$3b ; New name f o r GIMSK 10... 11 12 ; ***** PORTB ************************ 13 ; PORTB Port B Data R e g i s t e r 14.equ PORTB0 = 0 ; Port B Data R e g i s t e r b i t 0 15.equ PB0 = 0 ; For c o m p a t i b i l i t y 16.equ PORTB1 = 1 ; Port B Data R e g i s t e r b i t 1 17.equ PB1 = 1 ; For c o m p a t i b i l i t y 18... 19 20.equ RAMEND =$45F 21... 22 23 ; ***** INTERRUPT VECTORS ************************************************ 24.equ INT0addr = 0x0002 ; External I n t e r r u p t Request 0 25.equ INT1addr = 0x0004 ; External I n t e r r u p t Request 1 26.equ OC2addr = 0 x0006 ; Timer / Counter2 Compare Match 27...

Using of Macro Directives Macros could be used for repetitious parts of source code. While the macro name is used inside the source code, it is replaced by instructions succession defined between directives.macro and.endmacro. Macro can use up to 10 parameters (operands), titled @0 @9. 1 ; a p p l i c a t i o n i n i t i a l i z a t i o n, i n c l u d i n g new macro d e f i n i t i o n 2.include <m16def_mod.inc> ; i n c l u d e modified desc. f i l e f o r ATmega16 3.macro ADD16 ; beginning od new macro t i t l e d ADD16 4 add @0, @2 ; add two l o w e r b y t e s 5 adc @1, @3 ; add two h i g h e r b y t e s ( with c a r r y ) 6.endmacro ; end o f new macro 7 8... 9 ; u s i n g t h e new macro i n code 10 ADD16 r16, r17, r18, r19 ; add two 16 b i t values Example of macro usage: ADD16 r16,r17,r18,r19 @0: r16, @1: r17, @2: r18, @3: r19 1 add R16, R18 2 adc R17, R19

Using of Macro Directives 1 ; a p p l i c a t i o n i n i t i a l i z a t i o n, i n c l u d i n g new macro d e f i n i t i o n 2.include <m16def_mod.inc> ; i n c l u d e modified desc. f i l e f o r ATmega16 3.macro SETPORTB ; beginning of new macro t i t l e d SETPORTB 4 l d i r16, @0 ; l o a d f i r s t macro p a r a m e t e r 5 out DDRB, r16 ; s e t d i r e c t i o n o f p o r t B 6 l d i r16, @1 ; l o a d second macro p a r a m e t e r 7 out PORTB, r16 ; s e t data o f p o r t B 8.endmacro ; end o f new macro 9 10... 11 ; u s i n g t h e new macro i n code 12 SETPORTB 0xff, 0 x11110000 ; s e t p o r t B Example of macro usage: SETPORTB 0xff, 0b10101010 This macro contains two input parameters: 0xff (assembler works with in via symbol @0 ) and 0b10101010 (@1). In process of preprocessing, the new defined macro SETPORTB will be replaced by following code: 1 l d i r16, 0 xff 2 out DDRB, r16 3 l d i r16, 0 b10101010 4 out PORTB, r16

Programming Model Definition (Programming model) Programming model of microcontroller is description of memory space, available registers, addresses and functions the programmer could used. Memory space (AVRs) Separated memory space for program and data (Harvard architecture), Internal and external address space, ATmega16: Flash (8k 16), SRAM (1k 8), EEPROM (512 8). SRAM: 32 general purpose registers (R0 R31), 64 I/O registers for controlling internal peripherals, and data memory. EEPROM: longer access time than SRAM, stored data rest in memory after the supply voltage disconnection, (constant storage, conversion table, settings, etc.).

I/O (Control) Registers of AVR I/O registers are used for internal peripheries and MCU core control. Most important registers for programmers. For ATmega16 the I/O registers are mapped from 0x20 to 0x5F addresses. Access to I/O registers are possible via IN and OUT instructions. Table: Selected I/O AVR Registers Address Name Description... 0x39 PINA Port A Input Pins Address 0x3A DDRA Port A Data Direction Register 0x3B PORTA Port A Data Register... 0x52 TCNT0 Timer/Counter 0 (8 Bits)... 0x5B GICR General Interrupt Control Register 0x5C OCR0 Timer/Counter 0 Output Compare Reg. 0x5D SPL Stack Pointer (low byte) 0x5E SPH Stack Pointer (high byte) 0x5F SREG Status Register

Types of Instructions (2) [label:] instruction [operands] [; comments] Instructions could be divided into: Arithmetical operations (addition, subtraction, incrementation,...), Logical operations (AND, XOR,...), Jump operations (unconditional/conditional branching, subroutines calling,...), Data movement operations (between registers, read/write from/to memory,...), Binary operations (set/clear individual bits, swap nibbles,...), Control instructions (nop, sleep, watchdog reset,...). For AVR (ATmega16) there are 131 instructions. Detailed information could be found in AVR instruction set manual.

Arithmetical/logical Operations (AVRs) Instr. Operands Description Operation Flag Cycles ---------------------------------------------------------------------------- ADD Rd, Rr Add two Registers Rd=Rd+Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd=Rd+Rr+C Z,C,N,V,H 1 SUB Rd, Rr Subtract two Registers Rd=Rd-Rr Z,C,N,V,H 1 AND Rd, Rr Logical AND Registers Rd=Rd^Rr Z,N,V 1 OR Rd, Rr Logical OR Registers Rd=RdvRr Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd=RdxorRr Z,N,V 1 COM Rd One s Complement Rd=$FF-Rd Z,C,N,V 1 NEG Rd Two s Complement Rd=$00-Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd=RdvK Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd=Rd^($FF-K) Z,N,V 1 INC Rd Increment Rd=Rd+1 Z,N,V 1 DEC Rd Decrement Rd=Rd-1 Z,N,V 1 TST Rd Test for Zero or Minus Rd=Rd^Rd Z,N,V 1 CLR Rd Clear Register Rd=RdxorRd Z,N,V 1 SER Rd Set Register Rd=$FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0=RdxRr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0=RdxRr Z,C 2......

Jump Operations (AVRs) Instr. Operands Description Operation Flag Cycles ---------------------------------------------------------------------------- RJMP k Relative Jump PC=PC+k+1 None 2 IJMP Indirect Jump to (Z) PC=Z None 2 JMP k Direct Jump PC=k None 3 RCALL k Relative Subroutine Call PC=PC+k+1 None 3 ICALL Indirect Call to (Z) PC=Z None 3 CALL k Direct Subroutine Call PC=k None 4 RET Subroutine Return PC=STACK None 4 RETI Interrupt Return PC=STACK I 4 CPSE Rd, Rr Compare, Skip if Equal None 1/2/3 CP Rd, Rr Compare Rd-Rr Z,N,V,C,H 1 CPC Rd, Rr Compare with Carry Rd-Rr-C Z,N,V,C,H 1 CPI Rd, K Compare Register with Immediate Z,N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set None 1/2/3......

Data Movement Operations (AVRs) Instr. Operands Description Operation Flag Cycles ---------------------------------------------------------------------------- MOV Rd, Rr Move Between Registers Rd=Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd=Rr+1:Rr 1 LDI Rd, K Load Immediate Rd=K None 1 LD Rd, X Load Indirect Rd=(X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd=(X), X=X+1 2 LDD Rd, Z+q Load Indirect with Displacement Rd=(Z+q) None 2 LDS Rd, k Load Direct from SRAM Rd=(k) None 2 ST X, Rr Store Indirect (X)=Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X)=Rr, X=X+1 2 STS k, Rr Store Direct to SRAM (k)=rr None 2 LPM Load Program Memory R0=(Z) None 3 LPM Rd, Z Load Program Memory Rd=(Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd=(Z), Z=Z+1 3 SPM Store Program Memory (Z)=R1:R0 None - IN Rd, P In Port Rd=P None 1 OUT P, Rr Out Port P=Rr None 1 PUSH Rr Push Register on Stack STACK=Rr None 2 POP Rd Pop Register from Stack Rd=STACK None 2......

Binary Operations (AVRs) Instr. Operands Description Operation Flag Cycles ---------------------------------------------------------------------------- SBI P,b Set Bit in I/O Register I/O(P,b)=1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)=0 None 2 LSL Rd Logical Shift Left Z,C,N,V 1 LSR Rd Logical Shift Right Z,C,N,V 1 ROL Rd Rotate Left Through Carry Z,C,N,V 1 ROR Rd Rotate Right Through Carry Z,C,N,V 1 ASR Rd Arithmetic Shift Right Z,C,N,V 1 SWAP Rd Swap Nibbles None 1 BSET s Flag Set SREG(s)=1 SREG(s) 1 BCLR s Flag Clear SREG(s)=0 SREG(s) 1 BST Rr, b Bit Store from Register to T T=Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)=T None 1 SEC Set Carry C=1 C 1 CLC Clear Carry C=0 C 1 SEN Set Negative Flag N=1 N 1 CLN Clear Negative Flag N=0 N 1 SEZ Set Zero Flag Z=1 Z 1 CLZ Clear Zero Flag Z=0 Z 1 SEI Global Interrupt Enable I=1 I 1 CLI Global Interrupt Disable I=0 I 1......

Control Operations (AVRs) Instr. Operands Description Operation Flag Cycles ---------------------------------------------------------------------------- NOP No Operation None 1 SLEEP Sleep None 1 WDR Watchdog Reset None 1 BREAK Break For On-Chip Debug Only None N/A......

Example of Arithmetical Operations Example Implement following equation y = a 2 + 2ab + b 2 Solution Help: op code of instructions for multiplication and addition: MUL Rd, Rr (R1:R0 = Rd x Rr) op code: 1001 11rd dddd rrrr ADD Rd, Rr (Rd = Rd + Rr) op code: 0000 11rd dddd rrrr

Source Code Example Arithmetical Operations 1.include <m16def.inc> ; d e s c r i p t i o n f i l e f o r ATmega16 2.def temp = R16 ; s y m b o l i c name f o r r e g i s t e r R16 3.def a = R17 ; s y m b o l i c name f o r r e g i s t e r R17 4.def b = R18 ; s y m b o l i c name f o r r e g i s t e r R18 5 6 LDI a, 0 x05 ; a = 5 7 LDI b, 6 ; b = 6 8 9 MUL a, a ; R1 : R0 = a x a 10 MOV temp, R0 ; temp < R0 11 MUL a, b ; R1 : R0 = a x b 12 LSL R0 ; R0 = 2 x R0 13 ADD temp, R0 ; temp = temp + R0 14 MUL b, b ; R1 : R0 = b x b 15 ADD temp, R0 ; temp = temp + R0 16 17 loop : ; f o r e v e r l o o p 18 RJMP loop ; jump to l o o p Machine language of source code example: Address Mach.lang. Instruction ----------------------------------------- +00000000: E015 LDI R17,0x05 +00000001: E026 LDI R18,0x06 +00000002: 9F11 MUL R17,R17 +00000003: 2D00 MOV R16,R0 +00000004: 9F12 MUL R17,R18 +00000005: 0C00 LSL R0 +00000006: 0D00 ADD R16,R0 +00000007: 9F22 MUL R18,R18 +00000008: 0D00 ADD R16,R0 @00000009: loop +0000000A: CFFF RJMP PC-0x0000