Thermal Management for Low Cost Consumer Products

Thermal Management for Low Cost Consumer Products TI Fellow Manager: Advanced Package Modeling and Characterization Texas Instruments rvin@ti.com

Outline The challenges Stacked die, Package-on-Package, TSVs Cost constraints Common Issues Dumping too much heat into the PCB Thermally unaware design Poor instrumentation for thermal measurements Hot spots Requirements Education System simulation New spreading techniques Gaps Commercial cooling schemes Materials Thermal interface theory Summary

The Challenges Portable devices moving towards ever more compact electronics Stacked die + TSVs Stacked packages Embedded die Concentrates heat locally, drives up power density Is this an issue? Phones run 1-3 watts Can compress all circuits into one module Cooling 2-3 watt package without heat sink is challenging Top Die Spacer Bottom Die Spacer

The Challenges Low cost package types don t offer many routes for heat spreading away from die 1 or 2 layers of routing only Stacked packages have difficulty getting heat to PCB from top package Thin die have more hot spot issues than thicker die WSPs create very localized hot spots on PCBs Dies of highest concern: Battery charger die RF power amplifiers (PA) SOCs

The Challenges To optimize stacked die thermal performance, conduction paths to the PCB must be optimized Largest die must go on bottom of package for best thermal performance Large die acts as a heat spreader to get heat to solder balls and PCB With good die spacer thermal conductivity, high power die can be on top or bottom When the largest die is on the bottom, package thermal performance will be nearly the same as a single die package with the same large die Theta-ja and Theta-jb will be barely changed Theta-jc might go either way, depending on die thickness and die sizes in the package Theta-jc is a don t care for most portable applications Stacking adhesives should be void free for optimal thermal conduction System problem: Stacking die results in higher power density than single die package Higher junction temperature will result Need better thermal spreading in PCB Top Die Spacer Moving thermal balls to beneath edge of Bottom Die chip improves thermal performance over a center-only array

The Challenges To optimize stacked package thermal performance, thermal conduction through the stack must be maintained The top packages will not conduct heat into the PCB as effectively as bottom package Thermal balls not possible for top packages Thermal performance of top packages will degrade Adhesive between packages can provide relief The thermal performance of the bottom most package will look largely the same as if attached to PCB alone This generalization assumes heat sinking was not the plan Assumes zero heat generation in packages on top The best system design is to put high power die in the bottom package for best thermal conduction into PCB Thermal performance of stacked packages is somewhat worse than for a stacked die approach with the same die compliment Best practice modeling should include Cu conductor details of package True of almost every package type

The Challenges TSV Devices: Thermally similar to stacked die packages for lower power portable/consumer applications Positives: Cu TSV ~4x higher thermal conductivity than Si Possibility of cooling very local hot spots by conducting heat to underlying die Direct electrical coupling to underlying die also gives direct thermal conduction to underlying die Direct electrical coupling to substrate improves conduction to PCB Negatives: Thinner die = hotter hot-spots Vertical TSVs don t offer lateral heat spreading to make up for thinner die Top Die Bottom Die

The Challenges Cost: Customers are sensitive to every 0.2 cents increase in part or system cost Example: Assume 1 billion cell phones sold per year $0.002 * 1 billion = $2M Mitigating factors: Some products are less cost sensitive Performance line products such as Iphone or Nokia N85 Advances in technology which enhance product fashion seen as desirable Form factors Design features Special functions

Common Issues: Power Density on PCB Cross section of POP mounted on cell phone PCB with top and bottom component configurations Where is the power to go? Temperature Rise vs. Power vs. PCB Size 80 http://www.ednjapan.com/content/issue/2006/02/pulse/pulse04.html Temperature Rise ( C) 70 60 50 40 30 20 10 3 x 3 cm 4 x 4 cm 5 x 5 cm 0 0 0.5 1 1.5 2 2.5 Uniformly Distributed Power (W)

Common Issues: Using Theta-ja Thousands of electronic component engineers still depend on the JEDEC Theta-ja for system level thermal design! They are wrong: Theta-ja is dependent on the PCB & system T j = T ambient + ( Power θ ) ja JEDEC Theta-ja is only predictive for the JEDEC test system Single Pkg on PCB Max T = 69.8 C Separation=50mm Max T = 81.6 C Separation=8mm Max T = 98.4 C Example: error to old θ ja technique = 28.6 C

Common Issues: System Thermal Design is a Requirement System thermal design is no longer optional ignoring system thermal design can result in non-functionality or poor reliability Not enough co-design occurring Chip designs don t comprehend package/system boundary conditions Many modern chips are thermally aware but might not be implemented by users Package designers only put out JEDEC type parameters Theta-ja, Theta-jc, Theta-jb, etc., not compact models System level designers don t get hold of critical information Package thermal characteristics for their particular part and die size Appropriate package models for stacked die and MCMs Small design houses don t have resources for in-house thermal design Design subcontractors are available System failures due to thermal overloads have and will occur Early X-boxes, recent law suits against Dell, etc.

Common Issues: Poor Measurements Thermocouple measurements are misleading: Thermocouples act to heat sink the surfaces The smaller the die/package, the more difficult it is to measure the package surface temperature Models show measured case temperatures can easily be off by 30 C due to thermocouple! TC gauge Surface Temp Junction Temp none 104 105 36 70.3 99.9 40 78.6 102 No Thermocouple 105 C junction 104 C modeled case temp Thermocouple, 100 C junction 70 C measured case temp Difference is due to heat sinking down the thermocouple

Common Issues: Hot Spot Design Thinner die increase spreading resistance Hot spots get hotter Can reduce impact of hotspot by attaching die directly to high thermal conductivity spreader such as Cu plate Cost issue Possible reliability issue Hot Spot Temperature Rise vs. Spot Area Temperature Rise ( C) 20 15 10 5 0 0 10 20 30 40 50 Spot Area (mm**2) Exposed Pad Package 380um Thick Chip in CSP 150um Thick Chip in CSP

Common Issues: Hotspot Design Hotspots + thin die imply need for package/chip codesign In stacked die packages, hot spots on one die can create hotspots on another Die thermal design tools need to comprehend die-to-die interactions Don t cluster hotspots Spreading hotspots apart allows heat spreading from individual hotspots over wider areas, increasing conduction from each hot spot Applies to die and PCB design If only one hotspot, center of die is better than corner of die Allows maximum heat spreading Keep hotspots out of corners A hotspot in a corner blocks heat flow in 3 directions

Common Issues: Hotspot Design Center is better than corner for single hotspot 0.5x0.5 mm hotspot; 2 design placements 38% difference Center Spot Max. Temp. = 62 C Theta-ja = 37 C Corner Spot Max. Temp. = 76 C Theta-ja = 51 C

Common Issues: Hotspot Design With multiple hotspots, sweet location is somewhere in between 1 2 3 4 Worst Design 1 2 3 4 Better Design Temperature ( C) 1 2 3 4 Best Design 0.25x0.25mm Hotspot Temperature 64 vs. Distance From Center 62 60 Sweet Spot 58 56 54 0 1 2 3 4 Distance from Die Center (mm)

Hotspot Reliability Implications Device reliability is a linear function of the active die area and is exponential with temperature Small hotspots will have minor impact on reliability Large hotspots will have major impact on reliability Higher temperature spots will have large impact on reliability, regardless of size Typical reliability issues: Electromigration Hot electron effects Kirkendall voiding in Au/Al wire bonds Reliability and functionality need to be characterized at the temperatures the hotspots will reach

System Simulation: The 2R Model 2-Resistor modeling: A θ ja Replacement θ jc = thermal resistance to case θ jb = thermal resistance to PCB Junction = heat insertion node Ambient Node Ambient R a Surface Node θ jc R Junction θ jb R PC Board Representation of Single Package to PCB J1 J2 J3 J4 J5 PC Board PCB to Ambient Thermal Coupling of Multiple Pkg s on PCB

System Simulation: The Compact Model Compact models give higher accuracy than 2- resistor approach Industry accepted accuracy with good models = 5% Compact models are virtual representations of package Delphi compact models are the most common JEDEC is working to standardize compact model accuracy reporting

Modeling Challenges for SIP, POP, TSVs No standard compact model topologies for stacked die or stacked packages Present compact models don t include hot spots In suggested model, compact model topology changes dependent on which die is largest Inter-die resistance represented Potential Stacked Die Topology - modification of standard QFP compact model Die 2 Inter Die Resistance Die 1 Top 1 Side Top 2 Bottom 2 Bottom 1

Modeling Challenges for SIP, POP, TSVs Stacked packages may be represented with stacked compact models The best current solution: Use fully detailed models Standard package compact model Stacking of compact models Thermal Shunts (Shorts)

Solutions: Education System design engineers can t neglect thermal design Many don t know this! System design engineers need tools: Knowledge to fill in thermal design gaps High levels of EDA Automation so they can do more with less Tools need to easily import multiple data formats Thermal modeling tools must be able to appropriately model the important thermally conducting traces

Solutions: Compact System Optimizations Optimizations: Vents: even on portable devices Heat spreaders molded into plastic chassis boxes Conduction enhancements from PCB to box screws, gap fillers Phase change materials to absorb transient thermal events Low speed fans for portable devices In hot PCB s, thermally partition PCB s to isolate devices with lower allowed operating temperatures from those with higher Gap Filler or Phase Change low speed fan Chassis Chassis Chassis Screw Heat Spreader

Solutions: Compact System Optimizations Piezoelectric Bimorph Infraso nic fans Ultraso nic fans Piezoelectric Fans Heat Pipe Applications

Solutions: Cooling Ideas for Stacked Packages Al or Cu Spreader Soldered Connection Top Hat Spreader for Stacked Packages Plastic Case Gap Filler Metallized Case Gap Filler Conduction to Chassis

Solutions: Package Enhancements Embedded die with thermal conduction to thermal balls (Tjmax = 118 C) Embedded die with top and bottom thermal conduction in trace (Tjmax = 117 C) Embedded die with top and bottom thermal conduction in traces and to shield on top of overmolding (Tjmax = 115 C) Embedded die with top and bottom thermal conduction in traces and to shield on top of overmolding. The shield is soldered to module perimeter (Tjmax = 112 C) All of the above with another RF shield over the module which is soldered to the PCB and has gap filler to the module (Tjmax = 93 C)

Solutions: Cooling Ideas for SOPs - Spreaders

Solutions: Detailed Modeling When modeling portable devices, multiple thermal boundary conditions must be included Handheld Operating in case Operating on a table Example: typical CSP device in cell phone Jedec 2s2p No Hand Hand 36.7 C/W 74.5 C/W 18.2 C/W When held in the hand, a portable device is liquid cooled There is a limit to the power which can be comfortably dissipated by a portable device into the hand To extend beyond this limit, rejection of heat to the air is required

Solutions: Modeling, Including the Hand Hand is modeled as block of fat Exterior of fat held at body temperature, 37.1 C

Solutions: Modeling Including the Hand Good correlation to experiment achieved Still air box measurement Operation mode measurement Courtesy: M. Naeshiro (TTC)

Solutions: Smart Design Get Hotter: Higher maximum junction temperature ratings allow easier thermal design Challenge: high temperature with low leakage Get Smarter: Understanding the life usage thermal profile allows tuning of thermal solution vs. reliability A system specified at 125 C continuous operation may allow 300 hrs at 150 C with good reliability Design system for reliability goals, not just maximum temperature Must insure system functions at hottest temperature Time (hrs) f 15000 10000 5000 0 Life Usage Profile -100 0 100 200 Temperature (C) total FIT rate* Step 2 3 4 5 6 7 ( T ) = f ( T ) Temp. 65 95 120 135 150 155 n mechanisms Duration (Hours) 6000 12000 6000 1000 300 10 * Product Specific n FITS 0.0003 0.7 5 35 75 10 125

Gaps: Thermal Management Needs For high power arena (limited volume) TIM s with k effective better than solder (>50 W/m- C) Including thermal interfacial resistance Mechanical reliability a given Reliable liquid or refrigerant cooling Includes micro-channel heat exchanger For portable and consumer electronics (high volume) Inexpensive passive cooling schemes: Passive liquid convection cooling Higher thermal conductivity PCB materials (>50 W/m- C) High thermal conductivity plastic case materials Recent announcement made by NEC More spreaders molded into cases High conductivity couplings between PCB s and cases Inexpensive improved efficiency heat sinks Entrained air flow, turbulent generators, etc.

Gaps: Thermal Management Needs Modeling directions Higher levels of automation Chip, package, system codesign Hot spot analysis integrated with circuit simulation Better use of parallel processing PCB traces modeled in detail on PCB Die metallization temperature modeled in detail vs. current Accurate modeling of thermal interfacial resistances Based on material composition

Summary Portable devices are offering thermal challenges Stacked die (with/wo TSV) and stacked packages increase power density thinned die have potential hot spot issues Hotspots may need to be analyzed for thin die, even in portable applications Multiple environments must be considered when performing thermal design of a system New cooling schemes are on the way to handle higher power densities in portable systems Thermal lifetime application profiles should be used to estimate device reliability rather than maximum operating temperatures