Nano Architectures for Carbon Nanotube Circuits: Design, Analysis, and Experimental Attempts Extended Abstract Eugen Czeizler, Tuomo Lempiäinen, Pekka Orponen Department of Information and Computer Science, Aalto University Recent years have witnessed a burst of experimental activity concerning algorithmic self-assembly of nanostructures, motivated at least in part by the potential of this approach as a radically new manufacturing technology. Our specific interest is in the self-assembly of Carbon-Nanotube Field Effect Transistor (CNFET) circuits. Our research is focused on developing a new theoretical foundation for the design and analysis of CNFET circuits, as well as the derived algorithmic self-assembly problems which follow from making such systems experimentally achievable. Our approach is based on four inter-related research directions, each covering a different aspect of this ambitious goal. A design framework for CNFET circuits We propose a novel high-level design framework for self-assembling CNFET circuits. According to this methodology, the elements of the circuits, i.e., CNFETs and the connecting carbon nanotube wires, are affixed on different rectangular nano-scaffolds and selfassemble into the desired circuit. The underlying scaffold structures are all constructed from folded DNA molecules using the DNA origami method introduced by Rothemund [12]. In our work we were able to generate a universal set of 14 functionalised DNA origami tiles from which, with a proper selection of glues on the tiles, any desired CNFET circuit can be self-assembled. Experimental fabrication and assembly of DNA origami tiles Together with our colleagues from the Dept. of Applied Physics, Aalto University, we are working towards an actual experimental implementation of our design methodology. We have generated algorithmic designs for DNA tiles, capable of further self-assembly, in a highly controlled manner, into large fully addressable scaffolds, see Figure 1. Computational modeling of the ktam We propose a new framework for the computational modelling of the kinetic Tile Assembly Model (ktam), based 1
Figure 1: AFM images of DNA-origami tiles assembled on a horizontal ribbon pattern on agent- and rule-based modelling representations. This tile-based mathematical abstraction is the de-facto modelling framework for many of the current DNA based self-assembly applications. Moreover, this model is also the most appropriate abstraction for the self-assembly of our CNFET circuit components. So far, only computational approximations of the ktam have been possible, using a customized implementation of the Stochastic Simulation Algorithm (SSA). In our research we use agent- and rule-based modeling methodology in order to perform correct and complete computational simulations for the ktam. The Patterned self-assembly Tile set Synthesis (PATS) problem Within the ktam framework, we tackle the problem of finding an optimal number of glues (and tiles) which would derive the self assembly of any given pattern. Moreover, using numerical formulas derived from the ktam model, we undertake the problem of finding the most reliable tile designs, which would ensure the self-assembly of the desired pattern with the highest possible probability. In the following we concentrate on the first of the above research directions. A Design Framework for Carbon Nanotube Circuits Affixed on DNA Origami Tiles SWNT and DNA as elementary nanomaterials Single-wall carbon nanotubes (SWNTs) can be fabricated either metallic (m) or semiconducting (s). A cross-junction between an m- and s-type SNWTs generates a structure with field effect transistor (FET) behavior [9], [3]. In this way, both p-type and n-type FETs are realizable (a p-type FET is ON when input is 0, while an n-type FET is ON when input is 1 ).
One of the presently most reliable self-assembling, programmable nanostructure architectures is DNA origami [12]. Several authors have announced the formation of DNA origami tiles, capable of further assembly into larger, fully addressable, 1D and 2D scaffolds [4, 7, 10, 1]. Such scaffolds make possible the construction of highly complex structures on top of them [8], prospectively including nanocircuits. Moreover, the CNFET structures described above can also be affixed on top of these DNA origami [5], [11]. CNFET circuits have been previously introduced on top of addressable DNA lattices [3]. While such large lattices (2 5 µm) are experimentally achievable, the uniformity of their structure as well as the fact that the entire circuit must assemble simultaneously, makes the functionalisation of the lattice difficult. In the present work, we propose a generic framework for the design of CNFET circuits comprising a universal set of 14 functionalised DNA origami tiles shown in Figure 2. The marks on the tiles indicate the arrangements of the CN s affixed on the respective DNA origami; with a proper selection of glues on the tiles, any desired CNFET circuit can be self-assembled from this basis. Figure 2: The 14 tile types and the blank tile, out of which any CNFET circuit can be assembled: a) p-type and n-type CNFETs, b) straight CNWs, c) corner CNWs, d)-e) 3- and 4-way CNW junctions, f) crossing but non-interacting CNWs, g) blank tile (used for analyzing fault tolerant architectures).. One advantage of this approach is that it decouples the self-assembly aspects of the manufacturing process from the transistor circuit design. It also supports efficient high-level analysis of the purported circuits, both by computer simulations and by analytical means. For instance, all assembly errors can at this level be treated as tiling errors, leading to a transparent design discipline for fault-tolerant architectures. In order to design a particular nanocircuit, one first prepares the transistor circuit design using the 14 basis tiles indicated. Then, an optimal number of glues for these tiles is computed, see e.g. [6, 2], and finally, appropriate sticky ends are designed for the DNA origami tiles. In Figure 3 we present the designs for a CMOS inverter and NAND gate. The inverter constitutes a 3 2 = 6 tile assembly and the NAND gate correspondingly a 4 4 = 16 tile assembly. To illustrate how our approach supports the design of fault-tolerant circuit architectures, let us assume that the CN acting as gate in a CNFET does not attach to the DNA origami. Then this tile will act as a vertical CNW tile. Similarly, if one metal nanoparticle is not attached to a 3-way junction CNW
Figure 3: a) The design out of DNA origami tiles of a) a CMOS inverter, and b) a CMOS NAND gate. tile, depending on its position, we will obtain either a corner CNW tile, or a straight CNW tile. In the worst case, if the functionalisation of a tile is highly altered, the tile can be considered blank. Based on the Quadded Transistor (QT) model [13], we have prepared several fault tolerant circuit designs. For instance, Figure 4 presents tiling designs for a QT transistor structure and a fault-tolerant CNFET CMOS inverter based on this. In both designs, if any one tile is replaced, the output of the entire device is still preserved. In a similar way, fault-tolerant designs for more complicated devices such as CMOS NAND and NOR gates can be achieved. Figure 4: a) Implementation of the QT structure. b) A fault tolerant inverter; even if several tiles have errors, the gate is still giving the correct output.
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