CHARGE pumps are the circuits that used to generate dc

INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 27 A Charge Pump Circuit by using Voltage-Doubler as Clock Scheme Wen Chang Huang, Jin Chang Cheng, and Po Chih Liou Abstract A new charge pump circuit with a clock that shows an increased clock voltage as its stage is increased is proposed in the paper. The charge pump circuit utilizes the cross-connected NMOS, voltage doubler, as a pumping stage. Each stage of the voltage-doubler provides a pair of complementary clock voltages. The clock voltage also increases as the stage of voltage doubler is increased. It shows that a voltage up to 37.85V was obtained after eight-stage s pumping of the circuit, through the simulation of HSpice under 0.35 um process with 2V of supply voltage and clock voltage. Index Terms Charge pump, high voltage clock generator, voltage doubler. Fig. 1. Four-stage Dickson charge pump. I. INTRODUCTION CHARGE pumps are the circuits that used to generate dc voltages those are higher than the normal power supply voltage or lower than the ground voltage of the chip. Charge pumps have been used in the nonvolatile memories, such as EEPROM or flash memories, to write or to erase the floatinggate devices [1, 2]. They can also be used in the low-supplyvoltage circuits and switched-capacitor systems that require high voltage to drive the analog switches [3]. Analog circuitry also requires efficient charge pump to augment the internal voltage supplies in order to achieve the increased dynamic range and simplify the design [4]. The charge pump circuit reported by Dickson had been widely used for generating high voltages [5, 6] and in some circuit application. The structure of the circuit makes use of capacitors, which are interconnected by diodes and coupled in parallel with two non-overlapping clocks. Diodes in the Dickson circuit can be replaced by NMOS, which will result a more practical implementation [7]. Fig. 1 shows a four-stage Dickson charge pump circuit. However its performance is limited due to the threshold voltage drop of the NMOS devices and the reverse charge-sharing phenomenon. Moreover, for high output generated voltages, the increase in the threshold voltage due to the body effect can significantly reduce the pumping efficiency. In order to overcome the problems mentioned above in the Dickson charge pump, a charge pump, called NCP-2 [8], is reported which utilizes the charge transfer switches (MSi transistors). Each of the MSi transistors is controlled by the pass transistors MNi (nmos) and MPi (pmos). In that way the charge transfer switches can be turned off completely when required, preventing the reverse charge flow. Also they can be W. C. Huang and P. C. Liou are with the Department of Electronic Engineering, Kun Shan University, Tainan, Taiwan R.O.C. J. C. Cheng is with the Department of Accounting and Information System, Chang Jung Christian University, Tainan, Taiwan R.O.C. turned more effectively by the high voltage generated in the next stage. More complicated circuit scheme for charge pump have been applied to increase the voltage gain, such as all PMOS charge pump for low voltage operation [9], CMOS charge pump [10], charge transfer switches in combination with pumping the output stage clock of enhanced voltage amplitude. In our previous studied, we proposed a voltagedoubler charge pump circuit (VDCP) by cascading multistages of voltage-doubler [11], and the charge pump circuit by using multi-staged voltage-doubler as the clock scheme (MVDCP) [12] as shown in Fig. 2. Both these two charge pump circuits showed high efficiency of pumping voltage. The basic structure of the MVDCP is based on a chained of MOS-diode which combined with pumping capacitor. And each stage of the capacitor is pumped by a serial of clock voltage. The pumping clock of a multi-staged voltage-doubler is designed to replace the traditional clock. The supply voltage is constant at V DD. The input clock voltage of the first stage is also constant at the same as the supply voltage, V DD. The MVDCP shows high pumping efficiency while it also shows the deficiency of large transistor counts. At the aim of reducing the transistor counts, we present another version of MVDCP which called MVDCP-2. The clock, multi-staged voltage-doubler, shows the characteristic of out of phase in its two outputs. So, each stage of the clock can provide clock voltage for two stages of the transfer transistor. The number of transistors of MVDCP-2 is greatly reduced as it was compared with the MVDCP-1. The operation principle and the simulation results will be discussed in the following sections.

INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 28 II. PROPOSED NEW CHARGE PUMP CIRCUIT : MULTI-STAGED VOLTAGE-DOUBLER CHARGE PUMP CIRCUIT-2 (MVDCP-2) The proposed charge pump circuit is shown in Fig. 3. A serial of MOS transfer diode with pumping capacitors are used to transfer charge. The multi-staged voltage-doubler is designed to be the pumping clock. Fig. 3 shows a fourstaged connection of the multi-staged voltage-doubled charge pump circuit (MVDCP-2). Compared with the MVDCP-1, each stage of the voltage-doubler provides two clock-voltages for two stages of the MOS-diode. While the structure of MVDCP-1, each of voltage doubler only providing one clockvoltage to one stage of MOS-diode. The operation of the high-voltage clock generator and the concept of multi-staged voltage doubler are discussed in section II-A. The simulation results and discussion of the proposed MVDCP-2 is stated in section II-B. Table 1 shows a comparison of the number transistor, pumping capacitor and load capacitor of the two circuits. Both the two circuits are four stages of pumping. It shows the number of transistor and capacitor of MVDCP-2 is greatly reduced. The fewer number of transistors and capacitors of MVDCP-2 will result in lesser area of chip size as it compared with MVDCP-1. TABLE I COMPONENTS COUNTS OF A FOUR STAGES CHARGE PUMP CIRCUIT Circuit Number of components Comments NMOS/PMOS/Int. Cap./Load Cap. MVDVP-1 22 / 9 / 12 / 1 One clock output MVDCP-2 12 / 5 / 8 / 1 Two clock outputs A. Multi-staged voltage-doubler clock generator The unit cell of the multi-staged voltage-doubler clock generator is a clock voltage doubler[8] as shown in Fig. 4. In the circuit, the amplitude of input clock voltage, V CLK, is oscillated between 0 to V DD. The power supply voltage is constant at the voltage value of V DD. As the clock is at high voltage value (V DD ), the nmosfet(m8) will be turn on and the output voltage of the inverter will be discharged to 0V. As the clock goes to low voltage value (0V), this will turn on the pmosfet (M7), because its gate voltage is 0V and its source voltage is 2V DD. The source voltage (2V DD ) of the transistor M7 will charge the output capacitor of the inverter. Eventually, the output node of the inverter becomes 2V DD. So, the value of V out4 oscillated between 0V to 2V DD during the action of clock. The left hand side of the circuit shows similar operation principle with opposite polarity. Fig. 2. The charge pump circuit by using multi-staged voltage-doubler as the clock scheme (MVDCP-1)[12]. Fig. 4. The circuit diagram of the clock voltage doubler. Fig. 3. The proposed charge pump circuit by using multi-staged voltagedoubler as clock scheme (MVDCP-2). There are two purposes of the produced output clock voltage of each stage in the MVDCP-2 circuit. Firstly, it is to be the pumping clock of the nmos diode in the chained of charge pump structure. Secondly, it provides clock scheme for the following stage of clock voltage-doubler to produce higher amplitude of clock voltage. The concept is realized by the circuit of MVDCP-2, as shown in Fig. 3. Now we discussed the multi-staged voltage doubler clock scheme first. In the clock scheme, voltage doubler is connected stage by stage. As the input clock goes from 0 to V DD, the left output of the first stage will go from 0 to 2V DD, the right output of the first stage will go from 2V DD to 0. The left output of the second stage will go from 3V DD to 0 and the right output of the second stage will go from 0 to 3V DD at steady state. By suitable connection, the above four output clock voltages are

INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 29 Fig. 5. The pumping voltage of various stages of MVDCP-2, where V DD =2V, V CLK =2V and f=25mhz in the circuit. Fig. 6. The pumping voltages of a four-staged MVDCP-2 at various simulation frequencies (@ V DD =2V, V CLK =2V). used to be the pumping clock of the chained of the nmos diode. The receiving of the pumping voltage of capacitor C 1, C 2, C 3 and C 4 will be 0V, 2V DD, 0V and 3V DD, respectively as the input clock is 0V. The receiving of the pumping voltage of capacitor C 1, C 2, C 3 and C 4 will be 2V DD, 0V, 3V DD and 0V, respectively as the input clock is V DD. The circuit scheme of MVDCP-2 shows smaller chip area as it compared with the circuit scheme of MVDCP. B. Simulation results of the multi-staged voltage-doubler charge pump circuit (MVDCP-2) A four-staged multi-staged voltage-doubled charge pump circuit (MVDCP-2) is shown in Fig. 3. The simulation result of the output voltage of each stage of the multi-staged voltagedoubler charge pump circuit (MVDCP-2) is shown in Fig. 5. Both the supply voltage V DD and the input clock voltage V CLK are 2V, and the operation frequency is 25MHz. This figure shows the output voltage vs. operation time of different output stages. The output voltage can reach to 4.21V after one stage of pumping. As the number of the stages is increased, the output voltage is increased steadily. For an eight-staged MVDCP-2, its output voltage can be pumped up to 37.85V. Fig. 6 shows the pumping voltage of a four-staged MVDCP- 2 at various operating frequencies. The operating frequency is varied from 25, 50, 100, 200 to 500MHz, respectively. A higher output voltage is obtained at low frequency operation. The operation frequency of 25, 50 and 100MHz of the circuit can pump similar output voltage. The output voltage degraded serious as the operation frequency increased to 200MHz. The pumping capacitor can be charged to a more saturated situation under low frequency operation. On the other hand, as the operating frequency is increased the charging of the pumping capacitor is reduced, so it resulted in a lower pumping voltage. A comparison of the pumping voltage of various charge pump circuits is discussed. The MVPCP-2 is compared with some other charge pump circuits, the MVDCP-1, the VDCP, the Dickson charge pump circuit [5] and NCP-2 [8] charge pump circuit. The output voltage vs. number of stages of various charge pump circuits, Dickson charge pump, NCP-2, VDCP, Fig. 7. A comparison of the pumping voltage of MVDCP-2, MVDCP-1, VDCP, NCP-2 and Dickson charge pump at different number of pumping stages. MVDCP-1 and MVDCP-2 is shown in Fig. 7. The results are the simulation of HSpice under CMOS 0.35 um process with V CLK =V DD =2V, the pump capacitor is 20pF, the load capacitor is 10pF and at the operating frequency of 25MHz. At each stage, the MVDCP-2 shows a lower output voltage than that of MVDVP-1 while much higher than that of another circuits. In the MVDCP-1, the pumping voltage is equal to 4.31V after one stage pumping, is equal to 31.09V after five stages pumping and is equal to 40.37V after seven stages pumping. The MVDCP-2 shows lower pumping voltages at the same simulation condition. The pumping voltage is equal to 4.21V after one stage pumping, is equal to 21.31V after five stages pumping and is equal to 34.28V after seven stages pumping. While, these results are much higher than that of the VDCP, the Dickson charge pump and the NCP-2. In this figure we also find that the Dickson charge pump and NCP-2 will saturate after many stages of pumping while the MVDCP-2 did not show any tendency for saturation. The pumping voltage can be increased more as the stages of the MVDCP-2 are increased. Fig. 8 compares the simulated output voltages of the Dickson, NCP-2, VDCP, and the new proposed charge pump

INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 30 Fig. 8. A comparison of the pumping voltage of MVDCP-1, MVDCP-2, VDCP, NCP-2 and Dickson charge pump at different supply voltage. circuits under different power supply voltages (V DD ) without output current loading. The output voltages are obtained after three stages of pumping of these circuits, respectively. The output voltages of these charge pump circuits are degraded when the power supply voltage is decreased. However, the new proposed charge pump circuit still has higher output voltages under the lower power supply voltage because the proposed charge pump circuit has better pumping efficiency. Thus, the proposed charge pump circuit is more suitable in low-voltage processes than the prior designs. Fig. 9 shows the simulated output voltages of the MVDCP-2, MVDCP-1, VDCP, NCP- 2 and Dickson charge pump under different output currents. When the output current is increased, the output voltages of these charge pump circuit are decreased. The output voltage is 7.75V, 5.95V, 4.7V, 3.7V and 2.4V, respectively, at the output current of 30 µa. The output voltages of the proposed charge pump circuit with different output currents are much higher than those of other charge pump circuits. Especially, with the higher output current of 50 µa, the proposed charge pump circuit still has the better pumping performance than others. In addition, the high pumping clock voltage in the new proposed charge pump circuit could fully turned on to transfer the charges, but all MOSFET switches in the Dickson charge pump circuit and NCP-2 are diode-connected transistors, which have the threshold voltage drop problem. Thus, the proposed charge pump circuit has better pumping performance. III. CONCLUSION The new version (MVDCP-2) of charge pump circuit by using multi-staged voltage-doubler as clock scheme is proposed. Although it shows lower pumping efficiency than the previous version (MVDCP-1) while the area of chip size is greatly reduced. The MVDCP-2 still shows much higher pumping voltage than another charge circuits. No saturation of the pumping voltage is found as the pumping stage increased. It also shows suitable application for low power supply system. Fig. 9. The output voltage vs. output current of the MVDCP-2, MVDCP-1, VDCP, NCP-2 and Dickson charge pump. ACKNOWLEDGMENT The authors would like to thank the National Science Council of the Republic of China, for financially supporting the research under Contract No. NSC-97-2221-E-168-004. The simulation software was support by CIC. REFERENCES [1] T. Tanzawa, T. Tanaka, K. Takeuchi, and H. Nakamura, Circuit technologies for a single-1.8 V flash memory, IEEE J. Solid State Circuits, vol.31, no.1, 2002, pp.84-89. [2] T. Kawahara, T. Kobayashi, Y. Jyouno, S. Saeki, N. Miyamoto, T. Adachi, M. Kato, A. Sato, J. Yugami, H. Kume, and K. Kimura, Bit line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories, IEEE J. Solid-State Circuits, vol.31, pp.1590-1600, Nov. 1996. [3] T. B. Cho and P. R. Gray, A 10 b, 20 M sample/s, 35 mw pipeline A/D converter, IEEE J. Solid-State Circuits, vol.30, 1995, pp.166-172. [4] R. St. Pierre, Low-power BiCMOS op amp with integrated current mode charge pump, IEEE J. Solid State Circuits, vol.35, no.7, 2000, pp.1046-1050. [5] J. F. Dickson, On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique, IEEE J. Solid State Circuits, vol.sc-11, No.3, 1976, pp.374-378. [6] T. Tanzawa and T. Tanaka, A dynamic analysis of the Dickson charge pump circuit, IEEE J. Solid State Circuits, vol.32, No.8, 1997, pp.1231-1240. [7] J. S. Witters, G. Groeseneken, H. E. Maes, Analysis and modeling of onchip high-voltage generator circuits for use in EEPROM circuits, IEEE J. Solid State Circuits, vol.24, No.5, 1989, pp.1372-1380. [8] J. T. Wu, K. L. Chang, MOS charge pumps for low-voltage operation, IEEE J. Solid State Circuit, Vol.33, No.4, 1998, pp.592-597. [9] N. Yan and H. Min, High efficiency all-pmos charge pump for lowvoltage operations, Elect. Lett., vol.42, no.5, 2006, pp.277-279. [10] Y. Moisiadis, I. Bouras and A. Arapoyanni, A CMOS charge pump for low voltage operation, Proc. IEEE International Symposium on circuits and systems, Geneva, 2000, pp.v577-v580. [11] W. C. Huang, J. C. Cheng and P. C. Liou, A charge pump circuit cascading high-voltage clock generator, Proc. IEEE International Symposium on Electronic Design, Test & Application, pp.332-337, 2008, Hong Kong SAR, China. [12] W. C. Huang, J. C. Cheng and P. C. Liou, A charge pump circuit using multi-staged voltage doubler clock scheme, Proc. International Conference on Microelectronics, pp.330-333, 2007, Cairo, Egypt.

INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 31 Wen-Chang Huang was born on February 16, 1967. He received the B.S. degree in electronics engineering from Tamkang University 1989 and the M. S.and Ph.D. degrees in electronic engineering from Chiao Tung University, Hsinchu, Taiwan in 1991 and 1996, respectively. From 1998 to 2003, he was an Assistant Professor at the Department of Electronic engineering, Ta Hwa Institute of Technology, Hsin Chu, Taiwan. From 2003 to 2005, he was an Assistant Professor at the Department of Electronic engineering, Kun Shan University, Tainan, Taiwan. He is currently an Associate Professor at the Department of Electronic engineering, Kun Shan University, Tainan, Taiwan. His current research is in the areas of thin films material, semiconductor device and VLSI design. Po-Chih Liu received the MS. degree from the Department of Electronic Engineering, Kun Shan University in 2007. He is currently an IC layout engineer, Synerchip Co. Ltd. Jin-Chang Cheng received the Ph.D. degree from the Department of Electrical Engineering, State University of New York at Stony Brook in 1986. He is now with the Department of Accounting and Information System, Chang Jung Christian University, Tainan, Taiwan, R.O.C.. His research interests include digital system design, digital signal processing and image processing.