OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

OCTAL E SHOT HAUL LINE INTEFACE UNIT IDT8V58 FEATUES Fully integrated octal E short haul line interface which supports Ω E twisted pair and 75 Ω E coaxial applications Selectable Single ail mode or Dual ail mode and AMI or HDB encoder/decoder Built-in transmit pre-equalization meets G.7 Selectable transmit/receive jitter attenuator meets ETSI CT/, ITU G.76, G.74 and G.8 specifications SONET/SDH optimized jitter attenuator meets ITU G.78 mapping jitter specification Digital/Analog LOS detector meets ITU G.775 and ETS ITU G.77 non-intrusive monitoring for in-service testing for any one of channel to channel 7 Low impedance transmit drivers with high-z Selectable hardware and parallel/serial host interface Local and emote Loopback test functions Hitless Protection Switching (HPS) for to protection without relays JTAG boundary scan for board test. V supply with 5 V tolerant I/O Low power consumption Operating temperature range: -4 C to +85 C Available in 44-pin Thin Quad Flat Pack (TQFP) and 6-pin Plastic Ball Grid Array (PBGA) packages Green package options available FUNCTIONAL BLOCK DIAGAM LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Analog Loopback Peak Digital Loopback emote Loopback AIS TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones G.77 Monitor Clock Generator Control Interface egister File JTAG TAP VDD IO VDDT VDDD VDDA MCLK OE CLKE MODE[:] CS/JAS SCLK/ALE/AS D/ SDI/W/DS SDO/DY/ACK INT LP[7:]/D[7:]/AD[7:] MC[:]/A[4:] TST TCK TMS TDI TDO Figure- Block Diagram IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. January, - Integrated Device Technology, Inc. DSC-68/

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT DESCIPTION The IDT8V58 is a single chip, 8-channel E short haul PCM transceiver with a reference clock of.48 MHz. The IDT8V58 contains 8 transmitters and 8 receivers. All the receivers and transmitters can be programmed to work either in Single ail mode or Dual ail mode. HDB or AMI encoder/decoder is selectable in Single ail mode. Pre-encoded transmit data in NZ format can be accepted when the device is configured in Dual ail mode. The receivers perform clock and data recovery by using integrated digital phase-locked loop. As an option, the raw sliced data (no retiming) can be output on the receive data pins. Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. A jitter attenuator is integrated in the IDT8V58 and can be switched into either the transmit path or the receive path for all channels. The jitter attenuation performance meets ETSI CT/, ITU G.76, G.74 and G.8 specifications. INDUSTIAL TEMPEATUE ANGES The IDT8V58 offers hardware control mode and software control mode. Software control mode works with either serial host interface or parallel host interface. The latter works via an Intel/Motorola compatible 8-bit parallel interface for both multiplexed or non-multiplexed applications. Hardware control mode uses multiplexed pins to select different operation modes when the host interface is not available to the device. The IDT8V58 also provides loopback and JTAG boundary scan testing functions. Using the integrated monitoring function, the IDT8V58 can be configured as a 7-channel transceiver with nonintrusive protected monitoring points. The IDT8V58 can be used for SDH/SONET multiplexers, central office or PBX, digital access cross connects, digital radio base stations, remote wireless modules and microwave transmission systems. PIN CONFIGUATIONS 9 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 8 9 4 4 4 4 44 4 5 6 7 8 9 IDT8V58 (Top View) 4 5 6 7 8 9 4 5 6 7 8 9 4 5 6 7 7 7 69 68 67 66 65 64 6 6 6 6 59 58 57 56 55 54 5 5 5 5 49 48 47 46 45 44 4 4 4 4 9 8 7 TD7/TDP7 TCLK7 LOS6 CV6/DN6 D6/DP6 CLK6 BPVI6/TDN6 TD6/TDP6 TCLK6 MCLK MODE A4 MC/A MC/A MC/A MC/A VDDIO GNDIO VDDD GNDD LP/D/AD LP/D/AD LP/D/AD LP/D/AD LP4/D4/AD4 LP5/D5/AD5 LP6/D6/AD6 LP7/D7/AD7 TCLK TD/TDP BPVI/TDN CLK D/DP CV/DN LOS TCLK TD4/TDP4 TCLK4 LOS5 CV5/DN5 D5/DP5 CLK5 BPVI5/TDN5 TD5/TDP5 TCLK5 TDI TDO TCK TMS TST IC IC VDDIO GNDIO VDDA GNDA MODE/CODE CS/JAS SCLK/ALE/AS D/ SDI/W/DS SDO/DY/ACK INT TCLK TD/TDP BPVI/TDN CLK D/DP CV/DN LOS TCLK TD/TDP BPVI4/TDN4 CLK4 D4/DP4 CV4/DN4 LOS4 OE CLKE VDDT4 TTIP4 TING4 GNDT4 TIP4 ING4 GNDT5 TING5 TTIP5 VDDT5 ING5 TIP5 VDDT6 TTIP6 TING6 GNDT6 TIP6 ING6 GNDT7 TING7 TTIP7 VDDT7 ING7 TIP7 LOS7 CV7/DN7 D7/DP7 CLK7 BPVI7/TDN7 8 7 6 5 4 99 98 97 96 95 94 9 9 9 9 89 88 87 86 85 84 8 8 8 8 79 78 77 76 75 74 7 BPVI/TDN CLK D/DP CV/DN LOS TIP ING VDDT TTIP TING GNDT ING TIP GNDT TING TTIP VDDT TIP ING VDDT TTIP TING GNDT ING TIP GNDT TING TTIP VDDT MODE LOS CV/DN D/DP CLK BPVI/TDN TD/TDP Figure- TQFP44 Package Pin Assignment

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES A B C D E F G H J K L M N P CLK 7 TCLK 7 CLK 6 TCLK 6 MCLK MC VDDIO VDDD LP 6 LP 7 TCLK CLK TCLK CLK DP 7 TDP 7 DP 6 TDP 6 MODE MC LP LP LP 5 MODE TDP DP TDP DP DN 7 TDN 7 DN 6 TDN 6 LOS 6 MC MC LP LP 4 LOS TDN DN TDN DN 4 VDDT 7 VDDT 7 VDDT 6 VDDT 6 LOS 7 A4 GNDIO GNDD LP LOS VDDT VDDT VDDT VDDT 4 5 TING 7 TTIP 7 TING 6 TTIP 6 TTIP TING TTIP TING 5 6 GNDT 7 GNDT 7 GNDT 6 GNDT 6 GNDT GNDT GNDT GNDT 6 7 8 TIP 7 TIP 4 ING 7 ING 4 TIP 6 TIP 5 ING 6 ING 5 IDT8V58 (Bottom View) ING ING TIP TIP ING ING TIP TIP 7 8 9 GNDT 4 GNDT 4 GNDT 5 GNDT 5 GNDT GNDT GNDT GNDT 9 TING 4 TTIP 4 TING 5 TTIP 5 TTIP TING TTIP TING VDDT 4 VDDT 4 VDDT 5 VDDT 5 LOS 4 TMS GNDIO GNDA CS LOS VDDT VDDT VDDT VDDT DN 4 TDN 4 DN 5 TDN 5 LOS 5 TDI TST MODE SCLK LOS TDN DN TDN DN DP 4 TDP 4 DP 5 TDP 5 CLKE TDO IC IC D INT TDP DP TDP DP 4 CLK 4 TCLK 4 CLK 5 TCLK 5 OE TCK VDDIO VDDA SDI SDO TCLK CLK TCLK CLK 4 A B C D E F G H J K L M N P Figure- PBGA6 Package Pin Assignment

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT PIN DESCIPTION INDUSTIAL TEMPEATUE ANGES Table- Pin Description Name Type TQFP44 Pin No. PBGA6 Description Transmit and eceive Line Interface TTIP TTIP TTIP TTIP TTIP4 TTIP5 TTIP6 TTIP7 TING TING TING TING TING4 TING5 TING6 TING7 Analog Output 45 5 57 64 7 4 9 6 46 5 58 6 8 5 N5 L5 L N B D D5 B5 P5 M5 M P A C C5 A5 TTIPn/TINGn: Transmit Bipolar Tip/ing for Channel ~7 These pins are the differential line driver outputs. They will be in high-z if pin OE is low or the corresponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In host mode, each pin can be in high-z by programming a to the corresponding bit in register OE (). TIP TIP TIP TIP TIP4 TIP5 TIP6 TIP7 ING ING ING ING ING4 ING5 ING6 ING7 Analog Input 48 55 6 67 7 9 49 54 6 66 6 8 P7 M7 M8 P8 A8 C8 C7 A7 N7 L7 L8 N8 B8 D8 D7 B7 TIPn/INGn: eceive Bipolar Tip/ing for Channel ~7 These pins are the differential line receiver inputs.. egister name is indicated by bold capital letter. For example, OE indicates Output Enable egister. 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name Type TQFP44 Pin No. PBGA6 Description Transmit and eceive Digital Data Interface TD/TDP TD/TDP TD/TDP TD/TDP TD4/TDP4 TD5/TDP5 TD6/TDP6 TD7/TDP7 BPVI/TDN BPVI/TDN BPVI/TDN BPVI/TDN BPVI4/TDN4 BPVI5/TDN5 BPVI6/TDN6 BPVI7/TDN7 I 7 8 7 8 8 8 79 7 9 7 44 N L L N B D D B N L L N B D D B TDn: Transmit Data for Channel ~7 When the device is in Single ail mode, the NZ data to be transmitted is input on this pin. Data on TDn is sampled into the device on the falling edges of TCLKn, and encoded by AMI or HDB line code rules before being transmitted to the line. BPVIn: Bipolar Violation Insertion for Channel ~7 Bipolar violation insertion is available in Single ail mode (see Table- on page and Table- on page 4) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing. TDPn/TDNn: Positive/Negative Transmit Data for Channel ~7 When the device is in Dual ail Mode, the NZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail mode is as the follow: TDPn TDNn Output Pulse Space Negative Pulse Positive Pulse Space Pulling pin TDNn high for more than 6 consecutive TCLK clock cycles will configure the corresponding channel into Single ail mode (see Table- on page and Table- on page 4). TCLK TCLK TCLK TCLK TCLK4 TCLK5 TCLK6 TCLK7 I 6 9 8 74 7 9 N L L4 N4 B4 D4 D B TCLKn: Transmit Clock for Channel ~7 The clock of.48 MHz for transmit is input on this pin. The transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn. Pulling TCLKn high for more than 6 MCLK cycles, the corresponding transmitter is set in Transmit All Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the clock reference. If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports become high-z. Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the follows: MCLK TCLKn Transmit Mode Clocked Clocked Normal operation Clocked High ( 6 MCLK) Transmit All Ones (TAOS) signals to the line side in the corresponding transmit channel. Clocked Low ( 64 MCLK) The corresponding transmit channel is set into power down state. TCLKn is clocked Normal operation TCLKn is high ( 6 TCLK) Transmit All Ones (TAOS) signals to the line side in the corresponding transmit channel. High/Low TCLK is clocked The receive path is not affected by the status of TCLK. When MCLK is high, all receive paths just slice the incoming data stream. When MCLK is low, all the receive paths are powered down. TCLKn is low Corresponding transmit channel is set into power ( 64 TCLK) down state. High/Low TCLK is unavailable. All eight transmitters (TTIPn & TINGn) will be in high-z. 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name D/DP D/DP D/DP D/DP D4/DP4 D5/DP5 D6/DP6 D7/DP7 CV/DN CV/DN CV/DN CV/DN CV4/DN4 CV5/DN5 CV6/DN6 CV7/DN7 CLK CLK CLK CLK CLK4 CLK5 CLK6 CLK7 O High-Z O High-Z 4 77 7 4 5 4 4 4 76 69 5 4 4 9 78 7 6 4 P M M P A C C A P M M P A C C A P M M4 P4 A4 C4 C A MCLK I E LOS LOS LOS LOS LOS4 LOS5 LOS6 LOS7 Type O TQFP44 4 5 75 68 6 4 Pin No. PBGA6 K4 K K K E E E E4 Description Dn: eceive Data for Channel ~7 In Single ail mode, the received NZ data is output on this pin. The data is decoded by AMI or HDB line code rule. CVn: Code Violation for Channel ~7 In Single ail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin CVn high for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected. DPn/DNn: Positive/Negative eceive Data for Channel ~7 In Dual ail Mode with clock recovery, these pins output the NZ data. A high signal on DPn indicates the receipt of a positive pulse on TIPn/INGn while a high signal on DNn indicates the receipt of a negative pulse on TIPn/INGn. The output data at Dn or DPn/DNn are clocked out on the falling edges of CLK when the CLKE input is low, or are clocked out on the rising edges of CLK when CLKE is high. In Dual ail Mode without clock recovery, these pins output the raw Z sliced data. In this data recovery mode, the active polarity of DPn/DNn is determined by pin CLKE. When pin CLKE is low, DPn/DNn is active low. When pin CLKE is high, DPn/DNn is active high. In hardware mode, Dn or DPn/DNn will remain active during LOS. In host mode, these pins will either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in register GCF. Dn or DPn/DNn is set into high-z when the corresponding receiver is powered down. CLKn: eceive Clock for Channel ~7 In clock recovery mode, this pin outputs the recovered clock from signal received on TIPn/INGn. The received data are clocked out of the device on the rising edges of CLKn if pin CLKE is high, or on falling edges of CLKn if pin CLKE is low. In data recovery mode, CLKn is the output of an internal exclusive O (XO) which is connected with DPn and DNn. The clock is recovered from the signal on CLKn. If eceiver n is powered down, the corresponding CLKn is in high-z. MCLK: Master Clock This is an independent, free running reference clock. A clock of.48 MHz is supplied to this pin as the clock reference of the device for normal operation. In receive path, when MCLK is high, the device slices the incoming bipolar line signal into Z pulse (Data ecovery mode). When MCLK is low, all the receivers are powered down, and the output pins CLKn, DPn and DNn are switched to high-z. In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn pin description for details). NOTE: Wait state generation via DY/ACK is not available if MCLK is not provided. LOSn: Loss of Signal Output for Channel ~7 A high level on this pin indicates the loss of signal when there is no transition over a specified period of time or no enough ones density in the received signal. The transition will return to low automatically when there is enough transitions over a specified period of time with a certain ones density in the received signal. The LOS assertion and desertion criteria are described in..4 Loss of Signal (LOS) Detection. 6

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name Type Pin No. TQFP44 PBGA6 Description Hardware/Host Control Interface MODE: Control Mode Select The signal on this pin determines which control mode is selected to control the device: MODE Low VDDIO/ High Control Interface Hardware Mode Serial Host Interface Parallel Host Interface MODE I (Pulled to VDDIO/) E Hardware control pins include MODE[:], LP[7:], CODE, CLKE, JAS and OE. Serial host Interface pins include CS, SCLK, SDI, SDO and INT. Parallel host Interface pins include CS, A[4:], D[7:], W/DS, D/, ALE/AS, INT and DY/ACK. The device supports multiple parallel host interface as follows (refer to MODE and MODE pin descriptions below for details): MODE[:] Host Interface Non-multiplexed Motorola Mode Interface Non-multiplexed Intel Mode Interface Multiplexed Motorola Mode Interface Multiplexed Intel Mode Interface MODE I 4 K MODE: Control Mode Select In parallel host mode, the parallel interface operates with separate address bus and data bus when this pin is low, and operates with multiplexed address and data bus when this pin is high. In serial host mode or hardware mode, this pin should be grounded. MODE: Control Mode Select In parallel host mode, the parallel host interface is configured for Motorola compatible hosts when this pin is low, or for Intel compatible hosts when this pin is high. MODE/CODE I 88 H CODE: Line Code ule Select In hardware control mode, the HDB encoder/decoder is enabled when this pin is low, and AMI encoder/ decoder is enabled when this pin is high. The selections affect all the channels. In serial host mode, this pin should be grounded. CS/JAS I (Pulled to VDDIO/) 87 J CS: Chip Select (Active Low) In host mode, this pin is asserted low by the host to enable host interface. A high to low transition must occur on this pin for each read/write operation and the level must not return to high until the operation is over. JAS: Jitter Attenuator Select In hardware control mode, this pin globally determines the Jitter Attenuator position: JAS Low VDDIO/ High Jitter Attenuator (JA) Configuration JA in transmit path JA not used JA in receive path 7

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name Type TQFP44 Pin No. PBGA6 Description SCLK: Shift Clock In serial host mode, the signal on this pin is the shift clock for the serial interface. Data on pin SDO is clocked out on falling edges of SCLK if pin CLKE is high, or on rising edges of SCLK if pin CLKE is low. Data on pin SDI is always sampled on rising edges of SCLK. SCLK/ALE/AS I 86 J ALE: Address Latch Enable In parallel Intel multiplexed host mode, the address on AD[4:] is sampled into the device on the falling edges of ALE (signals on AD[7:5] are ignored). In non-multiplexed host mode, ALE should be pulled high. AS: Address Strobe (Active Low) In parallel Motorola multiplexed host mode, the address on AD[4:] is latched into the device on the falling edges of AS (signals on AD[7:5] are ignored). In non-multiplexed host mode, AS should be pulled high. NOTE: This pin is ignored in hardware control mode. D: ead Strobe (Active Low) In parallel Intel multiplexed or non-multiplexed host mode, this pin is active low for read operation. D/ I 85 J SDI/W/DS I 84 J4 SDO/DY/ACK O 8 K4 : ead/write Select In parallel Motorola multiplexed or non-multiplexed host mode, the pin is active low for write operation and high for read operation. NOTE: This pin is ignored in hardware control mode. SDI: Serial Data Input In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on the rising edges of SCLK. W: Write Strobe (Active Low) In parallel Intel host mode, this pin is active low during write operation. The data on D[7:] (in non-multiplexed mode) or AD[7:] (in multiplexed mode) is sampled into the device on the rising edges of W. DS: Data Strobe (Active Low) In parallel Motorola host mode, this pin is active low. During a write operation ( = ), the data on D[7:] (in non-multiplexed mode) or AD[7:] (in multiplexed mode) is sampled into the device on the rising edges of DS. During a read operation ( = ), the data is driven to D[7:] (in non-multiplexed mode) or AD[7:] (in multiplexed mode) by the device on the rising edges of DS. In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus A[4:] are latched into the device on the falling edges of DS. NOTE: This pin is ignored in hardware control mode. SDO: Serial Data Output In serial host mode, the data is output on this pin. In serial write operation, SDO is in high impedance for the first 8 SCLK clock cycles and driven low for the remaining 8 SCLK clock cycles. In serial read operation, SDO is in high-z only when SDI is in address/command byte. Data on pin SDO is clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising edges of SCLK if pin CLKE is low. DY: eady Output In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed, while low reports the host must insert wait states. ACK: Acknowledge Output (Active Low) In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is ready for a read operation or acknowledges the acceptance of the written data during a write operation. INT O Open Drain 8 K INT: Interrupt (Active Low) This is an open drain, active low interrupt output. Three sources may cause the interrupt. efer to.8 Interrupt Handling for details. 8

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name Type TQFP44 Pin No. PBGA6 Description LPn: Loopback Select 7~ In hardware control mode, pin LPn configures the corresponding channel in different loopback mode, as follows: LP7/D7/AD7 LP6/D6/AD6 LP5/D5/AD5 LP4/D4/AD4 LP/D/AD LP/D/AD LP/D/AD LP/D/AD I/O High-Z 8 7 6 5 4 K J J J J4 H H G LPn Low VDDIO/ High efer to.6 Loopback Mode for details. Loopback Configuration emote Loopback No loopback Analog Loopback Dn: Data Bus 7~ In non-multiplexed host mode, these pins are the bi-directional data bus. ADn: Address/Data Bus 7~ In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus. In serial host mode, these pins should be grounded. MCn: Performance Monitor Configuration ~ In hardware control mode, A4 must be connected to GND. MC[:] are used to select one transmitter or receiver of channel to 7 for non-intrusive monitoring. Channel is used as the monitoring channel. If a transmitter is monitored, signals on the corresponding pins TTIPn and TINGn are internally transmitted to TIP and ING. If a receiver is monitored, signals on the corresponding pins TIPn and INGn are internally transmitted to TIP and ING. The monitored is then output to DP and DN pins. In host mode operation, the signals monitored by channel can be routed to TTIP/ING by activating the remote loopback in this channel. efer to.9 G.77 Monitoring for more details. A4 MC/A MC/A MC/A MC/A I 4 5 6 F4 F F F G Performance Monitor Configuration determined by MC[:] is shown below. Note that if MC[:] =, the device is in normal operation of all the channels. MC[:] Monitoring Configuration Normal operation without monitoring Monitor eceiver Monitor eceiver Monitor eceiver Monitor eceiver 4 Monitor eceiver 5 Monitor eceiver 6 Monitor eceiver 7 Normal operation without monitoring Monitor Transmitter Monitor Transmitter Monitor Transmitter Monitor Transmitter 4 Monitor Transmitter 5 Monitor Transmitter 6 Monitor Transmitter 7 An: Address Bus 4~ When pin MODE is low, the parallel host interface operates with separate address and data bus. In this mode, the signal on this pin is the address bus of the host interface. OE I 4 E4 OE: Output Driver Enable Pulling this pin low can drive all driver output into high-z for redundancy application without external mechanical relays. In this condition, all other internal circuits remain active. 9

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name CLKE I 5 E TST TMS I Pull-up I Pull-up 95 G 96 F TCK I 97 F4 TDO TDI O High-Z I Pull-up VDDIO - GNDIO - VDDT VDDT VDDT VDDT VDDT4 VDDT5 VDDT6 VDDT7 GNDT GNDT GNDT GNDT GNDT4 GNDT5 GNDT6 GNDT7 VDDD VDDA Type - - - TQFP44 98 F 99 F 7 9 8 9 44 5 56 65 6 5 8 7 47 5 59 6 9 4 9 9 Pin No. PBGA6 G G4 G4 G N4, P4 L4, M4 L, M N, P A, B C, D C4, D4 A4, B4 N6, P6 L6, M6 L9, M9 N9, P9 A9, B9 C9, D9 C6, D6 A6, B6 H H4 CLKE: Clock Edge Select The signal on this pin determines the active edge of CLKn and SCLK in clock recovery mode, or determines the active level of DPn and DNn in the data recovery mode. See. Clock Edges on page 4 for details. JTAG Signals TST: JTAG Test Port eset (Active Low) This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor and it can be left open. TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is clocked into the device on the rising edges of TCK. This pin has an internal pull-up resistor and it can be left open. TCK: JTAG Test Clock This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on the rising edges of TCK, while the data on TDO is clocked out of the device on the falling edges of TCK. This pin should be connected to GNDIO or VDDIO pin when unused. TDO: JTAG Test Data Output This pin output the serial data of the JTAG Test. The data on TDO is clocked out of the device on the falling edges of TCK. TDO is a high-z output signal. It is active only when scanning of data is out. This pin should be left float when unused. TDI: JTAG Test Data Input This pin input the serial data of the JTAG Test. The data on TDI is clocked into the device on the rising edges of TCK. This pin has an internal pull-up resistor and it can be left open. Power Supplies and Grounds. V I/O Power Supply I/O GND. V/5 V Power Supply for Transmitter Driver All VDDT pins must be connected to. V or all VDDT must be connected to 5 V. It is not allowed to leave any of the VDDT pins open (not-connected) even if the channel is not used. Analog GND for Transmitter Driver. V Digital/Analog Core Power Supply Description

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- Pin Description (Continued) Name Type TQFP44 Pin No. PBGA6 Description GNDD GNDA - 89 H4 H Digital/Analog Core GND Others IC O 9 94 G H IC: Internal Connection Internal use. Leave it float for normal operation.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT FUNCTIONAL DESCIPTION. OVEVIEW The IDT8V58 is a fully integrated octal short-haul line interface unit, which contains eight transmit and receive channels for use in E applications. The receiver performs clock and data recovery. As an option, the raw sliced data (no retiming) can be output to the system. Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. A selectable jitter attenuator may be placed in the receive path or the transmit path. Moreover, multiple testing functions, such as error detection, loopback and JTAG boundary scan are also provided. The device is optimized for flexible software control through a serial or parallel host mode interface. Hardware control is also available. Figure- on page shows one of the eight identical channels operation... SYSTEM INTEFACE The system interface of each channel can be configured to operate in different modes:. Single rail interface with clock recovery.. Dual rail interface with clock recovery.. Dual rail interface with data recovery (that is, with raw data slicing only and without clock recovery). Each signal pin on system side has multiple functions depending on which operation mode the device is in. INDUSTIAL TEMPEATUE ANGES The Dual ail interface consists of TDPn, TDNn, TCLKn, DPn, DNn and CLKn. Data transmitted from TDPn and TDNn appears on TTIPn and TINGn at the line interface; data received from the TIPn and INGn at the line interface are transferred to DPn and DNn while the recovered clock extracting from the received data stream outputs on CLKn. In Dual ail operation, the clock/data recovery mode is selectable. Dual ail interface with clock recovery shown in Figure-4 is a default configuration mode. Dual ail interface with data recovery is shown in Figure-5. Pin DPn and DNn, are raw Z slice outputs and internally connected to an EXO which is fed to the CLKn output for external clock recovery applications. In Single ail mode, data transmitted from TDn appears on TTIPn and TINGn at the line interface. Data received from the TIPn and INGn at the line interface appears on Dn while the recovered clock extracting from the received data stream outputs on CLKn. When the device is in single rail interface, the selectable AMI or HDB line encoder/decoder is available and any code violation in the received data will be indicated at the CVn pin. The Single ail mode has sub-modes: Single ail Mode and Single ail Mode. Single ail Mode, whose interface is composed of TDn, TCLKn, Dn, CVn and CLKn, is realized by pulling pin TDNn high for more than 6 consecutive TCLK cycles. Single ail Mode, whose interface is composed of TDn, TCLKn, Dn, CVn, CLKn and BPVIn, is realized by setting bit CS in register e-cs and bit SING in register e-sing. The difference between them is that, in the latter mode bipolar violation can be inserted via pin BPVIn if AMI line code is selected. The configuration of the Hardware Mode System Interface is summarized in Table-. The configuration of the Host Mode System Interface is summarized in Table-.. The footprint n (n = - 7) indicates one of the eight channels.. The first letter e- indicates expanded register. LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/ AMI Decoder CLKn DPn DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/ AMI Encoder TCLKn TDPn TDNn Transmit All Ones Note: The grey blocks are bypassed and the dotted blocks are selectable. Figure-4 Dual ail Interface with Clock ecovery

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES TIPn INGn Slicer LOS CLK&Data ecovery (DPLL) One of Eight Identical Channels Jitter Attenuator HDB/ AMI Decoder LOSn CLKn (DP DN) DPn DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/ AMI Encoder TCLKn TDPn TDNn Transmit All Ones Note: The grey blocks are bypassed and the dotted blocks are selectable Figure-5 Dual ail Interface with Data ecovery LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/ AMI Decoder CLKn Dn CVn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/ AMI Encoder TCLKn TDn BPVIn/TDNn Transmit All Ones Figure-6 Single ail Mode Table- System Interface Configuration (In Hardware Mode) Pin MCLK Pin TDNn Interface Clocked High ( 6 MCLK) Single ail Mode Clocked Pulse Dual ail mode with Clock ecovery High Pulse Dual ail mode with Data ecovery. eceive just slices the incoming data. Transmit is determined by the status of TCLKn. Low Pulse eceiver is powered down. Transmit is determined by the status of TCLKn.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- System Interface Configuration (In Host Mode) Pin MCLK Pin TDNn CSn in e-cs SINGn in e-sing Interface Clocked High Single ail Mode Clocked Pulse Single ail Mode Clocked Pulse Dual ail mode with Clock ecovery Clocked Pulse Dual ail mode with Data ecovery. eceive just slices the incoming data. Transmit is determined by the status of TCLKn. High Pulse - - Dual ail mode with Data ecovery. eceive just slices the incoming data. Transmit is determined by the status of TCLKn. Low Pulse - - eceiver is powered down. Transmit is determined by the status of TCLKn. Table-4 Active Clock Edge and Active Level Pin CLKE Pin Dn/DPn and CVn/DNn Clock ecovery Slicer Output Pin SDO High CLKn Active High Active High SCLK Active High Low CLKn Active High Active Low SCLK Active High. CLOCK EDGES The active edge of CLKn and SCLK are selectable. If pin CLKE is high, the active edge of CLKn is the rising edge, as for SCLK, that is falling edge. On the contrary, if CLKE is low, the active edge of CLK is the falling edge and that of SCLK is rising edge. Pins Dn/DPn, CVn/ DNn and SDO are always active high, and those output signals are clocked out on the active edge of CLKn and SCLK respectively. See Table-4 Active Clock Edge and Active Level on page 4 for details. However, in dual rail mode without clock recovery, pin CLKE is used to set the active level for DPn/DNn raw slicing output: High for active high polarity and low for active low. It should be noted that data on pin SDI are always active high and are sampled on the rising edges of SCLK. The data on pin TDn/TDPn or BPVIn/TDNn are also always active high but are sampled on the falling edges of TCLKn, despite the level on CLKE.. ECEIVE In receive path, the line signals couple into INGn and TIPn via a transformer and are converted into Z digital pulses by a data slicer. Adaptation for attenuation is achieved using an integral peak detector that sets the slicing levels. Clock and data are recovered from the received Z digital pulses by a digital phase-locked loop that provides jitter accommodation. After passing through the selectable jitter attenuator, the recovered data are decoded using HDB or AMI line code rules and clocked out of pin Dn in single rail mode, or presented on DPn/ DNn in an undecoded dual rail NZ format. Loss of signal, alarm indication signal, line code violation and excessive zeros are detected. These various changes in status may be enabled to generate interrupts... PEAK DETECTO AND SLICE The slicer determines the presence and polarity of the received pulses. In data recovery mode, the raw positive slicer output appears on DPn while the negative slicer output appears on DNn. In clock and data recovery mode, the slicer output is sent to Clock and Data ecovery circuit for abstracting retimed data and optional decoding. The slicer circuit has a built-in peak detector from which the slicing threshold is derived. The slicing threshold is default to 5% (typical) of the peak value. Signals with an attenuation of up to db (from.4 V) can be recovered by the receiver. To provide immunity from impulsive noise, the peak detectors are held above a minimum level of.5 V typically, despite the received signal level... CLOCK AND DATA ECOVEY The Clock and Data ecovery is accomplished by Digital Phase Locked Loop (DPLL). The DPLL is clocked 6 times of the received clock rate, i.e..768 MHz in E mode. The recovered data and clock from DPLL is then sent to the selectable Jitter Attenuator or decoder for further processing. The clock recovery and data recovery mode can be selected on a per channel basis by setting bit CSn in register e-cs. When bit CSn is defaulted to, the corresponding channel operates in data and clock recovery mode. The recovered clock is output on pin CLKn and retimed NZ data are output on pin DPn/DNn in dual rail mode or on Dn in single rail mode. When bit CSn is set to, dual rail mode with data recovery is enabled in the corresponding channel and the clock recovery is bypassed. In this condition, the analog line signals are converted to Z digital bit streams on the DPn/DNn pins and internally connected to an EXO which is fed to the CLKn output for external clock recovery applications. If MCLK is pulled high, all the receivers will enter the dual rail mode with data recovery. In this case, register e-cs is ignored. 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT.. HDB/AMI LINE CODE ULE Selectable HDB and AMI line coding/decoding is provided when the device is configured in single rail mode. HDB rules is enabled by setting bit CODE in register GCF to or pulling pin CODE low. AMI rule is enabled by setting bit CODE in register GCF to or pulling pin CODE high. The settings affect all eight channels. Individual line code rule selection for each channel, if needed, is available by setting bit SINGn in register e-sing to (to activate bit CODEn in register e-code) and programming bit CODEn to select line code rules in the corresponding channel: for HDB, while for AMI. In this case, the value in bit CODE in register GCF or pin CODE for global control is unaffected in the corresponding channel and only affect in other channels. In dual rail mode, the decoder/encoder are bypassed. Bit CODE in register GCF, bit CODEn in register e-code and pin CODE are ignored. INDUSTIAL TEMPEATUE ANGES The configuration of the line code rule is summarized in Table-5...4 LOSS OF SIGNAL (LOS) DETECTION The Loss of Signal monitors the amplitude and density of the received signal on receiver line before the transformer (measured on port A, B shown in Figure-). The loss condition is reported by pulling pin LOSn high. At the same time, LOS alarm registers track LOS condition. When LOS is detected or cleared, an interrupt will generate if not masked. In host mode, the detection supports ITU G.775 and ETSI. In hardware mode, it supports the ITU G.775. Table-6 summarizes the conditions of LOS in clock recovery mode. During LOS, the DPn/DNn continue to output the sliced data when bit AISE in register GCF is set to or output all ones as AIS (alarm indication signal) when bit AISE is set to. The CLKn is replaced by MCLK only if the bit AISE is set. Table-5 Configuration of the Line Code ule Hardware Mode Host Mode CODE Line Code ule CODE in GCF CODEn in e-code SINGn in e-sing Line Code ule / Low All channels in HDB All channels in HDB / All channels in AMI High All channels in AMI CHn in AMI CHn in HDB Table-6 LOS Condition in Clock ecovery Mode LOS Detected Standard G.775 ETSI Continuous Intervals 48 ( ms) Amplitude () below typical mvp below typical mvp.5% (4 marks in a sliding -bit period) with no more than 5 continuous zeros LOS Density Cleared Amplitude () exceed typical 5 mvp exceed typical 5 mvp. LOS levels at device (TIPn, INGn) with all ones signal. For more detail regarding the LOS parameters, please refer to eceiver Characteristics on page 4. Signal on LOSn High.5% (4 marks in a sliding -bit period) with no more than 5 continuous zeros Low..5 ALAM INDICATION SIGNAL (AIS) DETECTION Alarm Indication Signal is available only in host mode with clock recovery, as shown in Table-7...6 EO DETECTION The device can detect excessive zeros, bipolar violation and HDB code violation, as shown in Figure-7 and Figure-8. All the three kinds of errors are reported in both host mode and hardware mode with HDB line code rule used. In host mode, the e-cze and e-codv are used to determine whether excessive zeros and code violation are reported respectively. When the device is configured in AMI decoding mode, only bipolar violation can be reported. The error detection is available only in single rail mode in which the pin CVn/DNn is used as error report output (CVn pin). The configuration and report status of error detection are summarized in Table-8. Table-7 AIS Condition ITU G.775 (egister LAC defaulted to ) ETSI (egister LAC set to ) AIS Detected Less than zeros contained in each of two consecutive 5-bit stream are received Less than zeros contained in a 5-bit stream are received AIS Cleared or more zeros contained in each of two consecutive 5-bit stream are received or more zeros contained in a 5-bit stream are received 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-8 Error Detection Hardware Mode Host Mode Line Code Pin CVn eports Line Code CODVn in e-codv CZEn in e-cze Pin CVn eports AMI Bipolar Violation AMI - - Bipolar Violation HDB Bipolar Violation + Code Violation + Excessive Zeros HDB Bipolar Violation + Code Violation Bipolar Violation + Code Violation + Excessive Zeros Bipolar Violation Bipolar Violation + Excessive Zeros CLKn TIPn 5 V 7 INGn 4 6 Dn 4 5 V 6 CVn Bipolar Violation Bipolar Violation detected Figure-7 AMI Bipolar Violation Code violation CLKn TIPn 4 consecutive zeros 5 INGn 4 V V 6 Dn 4 5 6 CVn Excessive zeros detected Code violation detected Figure-8 HDB Code Violation & Excessive Zeros.4 TANSMITTE In transmit path, data in NZ format are clocked into the device on TDn and encoded by AMI or HDB line code rules when single rail mode is configured or pre-encoded data in NZ format are input on TDPn and TDNn when dual rail mode is configured. The data are sampled into the device on falling edges of TCLKn. Jitter attenuator, if enabled, is provided with a FIFO through which the data to be transmitted are passing. A low jitter clock is generated by an integral digital phaselocked loop and is used to read data from the FIFO. The shape of the pulses should meet the E pulse template after the signal passes through different cable lengths or types. Bipolar violation, for diagnosis, can be inserted on pin BPVIn if AMI line code rule is enabled. 6

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT.4. WAVEFOM SHAPE E pulse template, specified in ITU-T G.7, is shown in Figure-9. The device has built-in transmit waveform templates for cable of 75 Ω or Ω. The built-in waveform shaper uses an internal high frequency clock which is 6XMCLK as the clock reference. This function will be bypassed when MCLK is unavailable. Normalized Amplitude...8.6.4.. -. - - - Time (ns) Figure-9 CEPT Waveform Template.4. BIPOLA VIOLATION INSETION When configured in Single ail Mode with AMI line code enabled, pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this pin inserts a bipolar violation on the next available mark in the transmit data stream. Sampling occurs on the falling edges of TCLK. But in TAOS (Transmit All Ones) with Analog Loopback and emote Loopback, the BPVI is disabled. In TAOS with Digital Loopback, the BPVI is looped back to the system side, so the data to be transmitted on TTIPn and TINGn are all ones with no bipolar violation..5 JITTE ATTENUATO The jitter attenuator can be selected to work either in transmit path or in receive path or not used. The selection is accomplished by setting pin JAS in hardware mode or configuring bits JACF[:] in register GCF in host mode, which affects all eight channels. INDUSTIAL TEMPEATUE ANGES For applications which require line synchronization, the line clock needed to be extracted for the internal synchronization, the jitter attenuator is set in the receive path. Another use of the jitter attenuator is to provide clock smoothing in the transmit path for applications such as synchronous/asynchronous demultiplexing applications. In these applications, TCLK will have an instantaneous frequency that is higher than the nominal E data rate and in order to set the average long-term TCLK frequency within the transmit line rate specifications, periods of TCLK are suppressed (gapped). The jitter attenuator integrates a FIFO which can accommodate a gapped TCLK. In host mode, the FIFO length can be X or 64 X bits by programming bit JADP in GCF. In hardware mode, it is fixed to 64 X bits. The FIFO length determines the maximum permissible gap width (see Table-9 Gap Width Limitation). Exceeding these values will cause FIFO overflow or underflow. The data is 6 or bits delay through the jitter attenuator in the corresponding transmit or receive path. The constant delay feature is crucial for the applications requiring hitless switching. Table-9 Gap Width Limitation FIFO Length Max. Gap Width 64 bit 56 UI bit 8 UI In host mode, bit JABW in GCF determines the jitter attenuator db corner frequency (fc). In hardware mode, the fc is fixed to.7 Hz. Generally, the lower the fc is, the higher the attenuation. However, lower fc comes at the expense of increased acquisition time. Therefore, the optimum fc is to optimize both the attenuation and the acquisition time. In addition, the longer FIFO length results in an increased throughput delay and also influences the db corner frequency. Generally, it s recommended to use the lower corner frequency and the shortest FIFO length that can still meet jitter attenuation requirements. The output jitter meets ITU-T G.76, ITU-T G.74, ITU-T G.78 and ETSI CT /..6 LINE INTEFACE CICUITY The transmit and receive interface TIPn/INGn and TTIPn/ TINGn connections provide a matched interface to the cable. Figure- shows the appropriate external components to connect with the cable for one transmit/receive channel. Table- summarizes the component values based on the specific application. 7

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- External Components Values Component 75 Ω Coax Ω Twisted Pair T 9.5 Ω ± % 9.5 Ω ± % 9. Ω ± % 5 Ω ± % Cp pf D - D4 Nihon Inter Electronics - EP5QL, EQSL, ECQS4, ECQSL; Motorola - MB54T A X Line B TX Line One of Eight Identical Channels : kω TIPn. µf VDDT INGn : kω D4 VDDT TTIPn T D VDDDn 68 µf Cp. µf VDDT D GNDTn TINGn T D IDT8V58 NOTE:. Pulse T4 transformer is recommended to be used in Standard (STD) operating temperature range ( C to 7 C), while Pulse T4 transformer is recommended to be used in Extended (EXT) operating temperature range is -4 C to +85 C. See Transformer Specifications Table for details.. Typical value. Adjust for actual board parasitics to obtain optimum return loss.. Common decoupling capacitor for all VDDT and GNDT pins. One per chip..7 TANSMIT DIVE POWE SUPPLY All transmit driver power supplies must be 5. V or. V. Despite the power supply voltage, the 75 Ω/ Ω lines are driven through a pair of 9.5 Ω series resistors and a : transformer. Table- Transformer Specifications ().8 POWE DIVE FAILUE MONITO An internal power Driver Failure Monitor (DFMON), parallel connected with TTIPn and TINGn, can detect short circuit failure between TTIPn and TINGn pins. Bit SCPB in register GCF decides whether the output driver short circuit protection is enabled. When the short circuit protection is enabled, the driver output current is limited to a typical value: 8 map. Also, register DF, DFI and DFM will be available. When DFMON will detect a short circuit, register DF will be set. With a short circuit failure detected and short circuit protection enabled, register DFI will be set and an interrupt will be generated on pin INT. Figure- External Transmit/eceive Line Circuitry Electrical Specification @ 5 C Part No. Turns atio (Pri: sec ± %) OCL @ 5 C (mh MIN) L L (µh MAX) C W/W (pf MAX) Package/Schematic STD Temp. EXT Temp. Transmit eceive Transmit eceive Transmit eceive Transmit eceive T4 T4 :CT CT:...6.6 5 5 TOU/. Pulse T4 transformer is recommended to be used in Standard (STD) operating temperature range ( C to 7 C), while Pulse T4 transformer is recommended to be used in Extended (EXT) operating temperature range is -4 C to +85 C..9 TANSMIT LINE SIDE SHOT CICUIT FAILUE DETECTION A pair of 9.5 Ω serial resistors connect with TTIPn and TINGn pins and limit the output current. In this case, the output current is a limited value which is always lower than the typical line short circuit current 8 map, even if the transmit line side is shorted. efer to Table- External Components Values for details. 8

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT. LINE POTECTION In transmit side, the Schottky diodes D~D4 are required to protect the line driver and improve the design robustness. In receive side, the series resistors of kω are used to protect the receiver against current surges coupled in the device. The series resistors do not affect the receiver sensitivity, since the receiver impedance is as high as kω typically.. HITLESS POTECTION SWITCHING (HPS) The IDT8V58 transceivers include an output driver with high-z feature for E redundancy applications. This feature reduces the cost of redundancy protection by eliminating external relays. Details of HPS are described in relative Application Note.. SOFTWAE ESET Writing register S will cause software reset by initiating about µs reset cycle. This operation set all the registers to their default value.. POWE ON ESET During power up, an internal reset signal sets all the registers to default values. The power-on reset takes at least µs, starting from when the power supply exceeds / VDDA..4 POWE DOWN Each transmit channel will be powered down by pulling pin TCLKn low for more than 64 MCLK cycles (if MCLK is available) or about µs (if MCLK is not available). In host mode, each transmit channel will also be powered down by setting bit TPDNn in register e-tpdn to. All the receivers will be powered down when MCLK is low. When MCLK is clocked or high, setting bit PDNn in register e-pdn to will configure the corresponding receiver to be powered down..5 INTEFACE WITH 5 V LOGIC The IDT8V58 can interface directly with 5 V TTL family devices. The internal input pads are tolerant to 5 V output from TTL and CMOS family devices..6 LOOPBACK MODE The device provides four different diagnostic loopback configurations: Digital Loopback, Analog Loopback, emote Loopback and Dual Loopback. In host mode, these functions are implemented by programming the registers DLB, ALB and LB respectively. In hardware mode, only Analog Loopback and emote Loopback can be selected by pin LPn..6. DIGITAL LOOPBACK By programming the bits of register DLB, each channel of the device can be configured in Local Digital Loopback. In this configuration, the data and clock to be transmitted, after passing the encoder, are looped back to Jitter Attenuator (if enabled) and decoder in the receive path, then output on CLKn, Dn/DPn and CVn/DNn. The data to be transmitted are still output on TTIPn and TINGn while the data received on TIPn and INGn are ignored. The Loss is still in use. Figure- shows the process. INDUSTIAL TEMPEATUE ANGES During Digital Loopback, the received signal on the receive line is still monitored by the LOS (See..4 Loss of Signal (LOS) Detection for details). In case of a LOS condition and AIS insertion enabled, all ones signal will be output on DPn/DNn. With ATAO enabled, all ones signal will be also output on TTIPn/TINGn. AIS insertion can be enabled by setting AISE bit in register GCF and ATAO can be enabled by setting register ATAO (default disabled)..6. ANALOG LOOPBACK By programming the bits of register ALB or pulling pin LPn high, each channel of the device can be configured in Analog Loopback. In this configuration, the data to be transmitted output from the line driver are internally looped back to the slicer and peak detector in the receive path and output on CLKn, Dn/DPn and CVn/DNn. The data to be transmitted are still output on TTIPn and TINGn while the data received on TIPn and INGn are ignored. The LOS (See..4 Loss of Signal (LOS) Detection for details) is still in use and monitors the internal looped back data. If a LOS condition on TDPn/TDNn is expected during Analog Loopback, ATAO should be disabled (default). Figure- shows the process. The TTIPn and TIPn, TINGn and INGn cannot be connected directly to do the external analog loopback test. Line impedance loading is required to conduct the external analog loopback test..6. EMOTE LOOPBACK By programming the bits of register LB or pulling pin LPn low, each channel of the device can be set in emote Loopback. In this configuration, the data and clock recovered by the clock and data recovery circuits are looped to waveform shaper and output on TTIPn and TINGn. The jitter attenuator is also included in loopback when enabled in the transmit or receive path. The received data and clock are still output on CLKn, Dn/DPn and CVn/DNn while the data to be transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The LOs is still in use. Figure- shows the process..6.4 DUAL LOOPBACK Dual Loopback mode is set by setting bit DLBn in register DLB and bit LBn in register LB to. In this configuration, after passing the encoder, the data and clock to be transmitted are looped back to decoder directly and output on CLKn, Dn/DPn and CVn/DNn. The recovered data from TIPn and INGn are looped back to waveform shaper through JA (if selected) and output on TTIPn and TINGn. The LOS is still in use. Figure-4 shows the process..6.5 TANSMIT ALL ONES (TAOS) In hardware mode, the TAOS mode is set by pulling pin TCLKn high for more than 6 MCLK cycles. In host mode, TAOS mode is set by programming register TAO. In addition, automatic TAOS signals are inserted by setting register ATAO when Loss of Signal occurs. Note that the TAOS generator adopts MCLK as a timing reference. In order to assure that the output frequency is within specified limits, MCLK must have the applicable stability. The TAOS mode, the TAOS mode with Digital Loopback and the TAOS mode with Analog Loopback are shown in Figure-5, Figure-6 and Figure-7. 9

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak Digital Loopback TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure- Digital Loopback LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Analog Loopback Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure- Analog Loopback LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak emote Loopback TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure- emote Loopback

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure-4 Dual Loopback LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure-5 TAOS Data Path LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones Figure-6 TAOS with Digital Loopback

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES LOS One of Eight Identical Channels LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/AMI Decoder CLKn Dn/DPn CVn/DNn Peak TTIPn TINGn Line Driver Waveform Shaper HDB/AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn.7 HOST INTEFACE The host interface provides access to read and write the registers in the device. The interface consists of serial host interface and parallel host interface. By pulling pin MODE to VDDIO/ or high, the device can be set to work in serial mode and in parallel mode respectively. Table- Parallel Host Interface Pins Transmit All Ones Figure-7 TAOS with Analog Loopback.7. PAALLEL HOST INTEFACE The interface is compatible with Motorola and Intel host. Pins MODE and MODE are used to select the operating mode of the parallel host interface. When pin MODE is pulled low, the host uses separate address bus and data bus. When high, multiplexed address/ data bus is used. When pin MODE is pulled low, the parallel host interface is configured for Motorola compatible hosts. When pin MODE is pulled high, the parallel host interface is configured for Intel compatible hosts. See Table- Pin Description for more details. The host interface pins in each operation mode is tabulated in Table-: MODE[:] Host Interface Generic Control, Data and Output Pin Non-multiplexed Motorola interface CS, ACK, DS,, AS, A[4:], D[7:], INT Non-multiplexed Intel interface CS, DY, W, D, ALE, A[4:], D[7:], INT Multiplexed Motorola interface CS, ACK, DS,, AS, AD[7:], INT Multiplexed Intel interface CS, DY, W, D, ALE, AD[7:], INT CS SCLK SDI A A A A4 A5 A6 A7 D D D D D4 D5 D6 D7 Address/Command Byte Input Data Byte SDO D D D D D4 D5 D6 D7 High Impedance Driven while =. While =, read from IDT8V58; While =, write to IDT8V58.. Ignored. Figure-8 Serial Host Mode Timing.7. SEIAL HOST INTEFACE By pulling pin MODE to VDDIO/, the device operates in the serial host Mode. In this mode, the registers are accessible through a 6-bit word which contains an 8-bit command/address byte (bit and 5- address-bit A~A5, A6 and A7 bits are ignored) and a subsequent 8-bit data byte (D7~D), as shown in Figure-8. When bit is set to, data is read out from pin SDO. When bit is set to, data on pin SDI is written into the register whose address is indicated by address bits A5~A. See Figure-8 Serial Host Mode Timing.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT.8 INTEUPT HANDLING.8. INTEUPT SOUCES There are three kinds of interrupt sources:. Status change in register LOS. The analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in register LOS which indicates presence or absence of a LOS condition.. Status change in register DF. The automatic power driver circuit continuously monitors the output drivers signal to update the specific bit in register DFM which indicates presence or absence of an output driver short circuit condition.. Status change in register AIS. The AIS detector monitors the received signal to update the specific bit in register AIS which indicates presence or absence of a AIS condition. No Interrupt Allowed Interrupt Condition Exist? Yes ead Interrupt Status egister ead Corresponding Status egister Service the Interrupt INDUSTIAL TEMPEATUE ANGES.8. INTEUPT ENABLE The IDT8V58 provides a latched interrupt output (INT) and the four kinds of interrupts are all reported by this pin. When the Interrupt Mask register (LOSM, DFM and AISM) is set to, the Interrupt Status register (LOSI, DFI and AISI) is enabled respectively. Whenever there is a transition ( to or to ) in the corresponding status register, the Interrupt Status register will change into, which means an interrupt occurs, and there will be a high to low transition on INT pin. An external pull-up resistor of approximately kω is required to support the wire- O operation of INT. When any of the three Interrupt Mask registers is set to (the power-on default value is ), the corresponding Interrupt Status register is disabled and the transition on status register is ignored..8. INTEUPT CLEAING When an interrupt occurs, the Interrupt Status registers: LOSI, DFI and AISI, are read to identify the interrupt source. These registers will be cleared to after the corresponding status registers: LOS, DF and AIS are read. The Status registers will be cleared once the corresponding conditions are met. Pin INT is pulled high when there is no pending interrupt left. The interrupt handling in the interrupt service routine is showed in Figure-9..9 G.77 MONITOING The eight channels of IDT8V58 can all be configured to work as regular transceivers. In applications using only seven channels (channels to 7), channel is configured to non-intrusively monitor any of the other channels inputs or outputs on the line side. The monitoring is nonintrusive per ITU-T G.77. Figure- shows the Monitoring Principle. The receiver path or transmitter path to be monitored is configured by pins MC[:] in hardware mode or by register PMON in host mode. The monitored signal goes through the clock and data recovery circuit of channel. The monitored clock can output on CLK which can be used as a timing interfaces derived from E signal. The monitored data can be observed digitally at the output pins CLK, D/ DP and DN. LOS detector is still in use in channel for the monitored signal. In monitoring mode, channel can be configured in emote Loopback. The signal which is being monitored will output on TTIP and TING. The output signal can then be connected to a standard test equipment with an E electrical interface for non-intrusive monitoring. Figure-9 Interrupt Service outine

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES LOS Channel N ( 7 > N > ) LOSn TIPn INGn Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/ AMI Decoder CLKn Dn/DPn CVn/DNn Peak TTIPn TINGn Line Driver Waveform Shaper Jitter Attenuator HDB/ AMI Encoder TCLKn TDn/TDPn BPVIn/TDNn Transmit All Ones G.77 Monitor LOS Channel LOS TIP ING Slicer CLK&Data ecovery (DPLL) Jitter Attenuator HDB/ AMI Decoder CLK D/DP CV/DN Peak emote Loopback TTIP TING Line Driver Waveform Shaper Jitter Attenuator HDB/ AMI Encoder TCLK TD/TDP BPVI/TDN Transmit All Ones Figure- Monitoring Principle 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT POGAMMING INFOMATION. EGISTE LIST AND MAP There are primary registers (including an Address Pointer Control egister and 8 expanded registers in the device). Whatever the control interface is, 5 address bits are used to set the registers. In non-multiplexed parallel interface mode, the five dedicated address bits are A[4:]. In multiplexed parallel interface mode, AD[4:] carries the address information. In serial interface mode, A[5:] are used to address the register. Table- Primary egister List INDUSTIAL TEMPEATUE ANGES The egister ADDP, addressed as or F Hex, switches between primary registers bank and expanded registers bank. By setting the register ADDP to AAH, the 5 address bits point to the expanded register bank, that is, the expanded registers are available. By clearing register ADDP, the primary registers are available. Primary egisters, whose addresses are H, H, 6H to EH, are reserved. Expanded registers, whose addresses are 8H to EH, are used for test and must be set to (default). Address Hex Serial Interface A7-A Parallel Interface A7-A egister Explanation XX XXX ID Device ID egister XX XXX ALB Analog Loopback Configuration egister XX XXX LB emote Loopback Configuration egister XX XXX TAO Transmit All Ones Configuration egister 4 XX XXX LOS Loss of Signal Status egister 5 XX XXX DF Driver Fault Status egister 6 XX XXX LOSM LOS Interrupt Mask egister 7 XX XXX DFM Driver Fault Interrupt Mask egister 8 XX XXX LOSI LOS Interrupt Status egister 9 XX XXX DFI Driver Fault Interrupt Status egister A XX XXX S W Software eset egister B XX XXX PMON Performance Monitor Configuration egister C XX XXX DLB Digital Loopback Configuration egister D XX XXX LAC LOS/AIS Criteria Configuration egister E XX XXX ATAO Automatic TAOS Configuration egister F XX XXX GCF Global Configuration egister XX XXX XX XXX eserved XX XXX OE Output Enable Configuration egister XX XXX AIS AIS Status egister 4 XX XXX AISM AIS Interrupt Mask egister 5 XX XXX AISI AIS Interrupt Status egister 6 XX XXX 7 XX XXX 8 XX XXX 9 XX XXX A XX XXX eserved B XX XXX C XX XXX D XX XXX E XX XXX F XX XXX ADDP Address pointer control egister for switching between primary register bank and expanded register bank 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-4 Expanded (Indirect Address Mode) egister List Address egister Explanation Hex Serial Interface A7-A Parallel Interface A7-A XX XXX e-sing Single ail Mode Setting egister XX XXX e-code Encoder/Decoder Selection egister XX XXX e-cs Clock ecovery Enable/Disable egister XX XXX e-pdn eceiver n Powerdown Enable/Disable egister 4 XX XXX e-tpdn Transmitter n Powerdown Enable/Disable egister 5 XX XXX e-cze Consecutive Zero Detect Enable/Disable egister 6 XX XXX e-codv Code Violation Detect Enable/Disable egister 7 XX XXX e-equa Enable Equalizer Enable/Disable egister 8 XX XXX 9 XX XXX A XX XXX B XX XXX C XX XXX D XX XXX E XX XXX F XX XXX XX XXX XX XXX XX XXX XX XXX Test 4 XX XXX 5 XX XXX 6 XX XXX 7 XX XXX 8 XX XXX 9 XX XXX A XX XXX B XX XXX C XX XXX D XX XXX E XX XXX F XX XXX ADDP Address pointer control register for switching between primary register bank and expanded register bank 6

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-5 Primary egister Map egister Address Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit ID ALB LB TAO LOS DF LOSM DFM LOSI DFI S PMON DLB LAC ATAO GCF H H H H 4H 5H 6H 7H 8H 9H AH W BH CH DH EH FH ID 7 ALB 7 LB 7 TAO 7 LOS 7 DF 7 LOSM 7 DFM 7 LOSI 7 DFI 7 S 7 W - DLB 7 LAC 7 ATAO 7 - ID 6 ALB 6 LB 6 TAO 6 LOS 6 DF 6 LOSM 6 DFM 6 LOSI 6 DFI 6 S 6 W - DLB 6 LAC 6 ATAO 6 AISE ID 5 ALB 5 LB 5 TAO 5 LOS 5 DF 5 LOSM 5 DFM 5 LOSI 5 DFI 5 S 5 W - DLB 5 LAC 5 ATAO 5 SCPB ID 4 ALB 4 LB 4 TAO 4 LOS 4 DF 4 LOSM 4 DFM 4 LOSI 4 DFI 4 S 4 W - DLB 4 LAC 4 ATAO 4 CODE ID ALB LB TAO LOS DF LOSM DFM LOSI DFI S W MC DLB LAC ATAO JADP ID ALB LB TAO LOS DF LOSM DFM LOSI DFI S W MC DLB LAC ATAO JABW ID ALB LB TAO LOS DF LOSM DFM LOSI DFI S W MC DLB LAC ATAO JACF ID ALB LB TAO LOS DF LOSM DFM LOSI DFI S W MC DLB LAC ATAO JACF 7

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-5 Primary egister Map (Continued) egister Address Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit OE AIS AISM AISI ADDP Hex Hex 4 Hex 5 Hex F Hex OE 7 AIS 7 AISM 7 AISI 7 ADDP 7 OE 6 AIS 6 AISM 6 AISI 6 ADDP 6 OE 5 AIS 5 AISM 5 AISI 5 ADDP 5 OE 4 AIS 4 AISM 4 AISI 4 ADDP 4 OE AIS AISM AISI ADDP OE AIS AISM AISI ADDP OE AIS AISM AISI ADDP OE AIS AISM AISI ADDP Table-6 Expanded (Indirect Address Mode) egister Map egister Address Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit e-sing e-code e-cs e-pdn e-tpdn e-cze e-codv e-equa ADDP H H H H 4H 5H 6H 7H FH SING 7 CODE 7 CS 7 PDN 7 TPDN 7 CZE 7 CODV 7 EQUA 7 ADDP 7 SING 6 CODE 6 CS 6 PDN 6 TPDN 6 CZE 6 CODV 6 EQUA 6 ADDP 6 SING 5 CODE 5 CS 5 PDN 5 TPDN 5 CZE 5 CODV 5 EQUA 5 ADDP 5 SING 4 CODE 4 CS 4 PDN 4 TPDN 4 CZE 4 CODV 4 EQUA 4 ADDP 4 SING CODE CS PDN TPDN CZE CODV EQUA ADDP SING CODE CS PDN TPDN CZE CODV EQUA ADDP SING CODE CS PDN TPDN CZE CODV EQUA ADDP SING CODE CS PDN TPDN CZE CODV EQUA ADDP 8

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES. EGISTE DESCIPTION.. PIMAY EGISTES ID: Device ID egister (, Address = H) Symbol Position Description ID[7:] ID.7- H An 8-bit word is pre-set into the device as the identification and revision number. This number is different with the functional changes and is mask programmed. ALB: Analog Loopback Configuration egister (, Address = H) Symbol Position Description = Normal operation. () ALB[7:] ALB.7- H = Analog Loopback enabled. LB: emote Loopback Configuration egister (, Address = H) Symbol Position Description = Normal operation. () LB[7:] LB.7- H = emote Loopback enabled. TAO: Transmit All Ones Configuration egister (, Address = H) Symbol Position Description = Normal operation. () TAO[7:] TAO.7- H = Transmit all ones. LOS: Loss of Signal Status egister (, Address = 4H) Symbol Position Description = Normal operation. () LOS[7:] LOS.7- H = Loss of signal detected. DF: Driver Fault Status egister (, Address = 5H) Symbol Position Description = Normal operation. () DF[7:] DF.7- H = Driver fault detected. LOSM: Loss of Signal Interrupt Mask egister (, Address = 6H) Symbol Position Description = LOS interrupt is not allowed. () LOSM[7:] LOSM.7- H = LOS interrupt is allowed. DFM: Driver Fault Interrupt Mask egister (, Address = 7H) Symbol Position Description = Driver fault interrupt not allowed. () DFM[7:] DFM.7- H = Driver fault interrupt allowed. LOSI: Loss of Signal Interrupt Status egister (, Address = 8H) Symbol Position Description LOSI[7:] LOSI.7- H = (). Or after a LOS read operation. = Any transition on LOSn (Corresponding LOSMn is set to ). 9

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES DFI: Driver Fault Interrupt Status egister (, Address = 9H) Symbol Position Description DFI[7:] DFI.7- H = (). Or after a DF read operation. = Any transition on DFn (Corresponding DFMn is set to ). S: Software eset egister (W, Address = AH) Symbol Position Description S[7:] S.7- FFH Writing to this register will not change the content in this register but initiate a µs reset cycle, which means all the registers in the device are set to their default values. PMON: Performance Monitor Configuration egister (, Address = BH) Symbol Position Description - PMON.7-4 = Normal operation. () = eserved. MC[:] PMON.- = Normal operation without monitoring () = Monitor eceiver = Monitor eceiver = Monitor eceiver = Monitor eceiver 4 = Monitor eceiver 5 = Monitor eceiver 6 = Monitor eceiver 7 = Normal operation without monitoring = Monitor Transmitter = Monitor Transmitter = Monitor Transmitter = Monitor Transmitter 4 = Monitor Transmitter 5 = Monitor Transmitter 6 = Monitor Transmitter 7 DLB: Digital Loopback Configuration egister (, Address = CH) Symbol Position Description = Normal operation. () DLB[7:] DLB.7- H = Digital Loopback enabled. LAC: LOS/AIS Criteria Configuration egister (, Address = DH) Symbol Position Description = G.775 () LAC[7:] LAC.7- H = ETSI ATAO: Automatic TAOS Configuration egister (, Address = EH) Symbol Position Description ATAO[7:] ATAO.7- H = No automatic transmit all ones. () = Automatic transmit all ones to the line side during LOS.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES GCF: Global Configuration egister (, Address = FH) Symbol Position Description - GCF.7 = Normal operation. = eserved. AISE GCF.6 = AIS insertion to the system side disabled on LOS. = AIS insertion to the system side enabled on LOS. SCPB GCF.5 = Short circuit protection is enabled. = Short circuit protection is disabled. CODE GCF.4 = HDB encoder/decoder enabled. = AMI encoder/decoder enabled. JADP GCF. Jitter Attenuator Depth Select = -bit FIFO () = 64-bit FIFO JABW GCF. Jitter Transfer Function Bandwidth Select =.7 Hz = 6.6 Hz JACF[:] GCF.- Jitter Attenuator Configuration = JA not used. () = JA in transmit path = JA not used. = JA in receive path OE: Output Enable Configuration egister (, Address = H) Symbol Position Description = Transmit drivers enabled. () OE[7:] OE.7- H = Transmit drivers in high-z. AIS: Alarm Indication Signal Status egister (, Address = H) Symbol Position Description = Normal operation. () AIS[7:] AIS.7- H = AIS detected. AISM: Alarm Indication Signal Interrupt Mask egister (, Address = 4H) Symbol Position Description = AIS interrupt is not allowed. () AISM[7:] AISM.7- H = AIS interrupt is allowed. AISI: Alarm Indication Signal Interrupt Status egister (, Address = 5H) Symbol Position Description AISI[7:] AISI.7- H = (), or after an AIS read operation = Any transition on AISn. (Corresponding AISMn is set to.) ADDP: Address Pointer Control egister (, Address = F H) Symbol Position Description ADDP[7:] ADDP.7- H Two kinds of configuration in this register can be set to switch between primary register bank and expanded register bank. When power up, the address pointer will point to the top address of primary register bank automatically. H = The address pointer points to the top address of primary register bank (default). AAH = The address pointer points to the top address of expanded register bank.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES.. EXPANDED EGISTE DESCIPTION e-sing: Single ail Mode Setting egister (, Expanded Address = H) Symbol Position Description SING[7:] SING.7- H = Pin TDNn selects single rail mode or dual rail mode. () = Single rail mode enabled (with CSn=) e-code: Encoder/Decoder Selection egister (, Expanded Address = H) Symbol Position Description CODE[7:] CODE.7- H CODEn selects AMI or HDB encoder/decoder on a per channel basis with SINGn = and CSn =. = HDB encoder/decoder enabled. () = AMI encoder/decoder enabled. e-cs: Clock ecovery Enable/Disable Selection egister (, Expanded Address = H) Symbol Position Description = Clock recovery enabled. () CS[7:] CS.7- H = Clock recovery disabled. e-pdn: eceiver n Powerdown egister (, Expanded Address = H) Symbol Position Description PDN[7:] PDN.7- H = Normal operation. () = eceiver n is powered down. e-tpdn: Transmitter n Powerdown egister (, Expanded Address = 4H) Symbol Position Description TPDN[7:] TPDN.7- H = Normal operation. () = Transmitter n is powered down () (the corresponding transmit output driver enters a low power high-z mode).. Transmitter n is powered down when either pin TCLKn is pulled low or TPDNn is set to e-cze: Consecutive Zero Detect Enable/Disable egister (, Expanded Address = 5H) Symbol Position Description CZE[7:] CZE.7- H = Excessive zeros detect disabled. () = Excessive zeros detect enabled for HDB decoder in single rail mode. e-codv: Code Violation Detect Enable/Disable egister (, Expanded Address = 6H) Symbol Position Description CODV[7:] CODV.7- H = Code Violation Detect enable for HDB decoder in single rail mode. () = Code Violation Detect disabled. e-equa: eceive Equalizer Enable/Disable egister (, Expanded Address = 7H) Symbol Position Description EQUA[7:] EQUA.7- H = Normal operation. () = Equalizer in eceiver n is enabled, which can improve the receive performance when transmission length is more than m.

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT 4 IEEE STD 49. JTAG TEST ACCESS POT The IDT8V58 supports the digital Boundary Scan Specification as described in the IEEE 49. standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the TMS and TCK pins. Data is shifted into the registers via the TDI pin, and shifted out of the registers via the TDO pin. JTAG test data are clocked at a rate determined by JTAG test clock. INDUSTIAL TEMPEATUE ANGES The JTAG boundary scan registers includes BS (Boundary Scan egister), ID (Device Identification egister), B (Bypass egister) and I (Instruction egister). These will be described in the following pages. efer to Figure- for architecture. 4. JTAG INSTUCTIONS AND INSTUCTION EG- ISTE (I) The I with instruction decode block is used to select the test to be executed or the data register to be accessed or both. The instructions are shifted in LSB first to this -bit register. See Table-7 Instruction egister Description on page 4 for details of the codes and the instructions related. Digital output pins Digital input pins parallel latched output BS (Boundary Scan egister) ID (Device Identification egister) MUX TDI B (Bypass egister) I (Instruction egister) MUX TDO TMS TST TCK TAP (Test Access Port) Controller Control<6:> Select High-Z Enable Figure- JTAG Architecture

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-7 Instruction egister Description I Code Instruction Comments Extest Sample/Preload Idcode Bypass The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by loading the boundary scan register using the Capture-D state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-D state. The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-D state. The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT8V58 logic and the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-D state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-D state. The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-D state. The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device. Table-8 Device Identification egister Description Bit No. 4. JTAG DATA EGISTE Comments Set to ~ Producer Number ~7 Part Number 8~ Device evision 4.. DEVICE IDENTIFICATION EGISTE (ID) The ID can be set to define the producer number, part number and the device revision, which can be used to verify the proper version or revision number that has been used in the system under test. The ID is bits long and is partitioned as in Table-8. Data from the ID is shifted out to TDO LSB first. Table-9 Boundary Scan egister Description 4.. BYPASS EGISTE (B) The B consists of a single bit. It can provide a serial path between the TDI input and TDO output, bypassing the BS to reduce test access times. 4.. BOUNDAY SCAN EGISTE (BS) The BS can apply and read test patterns in parallel to or from all the digital I/O pins. The BS is a 98 bits long shift register and is initialized and read using the instruction EXTEST or SAMPLE/PELOAD. Each pin is related to one or more bits in the BS. Please refer to Table-9 for details of BS bits and their functions. Bit No. Bit Symbol Pin Signal Type Comments POUT LP I/O PIN LP I/O POUT LP I/O PIN LP I/O 4 POUT LP I/O 5 PIN LP I/O 6 POUT LP I/O 7 PIN LP I/O 8 POUT4 LP4 I/O 9 PIN4 LP4 I/O POUT5 LP5 I/O PIN5 LP5 I/O POUT6 LP6 I/O PIN6 LP6 I/O 4 POUT7 LP7 I/O 5 PIN7 LP7 I/O 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-9 Boundary Scan egister Description (Continued) Bit No. Bit Symbol Pin Signal Type Comments 6 PIOS N/A - Controls pins LP[7:]. When, the pins are configured as outputs. The output values to the pins are set in POUT 7~. When, the pins are high-z. The input values to the pins are read in PIN 7~. 7 TCLK TCLK I 8 TDP TDP I 9 TDN TDN I CLK CLK O DP DP O DN DN O HZEN N/A - Controls pin DP, DN and CLK. When, the outputs are enabled on the pins. When, the pins are high-z. 4 LOS LOS O 5 TCLK TCLK I 6 TDP TDP I 7 TDN TDN I 8 CLK CLK O 9 DP DP O DN DN O HZEN N/A - Controls pin DP, DN and CLK. When, the outputs are enabled on the pins. When, the pins are high-z. LOS LOS O MODE MODE I 4 LOS LOS O 5 DN DN O 6 DP DP O 7 HZEN N/A - Controls pin DP, DN and CLK. When, the outputs are enabled on the pins. When, the pins are high-z. 8 CLK CLK O 9 TDN TDN I 4 TDP TDP I 4 TCLK TCLK I 4 LOS LOS O 4 DN DN O 44 DP DP O 45 HZEN N/A - Controls pin DP, DN and CLK. When, the outputs are enabled on the pins. When, the pins are high-z. 46 CLK CLK O 47 TDN TDN I 48 TDP TDP I 49 TCLK TCLK I 5 INT INT O 5 ACK ACK O 5 SDODYS N/A - Control pin ACK. When, the output is enabled on pin ACK. When, the pin is high-z. 5 WB DS I 54 DB I 55 ALE ALE I 56 CSB CS I 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table-9 Boundary Scan egister Description (Continued) Bit No. Bit Symbol Pin Signal Type Comments 57 MODE MODE I 58 TCLK5 TCLK5 I 59 TDP5 TDP5 I 6 TDN5 TDN5 I 6 CLK5 CLK5 O 6 DP5 DP5 O 6 DN5 DN5 O 64 HZEN5 N/A - Controls pin DP5, DN5 and CLK5. When, the outputs are enabled on the pins. When, the pins are high-z. 65 LOS5 LOS5 O 66 TCLK4 TCLK4 I 67 TDP4 TDP4 I 68 TDN4 TDN4 I 69 CLK4 CLK4 O 7 DP4 DP4 O 7 DN4 DN4 O 7 HZEN4 N/A - Controls pin DP4, DN4 and CLK4. When, the outputs are enabled on the pins. When, the pins are high-z. 7 LOS4 LOS4 O 74 OE OE I 75 CLKE CLKE I 76 LOS7 LOS7 O 77 DN7 DN7 O 78 DP7 DP7 O 79 HZEN7 N/A - Controls pin DP7, DN7 and CLK7. When, the outputs are enabled on the pins. When, the pins are high-z. 8 CLK7 CLK7 O 8 TDN7 TDN7 I 8 TDP7 TDP7 I 8 TCLK7 TCLK7 I 84 LOS6 LOS6 O 85 DN6 DN6 O 86 DP6 DP6 O 87 HZEN6 N/A - Controls pin DP6, DN6 and CLK6. When, the outputs are enabled on the pins. When, the pins are high-z. 88 CLK6 CLK6 O 89 TDN6 TDN6 I 9 TDP6 TDP6 I 9 TCLK6 TCLK6 I 9 MCLK MCLK I 9 MODE MODE I 94 A4 A4 I 95 A A I 96 A A I 97 A A I 98 A A I 6

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT 4. TEST ACCESS POT CONTOLLE The TAP controller is a 6-state synchronous state machine. Figure- shows its state diagram A description of each state follows. Note that the figure contains two main branches to access either the data or Table- TAP Controller State Description INDUSTIAL TEMPEATUE ANGES instruction registers. The value shown next to each state transition in this figure states the value present at TMS at each rising edge of TCK. efer to Table- for details of the state description. State Test Logic eset un-test/idle Select-D-Scan Capture-D Shift-D Exit-D Pause-D Exit-D Update-D Select-I-Scan Capture-I Shift-I Description In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. egardless of the original state of the controller, the controller enters the Test-Logic-eset state when the TMS input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically enters this state at power-up. This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller moves to the Select-D state. This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-D state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller moves to the Select-I-Scan state. In this state, the Boundary Scan egister captures input pin data if the current instruction is EXTEST or SAMPLE/PELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit-D state if TMS is high or the Shift-D state if TMS is low. In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit-D state if TMS is high or remains in the Shift-D state if TMS is low. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-D state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-D state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit-D state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-D state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-D state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The Boundary Scan egister is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST and SAMPLE/PELOAD instructions. When the TAP controller is in this state and the Boundary Scan egister is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state. This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-I state, and a scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-eset state. The instruction does not change during this state. In this controller state, the shift register contained in the instruction register loads a fixed value of on the rising edge of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit- I state if TMS is held high, or the Shift-I state if TMS is held low. In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit-I state if TMS is held high, or remains in the Shift-I state if TMS is held low. 7

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES Table- TAP Controller State Description (Continued) State Exit-I Pause-I Exit-I Update-I Description This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-I state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-I state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit-I state. This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-I state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-I state. The test data register selected by the current instruction retains its previous value and the instruction does not change during this state. The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain their previous value. Test-logic eset un Test/Idle Select-D Select-I Capture-D Capture-I Shift-D Shift-I Exit-D Exit-I Pause-D Pause-I Exit-D Exit-I Update-D Update-I Figure- JTAG State Diagram 8

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT ABSOLUTE MAXIMUM ATING INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Max Unit VDDA, VDDD Core Power Supply -.5 4. V VDDIO, VDDIO I/O Power Supply -.5 4. V VDDT-7 Transmit Power Supply -.5 7. V Vin. eferenced to ground. Human body model. Constant input current Input Voltage, any digital pin GND-.5 5.5 V Input Voltage (), TIPn pins and INGn pins ECOMMENDED OPEATING CONDITIONS GND-.5 VDDA+.5 VDDD+.5 ESD Voltage, any pin () V Transient Latch-up Current, any pin ma Iin Input Current, any digital pin () - ma DC Input Current, any analog pin () ± ma Pd Maximum Power Dissipation in package.6 W Tc Case Temperature C Ts Storage Temperature -65 +5 C CAUTION: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Min Typ Max Unit VDDA, VDDD Core Power Supply...47 V VDDIO I/O Power Supply...47 V VDDT Transmitter Supply. V...47 V 5 V 4.75 5. 5.5 V T A Ambient Operating Temperature -4 5 85 C L Output load at TTIPn pins and TINGn pins 5 W I VDD Average Core Power Supply Current () 4 6 ma I VDDIO I/O Power Supply Current () 5 5 ma I VDDT Average transmitter power supply current, E mode (), () 75 Ω 5% ones density data: 5 ma % ones density data: ma Ω 5% ones density data: ma % ones density data: ma. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.. Digital output is driving 5 pf load, digital input is within % of the supply rails.. Power consumption includes power absorbed by line load and external transmitter components. V V 9

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT POWE CONSUMPTION INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Typ Max ()() E,. V, 75 Ω Load 5% ones density data: % ones density data: E,. V, Ω Load 5% ones density data: % ones density data: E, 5. V, 75 Ω Load 5% ones density data: % ones density data: E, 5. V, Ω Load 5% ones density data: % ones density data:. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. - - - - - - - - 6 5 56 88 85 5 7 4-5 - 94-6 - Unit mw mw mw mw mw mw mw mw. Power consumption includes power absorbed by line load and external transmitter components. DC CHAACTEISTICS Symbol Parameter Min Typ Max Unit V IL Input Low Level Voltage MODE, JAS and LPn pins -- VDDIO-. V All other digital inputs pins.8 V V IM Input Mid Level Voltage MODE, JAS and LPn pins -- VDDIO+. -- VDDIO -- VDDIO-. V V IH Input High Voltage MODE, JAS and LPn pins -- VDDIO+. V All other digital inputs pins. V V OL Output Low level Voltage () (Iout =.6 ma).4 V V OH Output High level Voltage () (Iout = 4 µa).4 VDDIO V V MA Analog Input Quiescent Voltage (TIPn/INGn pin while floating)..4.47 V I H Input High Level Current (MODE, JAS and LPn pin) 5 µa I L Input Low Level Current (MODE, JAS and LPn pin) 5 µa I I Input Leakage Current TMS, TDI and TST pins All other digital input pins - 5 µa µa I ZL High-Z Leakage Current - µa Z OH Output High-Z on TTIPn pins and TINGn pins 5 kω. Output drivers will output CMOS logic levels into CMOS loads. 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT TANSMITTE CHAACTEISTICS INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Typ Max Unit V o-p Output Pulse Amplitudes ().4.7.6 V.7.. V V o-s 75 Ω load Ω load Zero (space) Level 75 Ω load Ω load Transmit Amplitude Variation with supply - + % Difference between pulse sequences for 7 consecutive pulses mv T PW Output Pulse Width at 5% of nominal amplitude 44 56 ns atio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval.95.5 TX Transmit eturn Loss (). Measured at the line output ports 75 Ω. Test at IDT8V58 evaluation board. Measured on device, between TTIPn and TINGn 5 khz khz khz.48 MHz.48 MHz.7 MHz 5 khz khz Ω khz.48 MHz.48 MHz.7 MHz Intrinsic Transmit Jitter (TCLK is jitter free, JA enabled) JTX P-P Hz khz.5 U.I. Td Transmit Path Delay (JA is disabled) Single ail 8 U.I. Dual ail U.I. I SC Line Short Circuit Current () 8 map -.7 -. 5 5 5 5 5 5.7. V V db db db db db db 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT ECEIVE CHAACTEISTICS INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Typ Max Unit ATT Permissible Cable Attenuation (@4 khz) 5 db IA Input Amplitude..9 Vp SI Signal to Interference atio Margin () -5 db SE Data Decision Threshold (refer to peak input voltage) 5 % Data Slicer Threshold 5 mv Analog Loss Of Signal () Declare/Clear: /5 /5 8/5 mvp Allowable consecutive zeros before LOS G.775: ETSI : LOS eset Clock ecovery Mode.5 % ones JX p-p Peak to Peak Intrinsic eceive Jitter (JA disabled).65 U.I. JTX Jitter Tolerance Hz Hz Hz.4 khz 8 khz khz ZDM eceiver Differential Input Impedance kω ZCM eceiver Common Mode Input Impedance to GND kω X eceive eturn Loss 5 khz khz khz.48 MHz.48 MHz.7 MHz eceive Path Delay Dual rail Single rail. Per G.7, O.5 @ 6 db cable attenuation. Measured on device, between TIP and ING, all ones signal. JITTE ATTENUATO CHAACTEISTICS Symbol Parameter Min Typ Max Unit f -db Jitter Transfer Function Corner Frequency ( db) Host mode: /64 bit FIFO JABW = : JABW = :.7 6.6 Hz Hz Hardware mode.7 Hz Jitter Attenuator () @ Hz @ 4 Hz @ 4 Hz @ khz td Jitter Attenuator Latency Delay bit FIFO: 64 bit FIFO: Input Jitter Tolerance before FIFO Overflow Or Underflow bit FIFO: 64 bit FIFO: Output Jitter in emote Loopback (). Per G.76, see Figure-8 on page 5.. Per ETSI CT/ output jitter. 8..5. -.5 -.5 +9.5 +9.5 48 8 6 8 56 U.I. U.I. U.I. db db db U.I. U.I. db db db db U.I. U.I. U.I. U.I.. U.I. 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT TANSCEIVE TIMING CHAACTEISTICS INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Typ Max Unit MCLK Frequency.48 MHz MCLK Tolerance - ppm MCLK Duty Cycle 4 6 % Transmit path TCLK Frequency.48 MHz TCLK Tolerance -5 +5 ppm TCLK Duty Cycle 9 % t Transmit Data Setup Time 4 ns t Transmit Data Hold Time 4 ns Delay Time of OE Low to Driver High-Z µs Delay Time of TCLK Low to Driver High-Z 4 44 48 µs eceive path Clock ecovery Capture ange () ± 8 ppm CLK Duty Cycle () 4 5 6 % t4 CLK Pulse Width () 457 488 59 ns t5 CLK Pulse Width Low Time 44 85 ns t6 CLK Pulse Width High Time 44 85 ns ise/fall Time () 5 ns t7 eceive Data Setup Time 44 ns t8 eceive Data Hold Time 44 ns t9 DPn/DNn Pulse Width (MCLK = High) (4) 44 ns. elative to nominal frequency, MCLK = ± ppm. CLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum CLK duty cycles are for worst case jitter conditions (. UI displacement for E per ITU G.8).. For all digital outputs. C load = 5 pf 4. Clock recovery is disabled in this mode. 4

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES TCLKn t t TDn/TDPn BPVIn/TDNn Figure- Transmit System Interface Timing t4 CLKn t6 t5 Dn/DPn (CLKE = ) CVn/DNn t7 t8 Dn/DPn (CLKE = ) CVn/DNn t7 t8 Figure-4 eceive System Interface Timing 44

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES JTAG TIMING CHAACTEISTICS Symbol Parameter Min Typ Max Unit Comments t TCK Period ns t TMS to TCK setup Time TDI to TCK Setup Time 5 ns t TCK to TMS Hold Time TCK to TDI Hold Time 5 ns t4 TCK to TDO Delay Time ns t TCK TMS t t TDI t4 TDO Figure-5 JTAG Interface Timing 45

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT PAALLEL HOST INTEFACE TIMING CHAACTEISTICS INTEL MODE EAD TIMING CHAACTEISTICS INDUSTIAL TEMPEATUE ANGES Symbol Parameter Min Typ Max Unit Comments t Active D Pulse Width 9 ns t Active CS to Active D Setup Time ns t Inactive D to Inactive CS Hold Time ns t4 Valid Address to Inactive ALE Setup Time (in Multiplexed Mode) 5 ns t5 Invalid D to Address Hold Time (in Non-Multiplexed Mode) ns t6 Active D to Data Output Enable Time 7.5 5 ns t7 Inactive D to Data High-Z Delay Time 7.5 5 ns t8 Active CS to DY delay time 6 ns t9 Inactive CS to DY High-Z Delay Time 6 ns t Inactive D to Inactive INT Delay Time ns t Address Latch Enable Pulse Width (in Multiplexed Mode) ns t Address Latch Enable to D Setup Time (in Multiplexed Mode) ns t Address Setup time to Valid Data Time (in Non-Multiplexed Mode) 8 ns t4 Inactive D to Active DY Delay Time 5 ns t5 Active D to Active DY Delay Time 85 ns t6 Inactive ALE to Address Hold Time (in Multiplexed Mode) 5 ns. The t is determined by the start time of the valid data when the DY signal is not used. () 46

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES CS t t D t ALE(=) t t5 A[4:] ADDESS D[7:] t6 DATA OUT t7 t8 t4 t9 DY INT t5 t Figure-6 Non-Multiplexed Intel Mode ead Timing CS D t t t ALE AD[7:] t t t6 t4 ADDESS t t6 DATA OUT t7 t8 t4 t9 DY INT t5 t Figure-7 Multiplexed Intel Mode ead Timing 47

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES INTEL MODE WITE TIMING CHAACTEISTICS Symbol Parameter Min Typ Max Unit Comments t Active W Pulse Width 9 ns () t Active CS to Active W Setup Time ns t Inactive W to Inactive CS Hold Time ns t4 Valid Address to Latch Enable Setup Time (in Multiplexed Mode) 5 ns t5 Invalid W to Address Hold Time (in Non-Multiplexed Mode) ns t6 Valid Data to Inactive W Setup Time 5 ns t7 Inactive W to Data Hold Time ns t8 Active CS to Inactive DY Delay Time 6 ns t9 Active W to Active DY Delay Time 85 ns t Inactive W to Inactive DY Delay Time 5 ns t Invalid CS to DY High-Z Delay Time 6 ns t Address Latch Enable Pulse Width (in Multiplexed Mode) ns t Inactive ALE to W Setup Time (in Multiplexed Mode) ns t4 Inactive ALE to Address hold time (in Multiplexed Mode) 5 ns t5 Address setup time to Inactive W time (in Non-Multiplexed Mode) 5 ns. The t can be 5 ns when DY signal is not used. CS W t t t ALE(=) A[4:] D[7:] DY t8 t5 ADDESS t9 t5 t6 t7 WITE DATA t t Figure-8 Non-Multiplexed Intel Mode Write Timing CS t t W t ALE t t AD[7:] DY t4 t4 t6 t7 ADDESS WITE DATA t8 t9 t Figure-9 Multiplexed Intel Mode Write Timing t 48

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES MOTOOLA MODE EAD TIMING CHAACTEISTICS Symbol Parameter Min Typ Max Unit Comments t Active DS Pulse Width 9 ns () t Active CS to Active DS Setup Time ns t Inactive DS to Inactive CS Hold Time ns t4 Valid to Active DS Setup Time ns t5 Inactive DS to Hold Time.5 ns t6 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) 5 ns t7 Active DS to Address Hold Time (in Non-Multiplexed Mode) ns t8 Active DS to Data Valid Delay Time (in Non-Multiplexed Mode) 5 ns t9 Active DS to Data Output Enable Time 7.5 5 ns t Inactive DS to Data High-Z Delay Time 7.5 5 ns t Active DS to Active ACK Delay Time 85 ns t Inactive DS to Inactive ACK Delay Time 5 ns t Inactive DS to Invalid INT Delay Time ns t4 Active AS to Active DS Setup Time (in Multiplexed Mode) 5 ns. The t is determined by the start time of the valid data when the ACK signal is not used. CS DS t4 t t t5 t ALE(=) A[4:] D[7:] t6 t7 ADDESS t9 t8 t DATA OUT t ACK INT t t Figure- Non-Multiplexed Motorola Mode ead Timing CS DS AS AD[7:] ACK INT t t t4 t t5 t4 t6 t8 t9 t7 t ADDESS DATA OUT t t t Figure- Multiplexed Motorola Mode ead Timing 49

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES MOTOOLA MODE WITE TIMING CHAACTEISTICS Symbol Parameter Min Typ Max Unit Comments t Active DS Pulse Width 9 ns () t Active CS to Active DS Setup Time ns t Inactive DS to Inactive CS Hold Time ns t4 Valid to Active DS Setup Time ns t5 Inactive DS to Hold Time ns t6 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) ns t7 Valid DS to Address Hold Time (in Non-Multiplexed Mode) ns t8 Valid Data to Inactive DS Setup Time 5 ns t9 Inactive DS to Data Hold Time ns t Active DS to Active ACK Delay Time 85 ns t Inactive DS to Inactive ACK Delay Time 5 ns t Active AS to Active DS (in Multiplexed Mode) ns t Inactive DS to Inactive AS Hold Time ( in Multiplexed Mode) 5 ns. The t can be 5ns when the ACK signal is not used. CS DS t4 t t t5 t ALE(=) A[4:] D[7:] t6 t7 ADDESS t t8 t9 WITE DATA t ACK Figure- Non-Multiplexed Motorola Mode Write Timing CS DS AS AD[7:] ACK t t t4 t t5 t t t6 t7 t8 t9 ADDESS WITE DATA t t Figure- Multiplexed Motorola Mode Writing Timing 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES SEIAL HOST INTEFACE TIMING CHAACTEISTICS Symbol Parameter Min Typ Max Unit Comments t SCLK High Time 5 ns t SCLK Low Time 5 ns t Active CS to SCLK Setup Time ns t4 Last SCLK Hold Time to Inactive CS Time 5 ns t5 CS Idle Time 5 ns t6 SDI to SCLK Setup Time 5 ns t7 SCLK to SDI Hold Time 5 ns t8 ise/fall Time (any pin) ns t9 SCLK ise and Fall Time 5 ns t SCLK to SDO Valid Delay Time 5 5 ns Load = 5 pf t SCLK Falling Edge to SDO High-Z Hold Time (CLKE = ) or CS ising Edge to SDO High-Z Hold Time (CLKE = ) ns CS SCLK SDI t t t t4 t5 t6 t7 t7 LSB LSB MSB CONTOL BYTE DATA BYTE Figure-4 Serial Interface Write Timing SCLK CS SDO 4 5 6 7 8 9 4 5 6 t t4 t 4 5 6 7 Figure-5 Serial Interface ead Timing with CLKE = SCLK CS SDO 4 5 6 7 8 t 9 4 5 6 t4 t 4 5 6 7 Figure-6 Serial Interface ead Timing with CLKE = 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT JITTE TOLEANCE PEFOMANCE INDUSTIAL TEMPEATUE ANGES G.8 IDT8V58 Jitter (UI) 8 UI @.8 Hz.5 UI @ Hz.5 UI @.4 khz Test condition: PBS ^5-; Line code rule HDB is used. Figure-7 Jitter Tolerance Performance JITTE TANSFE PEFOMANCE. UI @ 8 khz. 4 5 Frequency (Hz).5 db @ Hz.5 db @ 4 Hz G.76 IDT8V58 Gain (db) - -4-9.5 db @ 4 Hz -9.5 db @ khz fdb = 6.5 Hz fdb =.7 Hz -6 4 5 Test condition: PBS ^5-; Line code rule HDB is used. Frequency (Hz) Figure-8 Jitter Transfer Performance 5

IDT8V58 OCTAL E SHOT HAUL LINE INTEFACE UNIT INDUSTIAL TEMPEATUE ANGES ODEING INFOMATION XXXXXXX XX X Device Type Package Process/ Temperature ange Blank Industrial (-4 C to +85 C) BB BBG DA DAG Plastic Ball Grid Array (PBGA, BB6) Green Plastic Ball Grid Array (PBGA, BBG6) Thin Quad Flatpack (TQFP, DA44) Green Thin Quad Flatpack (TQFP, DAG44) 8V58 E Short Haul LIU DATASHEET DOCUMENT HISTOY /4/ pgs.,,, 7 // pgs. 5, 6,,, 6, 7, 4, 6,, 8, 9, 4, 5 /8/ pgs. 5, 4, 6, /9/ pgs. 5 /5/ pgs. 9 /4/ pgs.,, 9, 4, 9, 4 // pgs. 4, 6, 4 /5/ pgs.,, 5 4/7/ pgs. 7 5/7/ pgs. 4, 44, 45, 48 /5/ pgs., 5 4//5 pgs., 5 to 8,,, 4, 5, 8, 9, 9,, 4 to 4, 47 to 5 9/4/9 pg. 4 // pg. 8 COPOATE HEADQUATES 64 Silver Creek Valley oad San Jose, CA 958 www.idt.com for SALES: -8-45-75 or 48-84-8 fax: 48-84-775 for Tech Support: 48-6-55 email:telecomhelp@idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 5