I 2 C-Compatible, Wide Bandwidth, Triple 3:1 Multiplexer ADG793A/ADG793G

Transcription

1 I C-Compatible, Wide Bandwidth, Triple : Multiplexer ADG79A/ADG79G FEATURES Bandwidth: 9 MHz Low insertion loss and on resistance:.6 Ω typical On-resistance flatness. Ω typical. V analog signal range ( V supply, 7 Ω load) Single V/ V supply operation Low quiescent supply current: na typical Fast switching times: ton = 8 ns, toff = 8 ns I C -compatible interface Compact, -lead LFCSP Two I C-controllable logic outputs ESD protection kv human body model (HBM) V machine model (MM) kv field-induced charged device model (FICDM) APPLICATIONS RGB/YPbPr video switches HDTV Projection TV DVD-R/RW AV receivers SA SB SC SA SB SC SA SB SC A V DD FUNCTIONAL BLOCK DIAGRAMS ADG79A I CSERIAL INTERFACE A A SDA D D D SA SB SC SA SB SC SA SB SC GPO Figure. A V DD ADG79G I CSERIAL INTERFACE A A SDA D D D GPO 6- GENERAL DESCRIPTION The ADG79A/ADG79G are monolithic CMOS devices comprising three : multiplexers/demultiplexers controllable via a standard I C serial interface. The CMOS process provides ultralow power dissipation, yet gives high switching speed and low on resistance. The on-resistance profile is very flat over the full analog input range, and the wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG79A/ADG79G the ideal switching solution for a wide range of TV applications, including RGB and YPbPr video switches. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The ADG79A/ADG79G switches exhibit break-before-make switching action. The ADG79G has two general-purpose logic output pins controllable through the I C interface, which can be used to control other non-i C-compatible devices such as video filters. The integrated I C interface provides a large degree of flexibility in the system design. It has three configurable I C address pins that allow the user to connect up to eight devices to the same bus to build larger switching arrays. The ADG79A/ADG79G operate from a single V or V supply voltage and are available in a compact, mm mm body, -lead, lead-free chip scale package (LFCSP). PRODUCT HIGHLIGHTS. Wide bandwidth: 9 MHz.. Ultralow power dissipation.. Extended input signal range.. Integrated I C serial interface.. Compact, mm mm body, -lead, lead-free chip scale package (LFCSP). 6. ESD protection tested as per ESD Association standards: kv HBM (ANSI/ESD STM.-) V MM (ANSI/ESD STM.-999) kv FICDM (ANSI/ESDSTM..-999) Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADG79A/ADG79G TABLE OF CONTENTS Features... Applications... Functional Block Diagrams... General Description... Product Highlights... Revision History... Specifications... I C Timing Specifications... 7 Timing Diagram... 8 Absolute Maximum Ratings... 9 ESD Caution... 9 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Test Circuits... Terminology... 6 Theory of Operation... 7 I C Serial Interface... 7 I C Address... 7 Write Operation... 7 LDSW Bit... 9 Power On/Software Reset... 9 Read Operation... 9 Evaluation Board... Using the ADG79G Evaluation Board... Outline Dimensions... Ordering Guide... REVISION HISTORY 7/6 Revision : Initial Version Rev. Page of

3 SPECIFICATIONS VDD = V ± %, = V, TA = C to +8 C, unless otherwise noted. ADG79A/ADG79G Table. Parameter Conditions Min Typ Max Unit ANALOG SWITCH Analog Signal Range VS = VDD, RL = MΩ V VS = VDD, RL = 7 Ω. V On Resistance, RON VD = V, IS = ma, see Figure.6. Ω VD = V to V, IS = ma, see Figure Ω On-Resistance Matching Between VD = V, IS = ma.. Ω Channels, RON VD = V, IS = ma.6 Ω On-Resistance Flatness, RFLAT(ON) VD = V to V, IS = ma.. Ω LEAKAGE CURRENTS Source Off Leakage, IS(OFF) VD = V/ V, VS = V/ V, see Figure ±. na Drain Off Leakage, ID(OFF) VD = V/ V, VS = V/ V, see Figure ±. na Channel On Leakage, ID(ON), IS(ON) VD = VS = V/ V, see Figure ±. na DYNAMIC CHARACTERISTICS ton, tenable CL = pf, RL = Ω, VS = V, see Figure 8 8 ns toff, tdisable CL = pf, RL = Ω, VS = V, see Figure 8 8 ns Break-Before-Make Time Delay, td CL = pf, RL = Ω, VS = VS = V, ns see Figure 9 I C-to-GPO Propagation Delay, th, tl ADG79G only ns Off Isolation f = MHz, RL = Ω, see Figure 6 6 db Channel-to-Channel Crosstalk f = MHz, RL = Ω, see Figure 7 Same Multiplexer db Different Multiplexer 7 db db Bandwidth RL = Ω, see Figure 9 MHz THD + N RL = Ω. % Charge Injection CL = nf, VS = V, see Figure pc CS(OFF) pf CD(OFF) 6 pf CD(ON), CS(ON) 7 pf Power Supply Rejection Ratio, PSSR f = khz 7 db Differential Gain Error CCIR test signal.9 % Differential Phase Error CCIR test signal.8 Degrees LOGIC INPUTS A, A, A Input High Voltage, VINH. V Input Low Voltage, VINL.8 V Input Current, IINL or IINH VIN = V to VDD. ± μa Input Capacitance, CIN pf, SDA Input High Voltage, VINH.7 VDD VDD +. V Input Low Voltage, VINL. +. VDD V Input Leakage Current, IIN VIN = V to VDD. ± μa Input Hysteresis. VDD V Input Capacitance, CIN pf Rev. Page of

4 ADG79A/ADG79G Parameter Conditions Min Typ Max Unit LOGIC OUTPUTS SDA Pin Output Low Voltage, VOL ISINK = ma. V ISINK = 6 ma.6 V Floating-State Leakage Current ± μa Floating-State Output Capacitance pf GPO Pin and GPO Pin Output Low Voltage, VOL ILOAD = + ma. V Output High Voltage, VOH ILOAD = ma. V POWER REQUIREMENTS IDD Digital inputs = V or VDD, I C interface. μa inactive I C interface active, f = khz. ma I C interface active, f =. MHz.7 ma All typical values are at TA = C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test. Rev. Page of

5 ADG79A/ADG79G VDD = V ± %, = V, TA = C to +8 C, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit ANALOG SWITCH Analog Signal Range VS = VDD, RL = MΩ. V VS = VDD, RL = 7 Ω.7 V On Resistance, RON VD = V, IS = ma, see Figure Ω VD = V to V, IS = ma, see Figure 6 Ω On-Resistance Matching Between VD = V, IS = ma..6 Ω Channels, RON VD = V, IS = ma. Ω On-Resistance Flatness, RFLAT(ON) VD = V to V, IS = ma..8 Ω LEAKAGE CURRENTS Source Off Leakage, IS(OFF) VD = V/ V, VS = V/ V, see Figure ±. na Drain Off Leakage, ID(OFF) VD = V/ V, VS = V/ V, see Figure ±. na Channel On Leakage, ID(ON), IS(ON) VD = VS = V/ V, see Figure ±. na DYNAMIC CHARACTERISTICS ton, tenable CL = pf, RL = Ω, VS = V, see Figure 8 6 ns toff, tdisable CL = pf, RL = Ω, VS = V, see Figure 8 97 ns Break-Before-Make Time Delay, td CL = pf, RL = Ω, VS = VS = V, ns see Figure 9 I C-to-GPO Propagation Delay, th, tl ADG79G only ns Off Isolation f = MHz, RL = Ω, see Figure 6 6 db Channel-to-Channel Crosstalk f = MHz, RL = Ω, see Figure 7 Same Multiplexer db Different Multiplexer 7 db db Bandwidth RL = Ω, see Figure 9 MHz THD + N RL = Ω. % Charge Injection CL = nf, VS = V, see Figure. pc CS(OFF) pf CD(OFF) 6 pf CD(ON), CS(ON) 7 pf Power Supply Rejection Ratio, PSRR f = khz 7 db Differential Gain Error CCIR test signal. % Differential Phase Error CCIR test signal.6 Degrees LOGIC INPUTS A, A, A Input High Voltage, VINH. V Input Low Voltage, VINL.8 V Input Current, IINL or IINH VIN = V to VDD. ± μa Input Capacitance, CIN pf, SDA Input High Voltage, VINH.7 VDD VDD +. V Input Low Voltage, VINL. +. VDD V Input Leakage Current, IIN VIN = V to VDD. ± μa Input Hysteresis. VDD V Input Capacitance, CIN pf Rev. Page of

6 ADG79A/ADG79G Parameter Conditions Min Typ Max Unit LOGIC OUTPUTS SDA Pin Output Low Voltage, VOL ISINK = ma. V ISINK = 6 ma.6 V Floating-State Leakage Current ± μa Floating-State Output Capacitance pf GPO Pin and GPO Pin Output Low Voltage, VOL ILOAD = + ma. V Output High Voltage, VOH ILOAD = ma. V POWER REQUIREMENTS IDD Digital inputs = V or VDD, I C interface. μa inactive I C interface active, f = khz. ma I C interface active, f =. MHz. ma All typical values are at TA = C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test. Rev. Page 6 of

7 I C TIMING SPECIFICATIONS VDD =.7 V to. V; = V; TA = C to +8 C, unless otherwise noted. See Figure for timing diagram. Table. Parameter Conditions Min Max Unit Description f Standard mode khz Serial clock frequency Fast mode khz High speed mode CB = pf max. MHz CB = pf max.7 MHz t Standard mode μs thigh, high time Fast mode.6 μs High speed mode CB = pf max 6 ns CB = pf max ns t Standard mode.7 μs tlow, low time Fast mode. μs High speed mode CB = pf max 6 ns CB = pf max ns t Standard mode ns tsu;dat, data setup time Fast mode ns High speed mode ns t Standard mode. μs thd;dat, data hold time Fast mode.9 μs High speed mode CB = pf max 7 ns CB = pf max ns ADG79A/ADG79G t Standard mode.7 μs tsu;sta, setup time for a repeated start condition Fast mode.6 μs High speed mode 6 ns t6 Standard mode μs thd;sta, hold time (repeated) start condition Fast mode.6 μs High speed mode 6 ns t7 Standard mode.7 μs tbuf, bus free-time between a stop and a start condition Fast mode. μs t8 Standard mode μs tsu;sto, setup time for stop condition Fast mode.6 μs High speed mode 6 ns t9 Standard mode ns trda, rise time of SDA signal Fast mode +. CB ns High speed mode CB = pf max 8 ns CB = pf max 6 ns t Standard mode ns tfda, fall time of SDA signal Fast mode +. CB ns High speed mode CB = pf max 8 ns CB = pf max 6 ns Rev. Page 7 of

8 ADG79A/ADG79G Parameter Conditions Min Max Unit Description t Standard mode ns trcl, rise time of signal Fast mode +. CB ns High speed mode CB = pf max ns CB = pf max 8 ns ta Standard mode ns trcl, rise time of signal after a repeated start condition and after an acknowledge bit Fast mode +. CB ns High speed mode CB = pf max 8 ns CB = pf max 6 ns t Standard mode ns tfcl, fall time of signal Fast mode +. CB ns High speed mode CB = pf max ns CB = pf max 8 ns tsp Fast mode ns Pulse width of suppressed spike High speed mode ns Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between. VDD and.7 VDD. A device must provide a data hold time for SDA in order to bridge the undefined region of the falling edge. TIMING DIAGRAM t t t t 6 t 6 t t t 8 t t t t 9 SDA t 7 P S S P 6- Figure. Timing Diagram for -Wire Serial Interface Rev. Page 8 of

9 ADG79A/ADG79G ABSOLUTE MAXIMUM RATINGS TA = C, unless otherwise noted. Table. Parameter Rating VDD to. V to +6 V Analog, Digital Inputs. V to VDD +. V or ma, whichever occurs first Continuous Current, S or D Pins ma Peak Current, S or D Pins ma (pulsed at ms, % duty cycle max) Operating Temperature Range Industrial (B Version) C to +8 C Storage Temperature Range 6 C to + C Junction Temperature C θja Thermal Impedance -Lead LFCSP C/W Lead Temperature, Soldering ( sec) C IR Reflow, Peak Temperature (< sec) 6 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page 9 of

10 SA 7 SB 8 D 9 SDA NC SC NC A 9 A SA 7 SB 8 D 9 SDA NC SC GPO A 9 A ADG79A/ADG79G PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD V DD SA SB D NC SC NC 6 PIN INDICATOR ADG79A TOP VIEW (Not to Scale) 8 A 7 SC 6 NC D SB SA SA SB D NC SC GPO 6 PIN INDICATOR ADG79G TOP VIEW (Not to Scale) 8 A 7 SC 6 NC D SB SA NOTES. NC = NO CONNECT.. THE EXPOSED PAD MUST BE TIED TO. Figure. ADG79A Pin Configuration 6-9 NOTES. NC = NO CONNECT.. THE EXPOSED PAD MUST BE TIED TO. Figure. ADG79G Pin Configuration 6- Table. Pin Function Descriptions Pin No. Mnemonic Description SA A-Side Source Terminal for Mux. Can be an input or output. SB B-Side Source Terminal for Mux. Can be an input or output. D Drain Terminal for Mux. Can be an input or output. NC Not internally connected. SC C-Side Source Terminal for Mux. Can be an input or output. 6 NC/GPO Not internally connected for ADG79A. General-Purpose Logic Output for ADG79G. 7 SA A-Side Source Terminal for Mux. Can be an input or output. 8 SB B-Side Source Terminal for Mux. Can be an input or output. 9 D Drain Terminal for Mux. Can be an input or output. NC Not internally connected. SC C-Side Source Terminal for Mux. Can be an input or output. NC/GPO Not internally connected for ADG79A. General-Purpose Logic Output for ADG79G. SA A-Side Source Terminal for Mux. Can be an input or output SB B-Side Source Terminal for Mux. Can be an input or output. D Drain Terminal for Mux. Can be an input or output. 6 NC Not internally connected. 7 SC C-Side Source Terminal for Mux. Can be an input or output. 8 A Logic Input. Sets Bit A from the third least significant bit of the 7-bit slave address. 9 A Logic Input. Sets Bit A from the second least significant bit of the 7-bit slave address. A Logic Input. Sets Bit A from the first least significant bit of the 7-bit slave address. Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into the device. External pull-up resistor required. SDA Digital I/O. Bidirectional open-drain data line. External pull-up resistor required. VDD Positive Power Supply Input. Ground ( V) Reference. Rev. Page of

11 ADG79A/ADG79G TYPICAL PERFORMANCE CHARACTERISTICS.. T A = C CHANNEL V DD =V,R L =MΩ V DD =.V,R L =MΩ.. T A = C CHANNEL V DD =.V V DD =.V V DD =.7V,R L =MΩ. V DD =.V OUTPUT SIGNAL (V)... V DD =.V,R L =7Ω V DD =.7V,R L =7Ω V DD =V,R L =7Ω (Ω) R ON INPUT SIGNAL (V) Figure. Analog Signal Range ( V Supply) V D (V S )(V) Figure 8. On Resistance vs. VD (VS) with V Supply 6-6 OUTPUT SIGNAL (V) V V DD =.V,R L =MΩ DD =V,R L =MΩ V DD =.V,R L =7Ω V DD =.V,R L =MΩ V DD =V,R L =7Ω V DD =.V,R L =7Ω R ON (Ω) 7 6 T A = C CHANNEL V DD =V T A = + C T A =+8 C T A = C.. T A = C CHANNEL 6 INPUT SIGNAL (V) Figure 6. Analog Signal Range ( V Supply) V D (V S )(V) Figure 9. On Resistance vs. VD (VS) for Various Temperatures with V Supply T A = C CHANNEL V DD =.7V V DD =.V. T A =+ C CHANNEL. V DD =V. T A = +8 C T A = + C T A = C V DD =.V. R ON (Ω) (Ω) R ON V D (V S )(V) Figure 7. On Resistance vs. VD (VS) with V Supply V D (V S )(V) Figure. On Resistance vs. VD (VS) for Various Temperatures with V Supply 6-8 Rev. Page of

12 ADG79A/ADG79G T A = C T A = C V DD =V/V CHARGE INJECTION (pc) V DD =V V DD =V CROSSTALK (db) 6 8 SAME MULTIPLEXER DIFFERENT MULTIPLEXER SOURCE VOLTAGE (V) FREQUENCY (MHz) 6- Figure. Charge Injection vs. Source Voltage Figure. Crosstalk vs. Frequency t ON /t OFF (ns) t ON (V) t OFF (V) t ON (V) t OFF (V) ATTENUATION (db) T A = C V DD =V TEMPERATURE ( C) 6-.. FREQUENCY (MHz) 6- Figure. ton/toff vs. Temperature Figure. Bandwidth T A = C V DD =V/V T A = C CHANNEL V DD =V/V NO DECOUPLING CAPACITORS USED OFF ISOLATION (db) 6 8 PSRR (db) FREQUENCY (MHz) FREQUENCY (MHz) 6- Figure. Off Isolation vs. Frequency Figure 6. PSRR vs. Frequency Rev. Page of

13 ADG79A/ADG79G. T A = C 6 T A = C. I DD (ma).... V DD =V V DD =V GPO VOLTAGE (V) V DD =V V DD =V f CLK FREQUENCY (MHz) Figure 7. IDD vs. fclk Frequency LOAD CURRENT (ma) Figure. GPO VOH vs. Load Current 6-8. T A = C. T A = C.. V DD =V. V DD =V V DD =V I DD (ma) V DD =V GPO VOLTAGE (V) I C LOGIC INPUT VOLTAGE (V) Figure 8. IDD vs. I C Logic Input Voltage (SDA, ) 6-6 LOAD CURRENT (ma) Figure. GPO VOL vs. Load Current 6-9 PROPAGATION DELAY (ns) t PHL (V) t PLH (V) t PHL (V) t PLH (V) TEMPERATURE ( C) Figure 9. I C-to-GPO Propagation Delay vs. Temperature 6-7 Rev. Page of

14 ADG79A/ADG79G TEST CIRCUITS V DD I DS.µF V SA Ω NETWORK ANALYZER Ω S D SB V S V S R ON =V/I DS 6- D Ω Ω V OUT Figure. On Resistance Figure. Bandwidth 6- V DD.µF I S (OFF) A S D I D (OFF) A S Ω NETWORK ANALYZER Ω V S V D 6- D Ω Ω V S V OUT Ω 6-6 Figure. Off Leakage Figure 6. Off Isolation V DD NC S D I D (ON) A.µF SX Ω NETWORK ANALYZER Ω V S NC = NO CONNECT V D 6- SY DY Ω V OUT R L Ω DX Figure. On Leakage Ω Ω Figure 7. Channel-to-Channel Crosstalk 6-7 Rev. Page of

15 ADG79A/ADG79G CLOCK PULSES CORRESPONDING TO THE LDSW BITS V % %.µf V OUT 9% % V DD t ON t OFF S D V OUT V S I C INTERFACE R L Ω C L pf CLOCK PULSES CORRESPONDING TO THE LDSW BITS % % SDA V GPO t H 9% % t L 6- Figure 8. Switching Times V.µF CLOCK PULSE CORRESPONDING TO THE LDSW BIT V S SA SB V DD I C INTERFACE D R L Ω V OUT C L pf V OUT 8% V S t D SDA Figure 9. Break-Before-Make Time Delay 6- V V DD SWITCH ON R S S D V OUT SWITCH OFF ΔV OUT V S C L nf Q INJ =C L ΔV OUT 6-8 Figure. Charge Injection Rev. Page of

16 ADG79A/ADG79G TERMINOLOGY On Resistance (RON) The series on-channel resistance measured between the S pin and D pin. On Resistance Match (ΔRON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. On Resistance Flatness (RFLAT(ON)) The variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. Channel Off Leakage (IOFF) The sum of leakage currents into or out of an off channel input. Channel On Leakage (ION) The current loss/gain through an on-channel resistance, creating a voltage offset across the device. Input Leakage Current (IIN, IINL, IINH) The current flowing into a digital input when a specified low level voltage or high level voltage is applied to that input. Input/Output Off Capacitance (COFF) The capacitance between an analog input and ground when the switch channel is off. Input/Output On Capacitance (CON) The capacitance between the inputs or outputs and ground when the switch channel is on. Digital Input Capacitance (CIN) The capacitance between a digital input and ground. Output On Switching Time (ton) The time required for the switch channel to close. The time is measured from % of the falling edge of the LDSW bit to the time the output reaches 9% of the final value. Output Off Switching Time (toff) The time required for the switch to open. The time is measured from % of the falling edge of the load switch (LDSW) bit to the time the output reaches % of the final value. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. db Bandwidth The frequency at which the output is attenuated by db. Off Isolation The measure of unwanted signal coupling through an off switch. Crosstalk The measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Charge Injection The measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Differential Gain Error The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and expressed in percent (%). Differential Phase Error The measure of how much hue shift occurs when the luminance level changes. It can be a negative or positive value and is expressed in degrees of subcarrier phase. Input High Voltage (VINH) The minimum input voltage for Logic. Input Low Voltage (VINL) The maximum input voltage for Logic. Output High Voltage (VOH) The minimum input voltage for Logic. Output Low Voltage (VOL) The maximum output voltage for Logic. IDD Positive supply current. I C-to-GPO Propagation Delay (th, tl) The time required for the logic value at the GPO pin to settle after loading a GPO command. The time is measured from % of the falling edge of the LDSW bit to the time the output reaches 9% of the final value for high and % for low. Rev. Page 6 of

17 ADG79A/ADG79G THEORY OF OPERATION The ADG79A/ADG79G are monolithic CMOS devices comprising three : multiplexers/demultiplexers controllable via a standard I C serial interface. The CMOS process provides ultralow power dissipation, yet gives high switching speed and low on resistance. The on-resistance profile is very flat over the full analog input range, and the wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range make the ADG79A/ADG79G the ideal switching solution for a wide range of TV applications. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The integrated serial I C interface controls the operation of the multiplexers and general-purpose logic pins (ADG79G only). The ADG79A/ADG79G has many attractive features, such as the ability to individually control each multiplexer, the option of reading back the status of any switch, and two general purpose logic output pins controllable through the I C interface. The following sections describe these features in more detail. I C SERIAL INTERFACE The ADG79A/ADG79G are controlled via an I C-compatible serial bus interface (refer to the I C-Bus Specification available from Philips Semiconductor) that allows the part to operate as a slave device (no clock is generated by the ADG79A/ ADG79G). The communication protocol between the I C master and the device operates as follows.. The master initiates data transfer by establishing a start condition defined as a high-to-low transition on the SDA line while is high. This indicates that an address/data stream follows. All slave devices connected to the bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit. This bit determines the direction of the data flow during the communication between the master and the addressed slave device.. The slave device whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device.. Data transmits over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of the clock signal,, and remain stable during the high period of, because a low-to-high transition when the clock signal is high can be interpreted as a stop event which ends the communication between the master and the addressed slave device.. After transferring all data bytes, the master establishes a stop condition, defined as a low-to-high transition on the SDA line while is high. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (the SDA line remains high). The master brings the SDA line low before the tenth clock pulse and then high during the tenth clock pulse to establish a stop condition. I C ADDRESS The ADG79A/ADG79G have a 7-bit I C address. The four most significant bits are internally hardwired and the last three bits A, A, and A are user-adjustable. This allows the user to connect up to eight ADG79As/ADG79Gs to the same bus. The I C bit map shows the configuration of the 7-bit address. 7-Bit I C Address Bit Configuration MSB LSB A A A WRITE OPERATION When writing to the ADG79A/ADG79G, the user must begin with an address byte and R/W bit, after which time the switch acknowledges that it is prepared to receive data by pulling SDA low. Data is loaded into the device as a 6-bit word under the control of a serial clock input,. Figure illustrates the entire write sequence for the ADG79A/ ADG79G. The first data byte (AX7 to AX) controls the status of the switches and the LDSW and RESETB bits from the second byte control the operation mode of the device. Table 6 shows a list of all commands supported by the ADG79A/ ADG79G with the corresponding byte that needs to be loaded during a write operation. To achieve the desired configuration, one or more commands can be loaded into the device. Any combination of the commands in Table 6 can be used with these restrictions: Only one switch from a given multiplexer can be on at any given time. When a sequence of successive commands affect the same element (that is, the switch or GPO pin), only the last command is executed. Rev. Page 7 of

18 ADG79A/ADG79G SDA A A A R/W AX7 AX6 AX AX AX AX AX AX X X X X X X START CONDITION BY MASTER ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH RESETB LDSW ACKNOWLEDGE BY SWITCH STOP CONDITION BY MASTER 6- Figure. Write Operation Table 6. ADG79A/ADG79G Command List AX7 AX6 AX AX AX AX AX AX Addressed Switch/GPO Pin SA/D, SA/D, SA/D off SA/D, SA/D, SA/D on SB/D, SB/D, SB/D off SB/D, SB/D, SB/D on SC/D, SC/D, SC/D off SC/D, SC/D, SC/D on X Reserved SA/D off SA/D on SB/D off SB/D on SC/D off SC/D on X Reserved SA/D off SA/D on SB/D off SB/D on SC/D off SC/D on X Reserved SA/D off SA/D on SB/D off SB/D on S/C/D off S/C/D on X Reserved X Mux disabled (all switches connected to D are off) X Mux disabled (all switches connected to D are off) X Mux disabled (all switches connected to D are off) Reserved for ADG79A/GPO low for ADG79G Reserved for ADG79A/GPO high for ADG79G Reserved for ADG79A/GPO low for ADG79G Reserved for ADG79A/GPO high for ADG79G Reserved for ADG79A/GPO, GPO low for ADG79G Reserved for ADG79A/GPO, GPO high for ADG79G All muxes disabled (all switches are off) Reserved X = Logic state does not matter. Rev. Page 8 of

19 ADG79A/ADG79G LDSW BIT The LDSW bit allows the user to control the way the device executes the commands loaded during the write operations. The ADG79A/ADG79G execute all the commands loaded between two successive write operations that have set the LDSW bit high. Setting the LDSW high for every write cycle ensures that the device executes the command right after the LDSW bit was loaded into the device. This setting can be used when the desired configuration can be achieved by sending a single command or when the switches and/or GPO pin are not required to be updated at the same time. When the desired configuration requires multiple commands with simultaneous updates, the LDSW bit should be set low while loading the commands, except the last one when the LDSW bit should be set high. Once the last command with LDSW = high is loaded, the device executes all commands received since the last update simultaneously. READ OPERATION When reading data back from the ADG79A/ADG79G, the user must begin with an address byte and R/W bit. The switch then acknowledges that it is prepared to transmit data by pulling SDA low. Following this acknowledgement, the ADG79A/ADG79G transmit two bytes on the next clock edges. These bytes contain the status of the switches, and each byte is followed by an acknowledge bit. A logic high bit represents a switch in the on (close) state while a low represents a switch in the off (open) state. For the GPO pin (ADG79G only), the bit represents the logic value of the pin. Figure illustrates the entire read sequence. The bit maps accompanying Figure show the relationship between the elements of the ADG79A and ADG79G (that it, the switches and GPO pins) and the bits that represent their status after a completed read operation. POWER ON/SOFTWARE RESET The ADG79A/ADG79G have a software reset function implemented by the RESETB bit from the second data byte loaded into the device during a write operation. For normal operation of the multiplexers and GPO pins, this bit should be set high. When RESETB = low or after power-up, the switches from all multiplexers are turned off (open) and the GPO pins are set low. Bit Map for the ADG79A RB RB RB RB RB RB RB9 RB8 RB7 RB6 RB RB RB RB RB RB SA-D SB-D SC-D - SA-D SB-D SC-D - SA-D SB-D SC-D Bit Map for the ADG79G RB RB RB RB RB RB RB9 RB8 RB7 RB6 RB RB RB RB RB RB SA-D SB-D SC-D - SA-D SB-D SC-D - SA-D SB-D SC-D - GPO GPO - - Read Operation SDA A A A R/W RB RB RB RB RB RB RB9 RB8 RB7 RB6 RB RB RB RB RB RB START CONDITION BY MASTER ADDRESS BYTE ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH ACKNOWLEDGE BY SWITCH STOP CONDITION BY MASTER 6- Figure. ADG79A/ADG79G Read Operation Rev. Page 9 of

20 ADG79A/ADG79G EVALUATION BOARD The ADG79G evaluation kit allows designers to evaluate the high performance of the device with a minimum of effort. The evaluation kit includes a printed circuit board populated with the ADG79G. The evaluation board can be used to evaluate the performance of both the ADG79A and ADG79G. It interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. USING THE ADG79G EVALUATION BOARD The ADG79G evaluation kit is a test system designed to simplify the evaluation of the device. Each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. An evaluation board data sheet is also available and provides full instructions for operating the evaluation board. Software is available with the evaluation board that allows the user to program the ADG79G easily through the USB port. The software runs on any PC that has Microsoft Windows or Windows XP installed with a minimum screen resolution of 768. See Figure and Figure for schematics of the evaluation board. Rev. Page of

21 ADG79A/ADG79G J- J- T T SHIELD J USB-MINI-B VBUS D D+ IO.V.V C µf.v.v R 7Ω C9.µF R6 7Ω R7 Ω C8 C.µF C.µF RESET *WAKEUP CLKOUT D D+ PA/INT PA/INT PA/*SLOE PA/*WU PA/FIFOADR PA/FIFOADR PA6/*PKTEND PA7/*FLD/SLCS RDY/*SLRD RDY/*SLWR IFCLK RSVD.V 8 PB/FD 9 PB/FD PB/FD PB/FD PB/FD PB/FD PB6/FD6 PB7/FD7 PD/FD8 6 PD/FD9 7 PD/FD 8 PD/FD 9 PD/FD PD/FD PD6/FD PD7/FD.V 9 6 R.kΩ R.kΩ.V S Q D.V C.µF AVCC VCC VCC VCC VCC VCC VCC VCC R kω A CTL/*FLAGA CTL/*FLAGB CTL/*FLAGC SDA XTALOUT R kω XTALIN XTAL MHz R kω _EN R R9.kΩ R9.kΩ C µf.v VDD C.µF C6.µF C7.µF J A B C.µF ADP IN IN SD OUT OUT ERROR NR U C.µF C8.µF C9.µF C.µF C.µF 6 U CY7C68-CS P C7 pf LC6 A A A VSS U VCC WP SDA T7 T C pf T6.V C6.µF C µf C.µF R kω.v D G S Q D G U ADG8 8 S VDD D IN IN D S 7 6 _EN VDD SDA 6- *DENOTES PROGRAMMABLE POLARITY. Figure. EVAL-ADG79GEB Schematic, USB Controller Section Rev. Page of

22 ADG79A/ADG79G K BOTTOM TOP PHONO_DUAL K BOTTOM TOP PHONO_DUAL K6 BOTTOM TOP PHONO_DUAL R9 R R R R R T T T A T T T T T GPO VDD T T T T A ADG79G PADDLE 9 R6 Ω T7 T8 T9 T T U K7 BOTTOM TOP PHONO_DUAL K8 BOTTOM TOP PHONO_DUAL K9 BOTTOM TOP PHONO_DUAL R R6 R7 R8 R9 R 6 R kω R kω R8 kω J J7 J8 R Ω R Ω R R R R6 R7 R8 PHONO_DUAL TOP BOTTOM K PHONO_DUAL TOP BOTTOM K PHONO_DUAL TOP BOTTOM K GPO GPO GPO J6- J6- J6- SDA C.µF SDA T6 T7 T8 T9 T T SDA J- J- J- 6- Figure. EVAL-ADG79GEB Schematic, Chip Section Rev. Page of

23 ADG79A/ADG79G OUTLINE DIMENSIONS PIN INDICATOR..8.8 MAX. BSC SQ TOP VIEW.8 MAX.6 TYP.7 BSC SQ. MAX. NOM.6 MAX. BSC MAX EXPOSED PA D (BOTTOMVIEW) PIN INDICATOR *.. SQ MIN. REF SEATING PLANE...8. REF COPLANARITY.8 *COMPLIANT TO JEDEC STANDARDS MO--VGGD- EXCEPT FOR EXPOSED PAD DIMENSION Figure. -Lead Lead Frame Chip Scale Package [LFCSP_VQ] mm mm Body, Very Thin Quad (CP--) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range I C Speed Package Description Package Option ADG79ABCPZ-REEL C to +8 C khz, khz -Lead LFCSP_VQ CP-- ADG79ABCPZ-RL7 C to +8 C khz, khz -Lead LFCSP_VQ CP-- ADG79ACCPZ-REEL C to +8 C khz, khz,. MHz -Lead LFCSP_VQ CP-- ADG79ACCPZ-RL7 C to +8 C khz, khz,. MHz -Lead LFCSP_VQ CP-- ADG79GBCPZ-REEL C to +8 C khz, khz -Lead LFCSP_VQ CP-- ADG79GBCPZ-RL7 C to +8 C khz, khz -Lead LFCSP_VQ CP-- ADG79GCCPZ-REEL C to +8 C khz, khz,. MHz -Lead LFCSP_VQ CP-- ADG79GCCPZ-RL7 C to +8 C khz, khz,. MHz -Lead LFCSP_VQ CP-- EVAL-ADG79GEB Evaluation Board Z = Pb-free part. Evaluation board is RoHS compliant. Rev. Page of

24 ADG79A/ADG79G NOTES Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D6 7/6() Rev. Page of