Introduction to USB 3.1 Re-timer

Transcription

1 Introduction to USB 3.1 Retimer Huimin Chen, Howard Heck Intel Corporation Developer Days 2016 Hong Kong October 19 20,

2 In Memory of Neil Winchester (Microchip) 2

3 Agenda: USB 3.1 Retimer Retimer concept and classifications Challenges of USB 3.1 retimers Problem statement on SRIS retimer in SS operation Pending_HP_timer ECN Link delay budgeting Introduction to bitlevel retimer Motivation and architecture Sequential BLR training BLR compliance test Summary Q&A 3

4 Retimer Concept and Classifications Retimer concept SRIS retimer Bitlevel retimer (BLR) USB 3.1 retimer 4

5 Redriver Retimer concept RxAFE Analog Analog Digital Analog Retimer RxAFE CDR CLK To recondition the receiver signal on each unit interval A digital approach based on clock data recovery Less challenging in analog design A nonlinear solution that is more process friendly 5

6 SRIS Retimer RxAFE CDR EB RxCLK Ref Clock CLK PLL SRIS: separate refclock, independent SSC Transmit clock based on a local reference clock no jitter dependency on RxCLK An Elastic Buffer needed to handle phase/frequency offset between RxCLK and CLK A nonlinear solution that is more process friendly 6

7 BitLevel Retimer (BLR) RxAFE CDR FIFO RxCLK CLK Jitter Attenuator Jitter suppression filter No refclock is necessary CLK derived from RxCLK There is an inherent initialization delay to establish quality CLK jitter depends on jitter attenuator performance does not reset jitter Only a FIFO needed to handle phase offset between RxCLK and CLK Very small propagation delay A low cost implementation without need for external reference 7

8 USB 3.1 Retimer Rx Symbol Recovery Linecode dec descrambling Protocol intercept RD monitor Frame OS detection EB SRIS based Protocol aware DFP/UFP identification Link state aware RTSSM LTSSM RTSM LTSSM RTSSM to handle link operation RD monitor Protocol intercept Frame OS detection Linecode dec descrambling EB Symbol Recovery Rx Appendix E is intended to define a USB 3.1 retimer architecture for interop 8

9 USB 3.1 Retimer Appendix E Recap What went wrong with retimer Root cause Link delay budgeting 9

10 Issue #1: SCD2 Handshake Failure in Polling.LFPSPlus The delay introduced by retimers forwarding Polling.LFPS led to two SSP port failing to achieve SCD2 exit handshake Appendix E: Each retimer is allowed to store and forward 4~8 Polling.LFPS Delay by each retimer is additive 4 retimers will incur 16~32 Polling.LFPS equivalent to 4~8 SCDx Base Spec: in Polling.LFPSPlus, a host or device will switch to SS operation if it cannot detect SCD2 within 16 Polling.LFPS With multiple retimers SCD2 handshake will fail This issue is fixable if Constrain store and forward to one Polling.LFPS AND Relax timing for host/device to fall back to SS operation 16 Polling.LFPS to 16 SCDx No need to optimize for corner case

11 Issue #2: Recovery due to Pending_HP_Timer Timeout PA at Host Side Pending_HP_Timer = 3.4uS With retimer delay Delay due to outbound DP at transmitter leads to timeout of Pending_HP_timer!

12 EndtoEnd Link Delay An General View USB 3.1 Host PCB Cable Assembly Legacy USB 3.0 Device Host p n Rxp Rxn AC C apacit or Retimer Retimer LGOOD HP Retimer Rxp Rxn p n Device A DP of maximum payload 4 SKP OS accounts for 2.14us (SS)! Note for SSP, it is < 926ns AC C apacit or NO timing margin left in SS operation to accommodate for retimer delay Fundamental USB 3.1 technology limitation mandating performance 12

13 Pending_HP_Timer ECN Intended to support 50m cable Explicit test point for compliance test New requirement defined for backwards compatibility Want: maximum interop with legacy and extensible to new connectivity models 13

14 Retimer Connectivity Models 3 S USB 3.1 Host p n Host Rxp Rxn AC Capacitor Retimer Active Cable Retimer Captive retimer 10 S USB 3.1 Device Rxp Rxn p n Device AC Capacitor 3retimer USB 3.1 connectivity At least one of the DFP/UFP implements the 3µs Pending_HP_Timer Can only support max of three retimers 5m maximum for active cables Host 10 S USB 3.1 Host p n Rxp Rxn AC Capacitor Captive retimer Retimer Active Cable Retimer Captive retimer 10 S USB 3.1 Device Rxp Rxn p n Device AC Capacitor 4retimer USB 3.1 connectivity Both DFP/UFP implement the 10µs Pending_HP_Timer Can support at least four retimers 50m maximum for active cables (note: may not be backwards compatible) The link delay budget is defined based on 3retimer USB3.1 connectivity model 14

15 Link Delay Budgeting Pending_HP_Timer defines the link delay budget Active cable delay including two retimers and 5m cable (tdcable) Transmit/receive data path delay of the HP initiator (tdtdrx) Note: applies only to implementation with 3µs Pending_HP_Timer HP processing time of the HP responder (thpresponse) Transmit/receive datapath delay Worst case transmit scheduling delay (Max DP SKP) Captive retimer delay HP Initiator Host p n Rxp Rxn AC Capacitor td tdrx Retimer Active Cable tdcable tdcable Retimer Captive retimer HP Responder AC Capacitor Rxp tdhpresponse Rxn p n Device Link delay budget SS (ns) SSP (ns) tdtdrx tdcable tdhpresponse tdretimer Timing Term (ns) Pending_HP_Timer 3000 tdtdrx 200 Timing budget 2800 tcable Delay (5m) 125 thpresponsetime 2540 tcabledelay (5m) 125 5m Active Cable Delay HP Responder Delay 2790 Timing margin 10 Timing margin per 2500ns 290 Best effort link delay budgeting with no margin 15

16 Summary of Retimer Problem Statement USB 3.1 SS operation does not consider the need for retimers No SKP OS is defined for retimer to perform clock offset compensation The clock offset compensation scheme in the original Appendix E introduced significant retimer delay Pending_HP_Timer timeout Path to enable USB 3.1 retimer for SS operation Set max retimer delay 50ns/retimer Limit the maximum number of retimer in legacy operation three Relax Pending_HP_Timer timeout value 3µs 10µs Support typical four retimer link topology Allow 50m optical interconnect Redefine retimer architecture new appendix E Introduce USB 3.1 bitlevel retimer 16

17 Introduction to BitLevel Retimer BLR Jitter Suppression Concept BLR for USB 3.1 Recap Alternative USB 3.1 BLR Architecture Sequential BLR Training BLR Compliance Test 17

18 BLR Jitter Suppression: Concept RxCLK CLK H JTF _ RX ( s) s 2 2 Rx nrxs 2 s Rx nrx 2 nrx 2 nrx ( s) H Jitter suppression filter removes high frequency jitter from RxCDR Does not clean low frequency jitter A 2 nd order JSF may introduce low frequency wander that needs to be constrained Performance of the low BW Jitter suppression PLL is key to BLR H JTF JTF _ RX s H JSF s 18

19 BLR Feasibility for USB 3.1 Recap BLR properties clock derived from Rx data low latency with no need for EB No reference clock is needed low cost Initial delay due to Rx clock recovery additive JTF does not reset jitter completely pass low/reject high BLR concern for USB 3.1 Interop with legacy delay during training Jitter peaking Added transition latency from U1 Original conclusion (2013): feasible but with interop risk due to delay No specification The issue with excessive SRIS retimer delay in SS operation forces us to rethink BLR Rx FIFO Jitter Suppression Filter FIFO Jitter Suppression Filter Rx 19

20 Introduction to Hybrid BLR for USB 3.1 Rx FIFO LFPS/LBPM detection/condition TSEQ OS TS1A OS TS1B OS Jitter Suppression Filter RTSSM Reference clock RxData RxAFE D Symbol Recovery FIFO AFE Data FIFO Rx RxCR Jitter Suppression PLL BLR Jitter Suppression Filter Protocol decode RTSSM Optimize for delay and interop Hybrid BLR: SRIS during training, BLR during U0 Key to hybrid BLR architecture: transmit clock switching Hybrid BLR for USB 3.1 is NOT a low cost implementation PLL Reference clock SRIS 20

21 SRIS to BLR Switching Sequential Transmit Clock Transition Transmit clock switching must comply with df/dt (1250ppm/us or 10ms/s) to ensure the receiver CDR remained locked Want to ease the clock switching with Minimum frequency offset disable SSC: df(max) < 600ppm BLR to transmit TSEQ OS with SSC disabled Sequential transmit clock switching last retimer first Defined to be implementation friendly for BLR with maximum accommodation to various RxCDR implementations 21

22 Mechanism of Sequential Transmit Clock Transition Sequential transmit clock switching is a tradeoff between added logic complexity and ease of clock switching 22

23 SRIS to BLR Switching OS Switching Upon entry to Polling.Active/Recovery.Active Sequential clock RT1/RT4 RT1/RT4 RT2/RT3 RT2/RT3 start OS switching RT1/RT4 start OS switching All retimers complete OS switching A bitlevel retimer shall declare successful receiver training if eight consecutive and identical TS1A OS or TS1B OS or TS1 OS are received. A bitlevel retimer shall declare successful TS1B OS reception if one TS1B OS is received. New TS1A OS and TS1B OS handshakes defined to facilitate the sequential clock/os switching among BLRs 23

24 BLR Compliance Test Standalone Bitlevel Retimer Loopback Slave Rx Loopback data Loopback data Rx 0 Rx Loopback data CPx Rx Loopback master CPx 1 Intended for BLR transmit compliance test BLR to use loopback data pattern for its RxCDR to recover the clock BLR to transmit CPx CPx advancement based 4 consecutive SKP OS (Gen 1), or 4 SKP blocks (Gen 2) Need new test infrastructure Work for active cable and captive BLRs 24

25 Summary There is a need for USB 3.1 retimer to support large system and active cable The delay with SRIS retimers in SS operation has led to interop issues and the need to define the link delay budget The Pending_HP_Timer ECN is defined to achieve the maximum legacy interoperability and to support new connectivity models The hybrid BLR architecture is proposed to minimize the retimer propagation delay 25

26 Q&A 26