VPX Implementation Serves Shipboard Search and Track Needs

Transcription

1 VPX Implementation Serves Shipboard Search and Track Needs By: Thierry Wastiaux, Senior Vice President Interface Concept Defending against anti-ship missiles is a problem for which high-performance computing is instrumental. A VPX system architecture approach provides the throughput speeds and processing muscle to meet shipboard Search and Track requirements. Anti-ship missiles are a significant threat to surface ships. Navy leaders are known to be concerned with advanced radar-guided anti-ship missiles. New anti-ship missiles can fly at up to three times the speed of sound, giving targeted vessels little time to react. They may have the capability to maneuver on its terminal flight to its target, which could make defeating them difficult, if not impossible. To counter this threat, multilayer defenses have to be used. A combination of agile radar, infrared search and track systems and integrated missile firing control systems are usually used. Infrared sensor technology, high performance computing hardware and advanced detection and tracking algorithms have enabled a new generation of infrared warning systems for navy surface vessel allowing high precision engagement capacities. With that in mind, it's helpful to consider a new architecture for high performing Search and Track VPX systems as presented here. Employing Distributed Sensors Search and Track systems aim at automatically detect, track and classify air and surface targets. These targets may be stealthy or full maneuvering threats. In order to perform full panoramic and wide elevation coverage without any blind sector, a Search and Track system usually uses distributed advanced IR or RF Sensors. IR sensors may operate at different wavelength mainly Mid-Wavelength Infrared (MWIR) or intermediate infrared (3-5 µm). This is the atmospheric window in which the homing heads of passive IR heat seeking missiles are designed to work. The development of strategic technologies to design IR sensors at ever higher image definition needs a permanent sustained R&D effort. For efficient detection and tracking performance the sensor stabilized platforms must be installed in locations allowing wide angle vision from the vessel (Figure 1).

2 Figure 1- Sensor stabilized platforms must be installed in locations allowing wide angle vision. Fully passive infrared surveillance systems are able to automatically detect, track and classify air and surface targets (Maneuvering and stealthy threats). Distributed state of the art imaging sensors allow performing full panoramic and wide elevation coverage without any blind sector with a high surveillance rate. The short time of reaction implies heavy real time image processing allowing automatic fast detection and adaptive tracking. The image processing algorithms must contain clutter rejection features for very low false alarm rate. The data from the sensors may be fused with other sensor data for improved detection capabilities and flawless identification. These systems must be interfaced with the combat system of the vessel for firing control. VITA 65 FPGA Solution The following VPX architecture (Figure 2) provides an innovative approach to build high performance Search and Track systems. In compliance with the VITA 65 norm, this system architecture allows the cooperation of processor boards and FPGA modules connected to a high speed PCIe x 4 Data Plane, as well as the connection to many sensors for panoramic and elevation coverage. Each data inflow coming from each sensor is first processed in real time in the corresponding Virtex-7 running parallel powerful algorithms. The output of this first step is DMA transferred through PCIe x4 Gen2 links to each Intel Corei7 processor that performs a second processing step and in particular the tracking and the control. Figure 2 Back-end VPX Architecture Example. The distributed sensors collect low noise image data that must be transferred to the central image processing system with minimum latency. This transfer is achieved using optical or copper cables. However optical cables are lighter, free from EMI radiation and EMI resistant which enable them to avoid interferences inside space-restricted vessel situation awareness

3 and protection systems. Gigabit/10 Gigabit serial links connecting the sensors to the processing units bear various protocols as Serial FPDP, 10GbE, Aurora, Serial Rapid IO. Serial FPDP appears to be the interconnect of choice for streaming data capture systems as it is seen as an optimized protocol for maximum data rates and minimum overhead with different operation speed. In the proposed architecture, the sensors are connected to the system through communication FMCs bearing optical SFP transceivers (Figure 3). Figure 3 - FMCs with optical SFP transceivers. Last generation of FPGAs can perform massively parallel image processing algorithms. The last generation of extremely powerful FPGAs constitutes a technology disruption. They can perform massive parallel processing with very low consumption in comparison with other technologies and feature huge communication bandwidth-up to 2.76 Tb/s for the Xilinx Virtex- 7. The usual Search and Track step of signal processing consists in performing massive parallel algorithms on the sample data from the sensors among them partial differential equations, Cooley-Tuckey Fast Fourier Transform, multidimensional Discrete Cosine Transform and so on. Designers have considerably improved the performance of their Search and Track systems by using this last generation of FPGAs. Protocol Decoding with FPGAs An IP instantiated in the FPGA performs the protocol decoding. IC has especially developed a VITA compliant sfpdp IP that can run at high speed in a virtex-7 FPGA ensuring a low energy low latency interface. Using the high speed transceivers of the Virtex-7 FPGAs, the sfpdp link can run at a much higher data rate than the maximum rate of the norm. This IP supports unframed data as well as single frame data, fixed size repeating frame data and dynamic size repeating frame data. The configuration supported are Basic system, Flow control, Bi-directional data flow, Copy mode and Loop mode that allows the recording of the data coming from the sensors. One of the two SFP transceivers of the SFP FMC, receives the sensor data flow while the other transmits a copy of the same flow to a multi channels recorder under the Copy Mode. The IC-FEP-VPX6b (Figure 4) features two of the most powerful FPGAs of the Virtex-7 Xilinx family with up to 80 GTH 13.1 Gbit/s Transceivers and 3600 DSP48E1 slices. A PCIe

4 advanced switch allows combining the power of the two interconnected Virtex-7 Xilinx FPGAs, the Freescale QorIQ e5500 quad core T1042 and the fabric links of the VPX connectors. Each Virtex -7 FPGA has a very wide 64 bit connection to two DDR3 SDRAM memory banks supporting up to 1800 MT/s. as well as a connection to two DDRII+ SDRAM memory banks. Each Virtex-7 FPGA is interfaced with four SPI mirror flash memories (three for local bit streams storage and one for user parameters). They are directly interconnected together through 8 GTH lanes and 35 LVDS signals. Figure 4 Example of a 6U VPX FPGA carrier board. The IC-FEP-VPX6b is endowed with two FMC sites compliant with FPGA Mezzanine Card standard (VITA 57.1), allowing to implement FMC modules provided by IC, third-party or developed by the user. As on all of our FMC sites, an optional I/O connector can route sixteen additional differential pairs from the FMC module directly to the VPX backplane. The QorIQ processor T1042 provides the usual interfaces: Ethernet, Serial and USB ports with one eusb slot to plug an optional SSD module. Combining up to 32 Gbytes/s of backplane bandwidth and the processing power of two Intel Core i7 and a Kintex-7 Xilinx FPGA, the IC-INT-VPX6a fully uses the substantial bandwidth and system-enabling features of the 6U OpenVPX form factor. Delivered with IC UEFI Boot Loader for optimized power up sequences, the IC-INT-VPX6a provides versatile PCIe backplane configurations thanks to two PCIe switches, each attached to both processors. An ultra-low latency GbE switch attached to each CPU offers five GbE ports. IC provides its Fabric Management Software (Multiware) allowing message passing with synchronization, shared memory and bulk DMA powered transfers between PCIe domains (IDC). IC also provides its Reference Design to implement Signal Processing and High Speed communication functions into the Xilinx Kintex FPGA linked to an FMC slot. API for Software Development Multiware is a software package providing simplified API to users. A full set of software components provides a high level abstraction to provide the designer with services such as Virtual Ethernet over PCIe, shared memory, message synchronization with DMA powered transfers, between FPGA modules and CPU modules or between different 32-bit or 64-bit Intel or PowerPC CPU modules. The Multiware provides multiple kernel and user space services adapted to all users. Interface Concept supplies a full range of firmware and Example Designs for very high speed PCIe DMA data transfers, Signal Acquisition and signal processing. The PCIe DMA Engine

5 Reference Design allows high data rate transfers with a useful data transfer speed close to the theoretical limits of PCIe (1.5 GB/s on a PCIe x 4). The signal processing Example Designs allow to implement the firmware blocks allowing capture of multiple channels up to 3.0 Gb/s (on Virtex-7). Quick Response Defense The proposed architecture described above can be interfaced with the most demanding technologies of sensors allowing the design of advanced automatic fast Search and Track systems without any blind sector at a high surveillance rate and with low false alarm rate. These Search and Track systems represent the best means to protect vessels against the increasing threat of last ultrasonic anti-ship missiles. Interface Concept Quimper, France. +33 (0) Published in COTS Journal, April 2015