Standards for ESD Design Methodology

Transcription

1 Standards for ESD Design Methodology Mujahid Muhammad OPDKC ESD WG Chair & ESD Design Engineer Systems and Technology Group, IBM

2 Outline ESD Basics Overview ESD protection design ESD design/verification typical tools, proposed standardized methodology and newer tools Si2 OPDKC ESD WG ongoing activities Conclusion 2

3 What is Electrostatic Discharge (ESD)? Electrostatic Discharge (ESD) is a single-event, rapid transfer of electrostatic charge between two objects, usually resulting when two objects at different potentials come into direct contact with each other. Lightning Zap from a door 3

4 Introduction to ESD Models: HBM, MM, CDM ESD models: used to model Electrostatic Discharge events HBM: Human Body Model MM: Machine Model CDM: Charged Device Model 2A 3.8A 30ns 10A 1ns 800ns 2kV HBM Current waveform (~1.3A) 200V MM Current waveform (~3.8A) 500V CDM Current waveform (5-10A) 4

5 ESD Target Values ESD Model Human Body Model (HBM) Machine Model (MM) Charged Device Model (CDM) Historical Industry Standard Targets Alternate Target Set #1 Alternate Target Set #2 (ESD Industry Council recommended levels) 2000V 2000V 1000V (1000V ESD Industry Council) 200V 100V 50V (30V ESD Industry council) 500V 250V 250V (250V ESD Industry council) ESD targets in orders of difficulty MM 200V -> need to reduce to 100V or less 500V CDM -> need to reduce to 250V or less HBM 2000V not an issue. 5

6 Full chip ESD Protection Requirements Logic Vdd Optional ESD Device Analog Vcc Signal Pad #1 Logic Circuit ESD Power Clamp ESD Power Clamp Analog Circuit Signal Pad #2 Logic Gnd Desired Path Undesired Path Required ESD Device Analog Gnd Robust current handling, low resistance path for conduction of ESD current between any two pads Ensure that during an ESD event, the voltage drops across any internal device should not lead to the failure of the device 6

7 ESD Design Window ESD Design window shrinks with each successive technology advancement! 7

8 Typical ESD tools and limitations ESD Design Rule Checker (DRC) Limited ESD path-only checking - Impact on internal devices ignored Problems with this approach DRC cannot be used until layout level ESD FEOL and BEOL rules too complex for DRC decks ESD DRC rules limited by the number of testcases used Rigid, non-flexible ESD solutions Example of a complex case when using DRC to check for minimum BEOL wire width from pad to ESD device 8

9 ESD Design Methodology/Flow Cell Schematic Level Schematic Checking Tool Cell Layout Level Design Rule Checker Tool BEOL Current density/ resistance Tool Full Chip Floor planning Level Existence of sufficient powercells I / O ring placement checker Cross- boundary checks (flipchip) Full Chip Schematic Level Package Schematic Level Schematic Checking Tool CDM & system level checks Verification with package info incl.. Full Chip Layout Level Design Rule Checker Tool BEOL Current density Tool Power Bus resistance Extraction Tool Smart cap extraction to substrate 9

10 ESD Schematic Checking Back-to-Back diodes required between various domains to ensure a robust ESD path Netlist based checking able to check requirement at chip schematic level Check was problematic for Shapes-Based DRC checking 10

11 ESD Current Density Checking BEOL connection from pad to ESD devices need to be robust Static verification using known current density limits is used to analyze current flow from pad to ESD device 11

12 Si2 OPDK ESD WG Working Group formed in October 2011, moved under Si2 OPDKC in March 2012 Members include IBM, GlobalFoundries, ST, NXP, Intel and Samsung (others under discussion) Proposal includes a standardized ESD design methodology/tool flow for effective ESD protection design at all levels of a typical chip design Methodology indentifies the right ESD design/verification needs at each level of hierarchy in the design flow Methodology includes a basic set of requirements for each type of tool for utilization by the various EDA vendors Specific runset for each type of tool is envisioned at this point to be company specific Proposed design methodology creates a standardized high level flow for ESD design but allows for runset flexibility in each companies deck implementation of each tool. 12

13 ESD Methodology Standardization Extensive collaboration on the document, feedback incorporated from all members First version of the document is now ready to start the approval process 13

14 Conclusion Successful implementation of ESD protection is getting more difficult at each technology node Technology scaling implications on ESD protection drives the business justification to invest in ESD design methodologies and supporting tools Standardization of ESD design methodology needed to allow vendors to focus on the right design aids and verification tools for successful on-chip ESD protection Proposed ESD design methodology with supporting ESD verification tool requirements presented Sub-committee formed and work proceeding to come up with standardized final methodology to be released as an Si2 standard 14