The differential amplifier

Transcription

1 DiffAmp.doc 1 Te differential amplifier Te emitter coupled differential amplifier output is V o = A d V d + A c V C Were V d = V 1 V 2 and V C = (V 1 + V 2 ) / 2 In te ideal differential amplifier A c sould be zero and A d sould be as ig as possible, To find A d, we apply a purely differential signal V d to te amplifier, wit V C = 0 Ten Vo = A d V d, and we can find A d. To find A c, we apply purely common mode signal V 1 = V 2 = V C so tat Vo = A c V C. From tis we an find A c. In te general case, after finding A d and A c we can calculate Vo for given inputs. EMITTER COUPLED DIFFERENTIAL AMPLIFIER Gain A d : Vcc V1 Vo V2 Vo I E 2I E I E Ree Vd/2 I E + I E 2I E I E - I E -Vd/2 Vd/2 Vee Vee Te differential mode gain is obtained by applying a differential signal. In quiescent state, bot inputs are 0 and te emitters carry equal currents I E. Te current in R EE is 2I E. Wen differential signal is applied, current increase to I E + I E and current decreases to I E - I E. Te current in R EE remains 2I E. Tus voltage across R EE does not cange from quiescent value, even wen signal is present. Te voltage V E terefore remains constant, and is equivalent to a DC voltage source equal to 2I E R EE were connected in place of R EE. For signal analysis equivalent circuit, a dc source is equivalent to a sort circuit for te signal. Tus for te signal V d /2 te emitter of and are effectively grounded. Te circuit can terefore be bisected along te central axis of symmetry, witout canging any signal voltages or currents, and te alf circuit is a CE amplifier circuit. Te gain terefore is Vo /(V d /2) = fe R C / ie and te input resistance of eac alf circuit is ie. Tus Vo /V d =A d = fe R C /2 ie and differential input resistance is ie + ie = 2 ie across te two input terminals COMMON MODE GAIN: Initially consider Quiescent state. Te current in R EE is 2I E. Now give a pure common signal V C to bot inputs. Te current in bot transistors increases to I E + eac. Current in R EE is now 2(I E + ). Now replace R EE wit two resistors, eac of 2R EE value in parallel. Tis will not cange te circuit in any way. Te current in eac parallel resistor of 2R EE is 2(I E + )/2 = (I E + ). Tus ALL te current coming from eac emitter (I E + ) goes into te nearest 2R EE resistance. Tere is no current in te link joining te tops of te two 2R EE resistors., so we can safely open tat link witout affecting beaviour of te circuit. Te original circuit can now be cut along te axis of symmetry to form two identical alf circuits. Eac alf circuit is a CE wit R E were R E = 2R EE Hence gain Vo/V C =A c = fe R C /( ie + (I + fe ) 2R EE ) R C /2R EE for large fe and normal ie Te common mode input resistance is ie + (I + fe ) 2R EE

2 DiffAmp.doc 2 Vcc Vo Vc I E + I E + 2Ree 2Ree Vc 2Ree 2(I E + ) Vee CMRR improvement: CMRR can be improved by 1. Increasing R EE. Tis is possible only up to a certain limit decided by te power supply voltage and transistor bias current. Te Integrated circuit area problem and te teoretical limitations also exist as in CC case. 2. Replacing R EE by a current source. 3. Using active load (current sources) as R C for getting ig differential gain 4. Using cascaded differential amplifiers. However, direct coupling means tat V c of te first stage will be V B of te next stage. Tat in turn means tat V C of te next stage will be even iger, wit value approacing te V cc value. Te next stage transistor will ten get cut-off even wit a small input, giving a relatively smaller swing in output voltage. For tis reason it is not practical to cascade more tan two stages. Analysis and design of MC1530: Te conditions for te analysis and design are V cc R1 R2 R4 Q3 Q4 Q5 R3 Q7 R5 Q6 R9 Q8 R6 R7 R8 R10 1. All transistors ave fe = 100, and use V cc = V EE = 6V, 2. Transistors to Q4 ave I C = 0.5 ma, Q5 as I C =1.56 ma and Q6 as I C = 5 ma 3. All current sources are current mirrors wit equal current in eac branc. 4. First stage is designed for maximum differential gain witin a limited range of input voltage, and very ig CMRR by using a current source as R EE. Te range of input voltage is decided by ensuring tat Q7 does not saturate. 5. Te second stage is designed for maximum A d wit A c =1. Tis can be done as te first stage takes care of te CMRR. 6. Te voltage sifter and output stages are designed to get 0 output in quiescent (no signal) case. Calculation of current source resistances: R7: Te current source Q7 as to be active for te amplifier to work. Ten V CE7 V EE /2 = 3V Te inputs are at ground, Hence te top of R7 is at 0 V BE1 V CE 7 and bottom is at V EE - so voltage across R7 = ( ) ( 6) = 2.3V current troug R7 = I E1 + I E2 I C1 + I C2 = = 1 ma. Hence R7 = 2.3 K, but we coose te nearest standard value 2.2K V EE

3 DiffAmp.doc 3 Tus R7 = 2.2K R8: Wit R7 = 2.2K voltage V B7 = 6 + (2.2K 1ma) + V BE7 = = 3.1V Te drop in te two diodes is = 1.4V Ten top of R8 is at V B7 2V D = = 4.5 V Bottom is at 6 V. Ten V R8 = -4.5-(-6) = 1.5V, I R8 = 1 ma (current mirror action) Hence R8 = 1.5K R9: V B7 is 3.1V, ence across R9 voltage is 3.1V. current is 1 ma, ence R9 = 3.1K Calculation of differential stage R1 and R2 : Te Q7 transistor being a current source as to remain active for te amplifier to operate. Base voltage of Q7 is 3.1V, and under quiescent conditions, V C7 is = V BE1 = 0.7V. Wen a negative signal is given to base of, say V, ten te emitter voltage is V 0.7 And ence V C7 is V 0.7. If tis voltage is lower tan V B7 by 0.5 V ten Q7 will saturate. Tus Q7 saturates at V C7 = = 3.6V. Corresponding V B1 is = 2.9 V Tus input cannot be made more negative tan 2.9 V or Q7 will saturate. For safety we limit input to 2.7V Ten in positive alf cycle, max V B1 = 2.7V Now for maximum differential gain R C sould be maximum. As R C is made large, drop across it increases and V C1 becomes lower. If V C1 is less tan V B1 by 0.5 ten transistor will saturate. So minimum allowable V C1 = = 2.2 V. Below tis will saturate. Ten drop across R1 = 6 2.2V = 3.8V Current troug R1 = 0.5mA ence R1 = R2 = 3.8/0.5 = 7.6K Gain stage resistance: R3: Wit R1 = 7,6K, V C1 = V cc I C1 R1= = 2.2V Ten V B3 = V C1 and V E3 = = 1.5V Ten voltage across R3 = 1.5V and I R3 = I E3 + I E4 = = 1 ma So R3 = 1.5K R4: Wit R3 = 1.5K, to get max differential gain R C sould be largest. Increasing R C increase common mode gain as well, and tis as to be kept 1 Tus max value of R C we can use will make A c = 1 = R C /2R EE Ten R C = 2R EE = 2 1.5K = 3K Terefore R4 = 3K Voltage sifter and output stages: R5: Wit R4 = 3K, V C4 = = 4.5V. So V E5 = = 3.8V Now for 0 input output voltage i.e V E6 = 0. Ten V B6 = 0.7V Te voltage across R5 = = 3.1 V, and current =1,56 ma, giving R5 = 2K R10: Voltage across R10 is V EE + V d = = 5.3V, and current = 1.56mA Ten R10 = 5.3/1.56 = 3.1K R6: Vo = 0 in quiescent state, so across R6 we ave 6V. current is 5 ma, so R6 = 1.2K

4 DiffAmp.doc OPERATIONAL AMPLIFIER Te 741 Op Amplifier as four stages: 1. Input differential stage: and are CC input transistors wit ig R in. Tey are cascaded wit Q3 and Q4 wic are CB differential voltage amplifier, teir low i/p impedance matcing wit low output impedance of te previous CC stage. Q5, Q6 and Q7 are te current sources wic act as active load f or Q3 and Q4, Q8 acts as te common resistor (like R EE in te standard circuit). Te branc containing 2 and 1 decides bias current. If tis branc V as current I 4, ten te branc wit Q9, 0 as a muc smaller current I 3 because 0-1 are widlar source. I 0 in Q8 in te differential amplifier = I 3 as Q8 and Q9 are current mirror. Tese current mirrors are used to provide te bias currents. 2. Te gain stage as buffer CC 4 and amplifying CE wit R E 5. Te 5 load is active load given by current mirror transistor 3A, and te output is buffered by 8 wic passes it on to te output stage. 3. Te 3B and te block labelled V is te voltage sifter for ensuring te te two output transistors are ON under 0 input conditions, Ten V o = 0 as it is te electrical centre of te output branc. Block v is a V BE multiplier. 4. Output is complimentary pair of transistors. Under 0 input bot are ON wen +ve i/p is given at 8 base, 7 conducts and 8 cuts off, delivering current into load. During negative input 8 conducts and 7 cuts-off tus current is taken from load. 5. Under 0 input condition I 2 = I 1 and I = I 1 (current mirror) so I d =I 2 I = 0, ence no input to te next stage, and output stays 0V 6. Wen positive i/p is given to, current I 1 increases, and I 2 decreases. Hence I 2 I = I d is drawn from te next stage. 7. Wen negative i/p is given to, current I 1 decreases, and I 2 increases. Hence I 2 I = I d is delivered to te next stage. 8. Te amplifier first stage is tus a trans-conductance amplifier. Analysis of differential gain of 741 Te currents in te various current sources are sown in te figure, wic gives te important subcircuits of te 741. All Transistors ave fe = 200 and Q3 and Q4 ave fe = 4. Te input stage transistors and Q4 wit teir load Ro6 and R i 14 are sown in te second figure. Output resistance of Q6 and input resistance of 4. Appear as parallel load to Q4 collector. R id calculation: 2M Ro5 15 ua 15 ua Q3 From Q8 Q4 6uA 12 ua 12 ua Ro13A 200K 15 ua 250 ua Q!4 5 2M Ro6 50K Ro13B 200K ua ua

5 DiffAmp.doc 5 Here R id = 2R i2 = ie2 +( fe2 )R i4 and R i4 = ie4 /( fe4 +1 ) fe2vt ence Rid = + IC2 ere I c2 = 15 ua and I C4 = 12 ua giving R id = 1.38 MΩ fe2 fe4 fe4 T I V C4 1 st stage gain: R L4 = Ro 6 R i14 And output of first stage = V b14 = i c4 R L4 Now i c4 = fe4 / ( fe4 )i e4 Wit i e4 = ( fe2 )i b2 = ( fe2 )v id /2r i2 v 14 fe4 b fe2 Ten, = RL4 vid fe4 rid Now ie14 = fe14 V T / i c14 = 350K. Similarly fe15 = 21K Ten R i15 = ie15 +( fe15 )R 7 = 41K Ten R i14 = ie14 +( fe14 )(R 6 Ri 15 ) Giving R i14 = 4.88 M Using values of R i14 and R o6, R L4 = 1.42M, giving First stage gain = V b14 /V id = 166 Q4 Ro6 Ri14 Second stage gain If we assume tat R6 was not present ten i b15 = ( fe +1)i b14 Ten i C15 = fe15 fe14 I b14 Wit R 6, tere is a loss of current and te new gain is β = fe15 fe14 (R 6 /(R 6 + R i15 )) Neglecting drop in 8 v b16 / v b14 = - β (R o13 /R i14 ) fe14 and fe15 can be calculated and are 350K and 21K. ten R i15 = ie15 + ( fe15 )R7 = 41K, and R i14 = ie14 + ( fe14 )(R 6 Ri 15 ) = 4.88M β = (50/(50+41)) = Second stage gain = v b16 / v b14 = (0.2/4.88) = R6 5 Ro13A R7 Vb16 tus A d = = OUTPUT RESITANCE: For small signals 6 and 7 are in parallel as teir bases are connected. Ten R 0 = [(R o18 R o13a ) + ( ie17 + ie16 )] / ( fe17 +1) And R o18 = (R o13b + ie18 ) / ( fe18 + 1) Now ie17 = 26K (By calculation) ie18 = 26K and ie18 = 52K giving R o18 = 1.25K Ten R o18 R o13a and R o = (26 26) / 201 =71 Om Tus eac transistor as o/p resistance 142 Oms. Now eac transistor is in series wit 27 Om, so final output resistance is (142+27) (142+27) = 83 Oms

6 DiffAmp.doc 6 SPECIFICATION PARAMETERS OF OP-AMPS Input Bias Current (I B ) : average current entering i/p terminals wen amplifier is balanced i.e. v o = 0 Typical 100nA Input Offset Current (I io ): difference between currents entering input terminals wen v o =0. Typical:10 na V B2 I B2 V io V o =0 V B1 I B1 Output offset voltage Input Offset Current Drift: ratio of cange in I io upon cange in absolute temperature. Typical 0.1nA/degree C Input Offset Voltage (V io ): Voltage at te input terminals to balance te amplifier. Typical 1mV Input Offset Voltage Drift: Ratio of cange in input offset voltage to te cange in temperature. Typical 1uV/degree C Output Offset Voltage: Output voltage wen inputs are grounded. Power Supply Rejection Ratio: Ratio of cange in input offset voltage to te cange in any one of te power supply voltages. Typical 20 uv/v Slew Rate: Time rate of cange of te closed loop amplifier output voltage under large signal conditions. Typical 1V/uS Open Loop Gain: typical CMRR: Typical 100dB Measurement: A v Measure output signal voltage witout R L, ensuring output voltage is not more tan 30% of rating. Find A v Output Resistance: Attac R L and measure gain. Ten A V = R L /(R L + R o ) A v and so R o = ((A v /A V )-1)R L Vs V i V o R id : Insert two equal resistors in series wit te two input terminals measure output. Ten new output V o = [R id / (R id + 2R) ] V o were Vo is te output witout te two resistances. Ten R id = 2R [V o /(V o V o )] 50K Pot +v -v 200K 100 Om V io : Connect circuit as sown. Ten v io exists between input terminals From te circuit V o = [(R+ R )/R] V io Take R = 100 Om and R = 100K for easy measurement. R R' I io and I B : Use large resistance > 10M as sown, wit noise bypassing capacitors. (0.01uF)

7 DiffAmp.doc 7 Connect A and B sort-circuiting te lower resistance. ten measured output is V o = I B2 R., from wic I B2 is obtained If we sort-circuit C and D and measure output, V o = -I B1 R. wic gives I B1.Tus I B1 and I B2 can be found. From tis I B = (I B1 + I B2 )/2 and I io = I B1 I B2 Te capacitors are used to bypass effects of noise voltage wic is generated by random flows of electrons in te resistance. At te ig resistance used, tis voltage is significant. A C D R>10M R>10M CMRR: Using circuit sown, wit R =R1 = 100 Oms and R = R1 = 100K we can calculate CMRR as follows: B Voltage across R = V i [V s R 1 /(R 1 +R 1 )] Across R = V o -Vi -[V s R 1 /(R 1 +R 1 )] Assuming equal currents in R and R ( neglecting input bias current) and noting tat R = R 1 and R = R 1 and solving, V i = (R/(R+R ))V o V c = V s [R 1 /(R 1 + R 1 )] = V s [R /(R + R )] Also V o = A d V d + A c V c = [(A d RV o )/(R+R )] + [(A c R V s )/(R+R )] Tus V o [1- (A d R/(R+R ))] = (A c R V s )/(R+R ) By coosing R and R suc tat A d R/(R+R ) >>1 -V o A d R/(R+R ) = A c R V s /(R+R ) and so A d /A c = (R /R) (V s /V o ) wic is te CMRR. Vs R R1 Vc Vi R1' R'