Ultralow Offset Voltage Operational Amplifier OP07

Transcription

1 Data Sheet FEATURES Low VOS: 5 μv maximum Low VOS drift:. μv/ C maximum Ultrastable vs. time:.5 μv per month maximum Low noise:. μv p-p maximum Wide input voltage range: ± V typical Wide supply voltage range: ± V to ±8 V 5 C temperature-tested dice APPLICATIONS Wireless base station control circuits Optical network control circuits Instrumentation Sensors and controls Thermocouples Resistor thermal detectors (RTDs) Strain bridges Shunt current measurements Precision filters GENERAL DESCRIPTION The has very low input offset voltage (5 μv maximum for E) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The also features low input bias current (± na for the E) and high open-loop gain ( V/mV for the E). The low offset and high open-loop gain make the particularly useful for high gain instrumentation applications. Ultralow Offset Voltage Operational Amplifier PIN CONFIGURATION V OS TRIM 8 V OS TRIM IN V IN OUT V 5 NC NC = NO CONNECT Figure. The wide input voltage range of ± V minimum combined with a high CMRR of db (E) and high input impedance provide high accuracy in the noninverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the, even at high gain, combined with the freedom from external nulling have made the an industry standard for instrumentation applications. The is available in two standard performance grades. The E is specified for operation over the C to C range, and the C is specified over the C to 85 C temperature range. The is available in epoxy 8-lead PDIP and 8-lead narrow SOIC packages. For CERDIP and TO-99 packages and standard microcircuit drawing (SMD) versions, see the OP. - V RA RA (OPTIONAL NULL) 8 RB RB C R Q9 NONINVERTING INPUT INVERTING INPUT R R Q5 Q Q Q Q Q Q Q Q Q8 Q Q Q Q Q5 Q9 C R5 Q Q C Q Q Q Q Q5 Q8 R9 OUT R Q Q V RA AND RB ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE. R R8 - Figure. Simplified Schematic Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Configuration... Revision History... Specifications... E Electrical Characteristics... C Electrical Characteristics... Data Sheet Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Typical Performance Characteristics... Typical Applications... Applications Information... Outline Dimensions... Ordering Guide... REVISION HISTORY / Rev. F. to Rev G Changes to Features Section... 8/ Rev. E. to Rev F Changes to Ordering Guide... /9 Rev. D. to Rev E Changes to Figure 9 Caption... Changes to Ordering Guide... / Rev. C. to Rev D Changes to Features... Changes to General Description... Changes to Specifications Section... Changes to Table... Changes to Figure and Figure 8... Changes to Figure and Figure... 8 Changes to Figure... 9 Changes to Figure to Figure 5... Changes to Figure and Figure... Replaced Figure 8... Changes to Applications Information Section... Updated Outline Dimensions... Changes to Ordering Guide... 8/ Rev. B to Rev. C Changes to E Electrical Specifications... Changes to C Electrical Specifications... Edits to Ordering Guide... 5 Edits to Figure... 9 Updated Outline Dimensions... / Rev. A to Rev. B Updated Package Titles... Universal Updated Outline Dimensions... / Rev. to Rev. A Edits to Features... Edits to Ordering Guide... Edits to Pin Connection Drawings... Edits to Absolute Maximum Ratings... Deleted Electrical Characteristics... Deleted D Column from Electrical Characteristics... 5 Edits to TPCs... 9 Edits to High-Speed, Low VOS Composite Amplifier... 9 Rev. G Page of

3 Data Sheet SPECIFICATIONS E ELECTRICAL CHARACTERISTICS VS = ±5 V, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS TA = 5 C Input Offset Voltage VOS 5 μv Long-Term VOS Stability VOS/Time..5 μv/month Input Offset Current IOS.5.8 na Input Bias Current IB ±. ±. na Input Noise Voltage en p-p. Hz to Hz.5. μv p-p Input Noise Voltage Density en fo = Hz. 8. nv/ Hz fo = Hz.. nv/ Hz fo = khz 9.. nv/ Hz Input Noise Current In p-p pa p-p Input Noise Current Density In fo = Hz..8 pa/ Hz fo = Hz.. pa/ Hz fo = khz.. pa/ Hz Input Resistance, Differential Mode RIN 5 5 MΩ Input Resistance, Common Mode RINCM GΩ Input Voltage Range IVR ± ± V Common-Mode Rejection Ratio CMRR VCM = ± V db Power Supply Rejection Ratio PSRR VS = ± V to ±8 V 5 μv/v Large Signal Voltage Gain AVO RL kω, VO = ± V 5 V/mV RL 5 Ω, VO = ±.5 V, VS = ± V 5 V/mV C TA C Input Offset Voltage VOS 5 μv Voltage Drift Without External Trim TCVOS.. μv/ C Voltage Drift with External Trim TCVOSN RP = kω.. μv/ C Input Offset Current IOS.9 5. na Input Offset Current Drift TCIOS 8 5 pa/ C Input Bias Current IB ±.5 ±5.5 na Input Bias Current Drift TCIB 5 pa/ C Input Voltage Range IVR ± ±.5 V Common-Mode Rejection Ratio CMRR VCM = ± V db Power Supply Rejection Ratio PSRR VS = ± V to ±8 V μv/v Large Signal Voltage Gain AVO RL kω, VO = ± V 8 5 V/mV OUTPUT CHARACTERISTICS TA = 5 C Output Voltage Swing VO RL kω ±.5 ±. V RL kω ±. ±.8 V RL kω ±.5 ±. V C TA C Output Voltage Swing VO RL kω ± ±. V Rev. G Page of

4 Data Sheet Parameter Symbol Conditions Min Typ Max Unit DYNAMIC PERFORMANCE TA = 5 C Slew Rate SR RL kω.. V/μs Closed-Loop Bandwidth BW AVOL = 5.. MHz Open-Loop Output Resistance RO VO =, IO = Ω Power Consumption Pd VS = ±5 V, No load 5 mw VS = ± V, No load mw Offset Adjustment Range RP = kω ± mv Input offset voltage measurements are performed by automated test equipment approximately.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first days of operation. Excluding the initial hour of operation, changes in VOS during the first operating days are typically.5 μv. Refer to the Typical Performance Characteristics section. Parameter is sample tested. Sample tested. Guaranteed by design. 5 Guaranteed but not tested. C ELECTRICAL CHARACTERISTICS VS = ±5 V, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS TA = 5 C Input Offset Voltage VOS 5 μv Long-Term VOS Stability VOS/Time.. μv/month Input Offset Current IOS.8. na Input Bias Current IB ±.8 ±. na Input Noise Voltage en p-p. Hz to Hz.8.5 μv p-p Input Noise Voltage Density en fo = Hz.5. nv/ Hz fo = Hz..5 nv/ Hz fo = khz nv/ Hz Input Noise Current In p-p 5 5 pa p-p Input Noise Current Density In fo = Hz.5.9 pa/ Hz fo = Hz.5. pa/ Hz fo = khz..8 pa/ Hz Input Resistance, Differential Mode RIN 8 MΩ Input Resistance, Common Mode RINCM GΩ Input Voltage Range IVR ± ± V Common-Mode Rejection Ratio CMRR VCM = ± V db Power Supply Rejection Ratio PSRR VS = ± V to ±8 V μv/v Large Signal Voltage Gain AVO RL kω, VO = ± V V/mV RL 5 Ω, VO = ±.5 V, VS = ± V V/mV C TA 85 C Input Offset Voltage VOS 85 5 μv Voltage Drift Without External Trim TCVOS.5.8 μv/ C Voltage Drift with External Trim TCVOSN RP = kω.. μv/ C Input Offset Current IOS. 8. na Input Offset Current Drift TCIOS 5 pa/ C Input Bias Current IB ±. ±9. na Input Bias Current Drift TCIB 8 5 pa/ C Input Voltage Range IVR ± ±.5 V Common-Mode Rejection Ratio CMRR VCM = ± V 9 db Power Supply Rejection Ratio PSRR VS = ± V to ±8 V 5 μv/v Large Signal Voltage Gain AVO RL kω, VO = ± V V/mV Rev. G Page of

5 Data Sheet Parameter Symbol Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS TA = 5 C Output Voltage Swing VO RL kω ±. ±. V RL kω ±.5 ±.8 V RL kω ±. V C TA 85 C Output Voltage Swing VO RL kω ± ±. V DYNAMIC PERFORMANCE TA = 5 C Slew Rate SR RL kω.. V/μs Closed-Loop Bandwidth BW AVOL = 5.. MHz Open-Loop Output Resistance RO VO =, IO = Ω Power Consumption Pd VS = ±5 V, No load 8 5 mw VS = ± V, No load 8 mw Offset Adjustment Range RP = kω ± mv Input offset voltage measurements are performed by automated test equipment approximately.5 seconds after application of power. Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first days of operation. Excluding the initial hour of operation, changes in VOS during the first operating days are typically.5 μv. Refer to the Typical Performance Characteristics section. Parameter is sample tested. Sample tested. Guaranteed by design. 5 Guaranteed but not tested. Rev. G Page 5 of

6 ABSOLUTE MAXIMUM RATINGS Table. Parameter Ratings Supply Voltage (VS) ± V Input Voltage ± V Differential Input Voltage ± V Output Short-Circuit Duration Indefinite Storage Temperature Range S and P Packages 5 C to 5 C Operating Temperature Range E C to C C C to 85 C Junction Temperature 5 C Lead Temperature, Soldering ( sec) C For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. Data Sheet Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table. Thermal Resistance Package Type θja θjc Unit 8-Lead PDIP (P-Suffix) C/W 8-Lead SOIC_N (S-Suffix) 58 C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. G Page of

7 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS OPEN-LOOP GAIN (V/mV) TEMPERATURE ( C) Figure. Open-Loop Gain vs. Temperature - MAXIMUM ERROR REFERRED TO INPUT (mv) T A = 5 C C E k k k MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) Figure. Maximum Error vs. Source Resistance - ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µv) T A = 5 C, T A = C THERMAL SHOCK RESPONSE BAND DEVICE IMMERSED IN C OIL BATH 8 TIME (Seconds) - MAXIMUM ERROR REFERRED TO INPUT (mv) C T A C C E k k k MATCHED OR UNMATCHED SOURCE RESISTANCE (Ω) - Figure. Offset Voltage Change due to Thermal Shock Figure. Maximum Error vs. Source Resistance ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µv) T A = 5 C C E NONINVERTING INPUT BIAS CURRENT (na) AT V DIFF.V, I B na (C) T A = 5 C 5 TIME AFTER SUPPLY TURN-ON (Minutes) Figure 5. Warm-Up Drift -5 DIFFERENTIAL INPUT VALUE (V) Figure 8. Input Bias Current vs. Differential Input Voltage -8 Rev. G Page of

8 Data Sheet INPUT BIAS CURRENT (na) C E INPUT NOISE VOLTAGE (nv/ Hz) R S = R S = kω THERMAL NOISE SOURCE RESISTORS INCLUDED EXCLUDED R S = TEMPERATURE ( C) Figure 9. Input Bias Current vs. Temperature -9 T A = 5 C FREQUENCY (Hz) Figure. Total Input Noise Voltage vs. Frequency -.5 T A = 5 C INPUT OFFSET CURRENT (na) C RMS NOISE (µv) E TEMPERATURE ( C) Figure. Input Offset Current vs. Temperature REFERRED TO INPUT 5mV/CM AT OUTPUT -. k k k BANDWIDTH (Hz) Figure. Input Wideband Noise vs. Bandwidth,. Hz to Frequency Indicated - VOLTAGE (nv/div) CMRR (db) 9 8 C TIME (s/div) Figure. Low Frequency Noise - k k k FREQUENCY (Hz) Figure. CMRR vs. Frequency - Rev. G Page 8 of

9 Data Sheet C T A = 5 C 8 T A = 5 C PSRR (db) 9 8 CLOSED-LOOP GAIN (db) 5. k k FREQUENCY (Hz) Figure 5. PSRR vs. Frequency -5 k k k M M FREQUENCY (Hz) Figure 8. Closed-Loop Frequency Response for Various Gain Configurations -8 OPEN-LOOP GAIN (V/mV) 8 T A = 5 C PEAK-TO-PEAK AMPLITUDE (V) 8 8 T A = 5 C ±5 ± ±5 ± POWER SUPPLY VOLTAGE (V) Figure. Open-Loop Gain vs. Power Supply Voltage - k k k M FREQUENCY (Hz) Figure 9. Maximum Output Swing vs. Frequency -9 T A = 5 C V IN = ±mv T A = 5 C OPEN-LOOP GAIN (db) 8 MAXIMUM OUTPUT (V) 5 5 POSITIVE SWING NEGATIVE SWING. k k k M M FREQUENCY (Hz) Figure. Open-Loop Frequency Response - k k LOAD RESISTANCE TO GROUND (Ω) Figure. Maximum Output Voltage vs. Load Resistance - Rev. G Page 9 of

10 Data Sheet POWER CONSUMPTION (mw) T A = 5 C 5 TOTAL SUPPLY VOLTAGE, V TO V (V) Figure. Power Consumption vs. Power Supply - ABSOLUTE VALUE OF OFFSET VOLTAGE (µv) V OS TRIMMED TO < 5µV AT 5 C NULLING POT = kω C E TEMPERATURE ( C) C E Figure. Trimmed Offset Voltage vs. Temperature - OUTPUT SHORT-CIRCUIT CURRENT (ma) 5 5 T A = 5 C V IN (PIN ) = mv, V O = 5V V IN (PIN ) = mv, V O = 5V TOTAL DRIFT WITH TIME (µv) 8 8.µV/MONTH TREND LINE.µV/MONTH TREND LINE.µV/MONTH TREND LINE.µV/MONTH TREND LINE.µV/MONTH TREND LINE.µV/MONTH TREND LINE 5 TIME FROM OUTPUT BEING SHORTED (Minutes) Figure. Output Short-Circuit Current vs. Time TIME (Months) Figure 5. Offset Voltage Drift vs. Time -5 ABSOLUTE VALUE OF OFFSET VOLTAGE (µv) R S = Ω TEMPERATURE ( C) C E Figure. Untrimmed Offset Voltage vs. Temperature - Rev. G Page of

11 Data Sheet TYPICAL APPLICATIONS RF R E IN SUM MODE BIAS V R R R5 V C A V R kω R5 R kω AD5 OR AD85 V E O = E RF IN I B RF R Figure. Typical Offset Voltage Test Circuit E O - E IN ±V R V V FD D FD D R V V Figure 9. Absolute Value Circuit R R = R R E O V TO V -9 RF R E IN SUM MODE BIAS V E E E R R R R5.5kΩ R 5V C 5V E O - V C A R kω R R kω V E O = E RF IN I B RF R NOTES. PINOUT SHOWN FOR P PACKAGE C A V E O - Figure. Typical Low Frequency Noise Circuit Figure. High Speed, Low VOS Composite Amplifier R INPUT 8 V kω V OUT Figure 8. Optional Offset Nulling Circuit -8 E E E R R R R5.5kΩ NOTES. PINOUT SHOWN FOR P PACKAGE 5V 5V Figure. Adjustment-Free Precision Summing Amplifier E O - Rev. G Page of

12 Data Sheet SENDING JUNCTION REFERENCE JUNCTION R R R NOTES. PINOUT SHOWN FOR P PACKAGE R V V R R = R R Figure. High Stability Thermocouple Amplifier E O - APPLICATIONS INFORMATION The provides stable operation with load capacitance of up to 5 pf and ± V swings; larger capacitances should be decoupled with a 5 Ω decoupling resistor. Stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals can degrade drift performance. Therefore, best operation is obtained when both input contacts are maintained at the same temperature, preferably close to the package temperature. R R R5 E IN ±V R V A V FD D FD D R V A V A V E O V TO V NOTES. PINOUT SHOWN FOR P PACKAGE Figure. Precision Absolute-Value Circuit - Rev. G Page of

13 Data Sheet OUTLINE DIMENSIONS 5. (.98).8 (.89). (.5).8 (.9) 8 5. (.) 5.8 (.8).5 (.98). (.) COPLANARITY. SEATING PLANE. (.5) BSC.5 (.88).5 (.5).5 (.). (.) 8.5 (.98). (.).5 (.9).5 (.99). (.5). (.5) 5 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) -A. (.).5 (9.).55 (9.). (5.) MAX.5 (.8). (.).5 (.9). (.5).8 (.). (.) 8. (.5) BSC 5.8 (.).5 (.5). (.).5 (.8) MIN SEATING PLANE.5 (.) MIN. (.5) MAX.5 (.8) GAUGE PLANE.5 (8.). (.8). (.). (.9) MAX.95 (.95). (.).5 (.9). (.). (.5).8 (.). (.8). (.5).5 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 5. 8-Lead Plastic Dual-in-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) -A Rev. G Page of

14 Data Sheet ORDERING GUIDE Model Temperature Range Package Description Package Option EPZ C to C 8-Lead PDIP N-8 (P-Suffix) CPZ C to 85 C 8-Lead PDIP N-8 (P-Suffix) CSZ C to 85 C 8-Lead SOIC_N R-8 (S-Suffix) CSZ-REEL C to 85 C 8-Lead SOIC_N R-8 (S-Suffix) CSZ-REEL C to 85 C 8-Lead SOIC_N R-8 (S-Suffix) Z = RoHS Compliant Part. Rev. G Page of

15 Data Sheet NOTES Rev. G Page 5 of

16 Data Sheet NOTES - Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--/(G) Rev. G Page of