MCP4017/18/19. 7-Bit Single I 2 C Digital POT with Volatile Memory in SC70. Package Types. Features. Device Features. Rheostat

Transcription

1 7-Bit Single I 2 C Digital POT with Volatile Memory in SC7 Features Potentiometer or Rheostat configuration options 7-bit: Resistor Network Resolution Resistors (128 Steps) Zero Scale to Full Scale Wiper operation R AB Resistances: 5 kω, 1 kω, 5 kω, or 1 kω Low Wiper Resistance: 1Ω (typical) Low Tempco: - Absolute (Rheostat): 5 ppm typical ( C to 7 C) - Ratiometric (Potentiometer): 1 ppm typical Simple I 2 C Protocol with read & write commands Brown-out reset protection (1.5V typical) Power-on Default Wiper Setting (Mid-scale) Low-Power Operation: µa Static Current (typical) Wide Operating Voltage Range: - 2.7V to 5.5V - Device Characteristics Specified - 1.8V to 5.5V - Device Operation Package Types Potentiometer MCP418 SC7-6 V DD V SS SCL B A W 6 A 5 W 4 SDA V DD V SS SCL V DD V SS SCL Rheostat MCP419 SC7-5 Wide Bandwidth (-3 db) Operation: - 2 MHz (typical) for 5. kω device Extended temperature range (-4 C to +125 C) Very small package (SC7) Lead free (Pb-free) package MCP417 SC7-6 B A W 6 W W 5 B B 4 SDA 5 W A 4 SDA Device Features Device Control Interface # of Steps Wiper Configuration Memory Type Resistance (typical) Options (kω) Wiper (Ω) VDD Operating Range (1) Package MCP417 I 2 C 128 Rheostat RAM 5., 1., 5., V to 5.5V SC7-6 MCP418 I 2 C 128 Potentiometer RAM 5., 1., 5., V to 5.5V SC7-6 MCP419 I 2 C 128 Rheostat RAM 5., 1., 5., V to 5.5V SC7-5 Note 1: Analog characteristics only tested from 2.7V to 5.5V 29 Microchip Technology Inc. DS22147A-page 1

2 Device Block Diagram V DD V SS SCL SDA Power-up/ Brown-out Control I 2 C Serial Interface Module, Control Logic, & Memory Resistor Network (Pot ) Note 1 A (2) W (1, 2) B Note 1: Some configurations will have this signal internally connected to ground. 2: In some configurations, this signal may not be connected externally (internally floating or grounded). Comparison of Similar Microchip Devices (1) Control Interface # of Steps Memory Type Resistance (typical) V DD Operating Range (2) HV Interface WiperLock Technology Wiper Device Configuration Options (kω) Package MCP417 I 2 C 128 Rheostat RAM 5., 1., 5., V to 5.5V No No SC7-6 MCP412 U/D 64 Rheostat RAM 2.1, 5., 1., V to 5.5V Yes No SOT-23-6 MCP422 U/D 64 Rheostat EE 2.1, 5., 1., V to 5.5V Yes Yes SOT-23-6 MCP4132 SPI 129 Rheostat RAM 5., 1., 5., V to 5.5V Yes No PDIP-8, MCP4142 SPI 129 Rheostat EE 5., 1., 5., V to 5.5V Yes Yes SOIC-8, MSOP-8, MCP4152 SPI 257 Rheostat RAM 5., 1., 5., V to 5.5V Yes No DFN-8 MCP4162 SPI 257 Rheostat EE 5., 1., 5., V to 5.5V Yes Yes MCP4532 I 2 C 129 Rheostat RAM 5., 1., 5., V to 5.5V Yes No MSOP-8, MCP4542 I 2 C 129 Rheostat EE 5., 1., 5., V to 5.5V Yes Yes DFN-8 MCP4552 I 2 C 257 Rheostat RAM 5., 1., 5., V to 5.5V Yes No MCP4562 I 2 C 257 Rheostat EE 5., 1., 5., V to 5.5V Yes Yes MCP418 I 2 C 128 Potentiometer RAM 5., 1., 5., V to 5.5V No No SC7-6 MCP413 U/D 64 Potentiometer RAM 2.1, 5., 1., V to 5.5V Yes No SOT-23-6 MCP423 U/D 64 Potentiometer EE 2.1, 5., 1., V to 5.5V Yes Yes SOT-23-6 MCP419 I 2 C 128 Rheostat RAM 5., 1., 5., V to 5.5V No No SC7-5 MCP414 U/D 64 Rheostat RAM 2.1, 5., 1., V to 5.5V Yes No SOT-23-5 MCP424 U/D 64 Rheostat EE 2.1, 5., 1., V to 5.5V Yes Yes SOT-23-5 Note 1: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table are the devices described in this data sheet, while the shaded devices offer a comparable resistor network configuration. 2: Analog characteristics only tested from 2.7V to 5.5V DS22147A-page 2 29 Microchip Technology Inc.

3 1. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Voltage on V DD with respect to V SS V to +7.V Voltage on SCL, and SDA with respect to V SS V to 12.5V Voltage on all other pins (A, W, and B) with respect to V SS V to V DD +.3V Input clamp current, I IK (V I <, V I > V DD, V I > V PP ON HV pins)... ±2 ma Output clamp current, I OK (V O < or V O > V DD )... ±2 ma Maximum output current sunk by any Output pin ma Maximum output current sourced by any Output pin ma Maximum current out of V SS pin... 1 ma Maximum current into V DD pin... 1 ma Maximum current into A, W and B pins... ±2.5 ma Package power dissipation (T A = +5 C, T J = +15 C) SC mw SC TBD Storage temperature C to +15 C Ambient temperature with power applied C to +125 C ESD protection on all pins... 4 kv (HBM)... 4V (MM) Maximum Junction Temperature (T J ) C Notice: Stresses above those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 29 Microchip Technology Inc. DS22147A-page 3

4 AC/DC CHARACTERISTICS DC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C T A +125 C (extended) All parameters apply across the specified operating ranges unless noted. V DD = +2.7V to 5.5V, 5 kω, 1 kω, 5 kω, 1 kω devices. Typical specifications represent values for V DD = 5.5V, T A = +25 C. Parameters Sym Min Typ Max Units Conditions Supply Voltage V DD V Analog Characteristics specified V Digital Characteristics specified V DD Start Voltage to ensure Wiper Reset V BOR 1.65 V RAM retention voltage (V RAM ) < V BOR V DD Rise Rate to ensure Power-on Reset Delay after device exits the reset state (V DD > V BOR ) Supply Current (Note 8) V DDRR (Note 7) V/ms T BORD 1 2 µs I DD 45 8 µa Serial Interface Active, Write all s to Volatile Wiper V DD = 5.5V, F SCL = 4 khz µa Serial Interface Inactive, (Stop condition, SCL = SDA = V IH ), Wiper =, V DD = 5.5V Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V W with V A = V DD and V B = V SS. 3: MCP418 device only, includes V WZSE and V WFSE. 4: Resistor terminals A, W and B s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R W ), which changes significantly over voltage and temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22147A-page 4 29 Microchip Technology Inc.

5 AC/DC CHARACTERISTICS (CONTINUED) DC Characteristics Resistance R AB kω -52 devices (Note 1) (± 2%) kω -13 devices (Note 1) kω -53 devices (Note 1) kω -14 devices (Note 1) Resolution N 128 Taps No Missing Codes Step Resistance R S R AB / Ω Note 5 (127) Wiper Resistance R W 1 17 Ω V DD = 5.5 V, I W = 2. ma, code = h Ω V DD = 2.7 V, I W = 2. ma, code = h Nominal ΔR AB /ΔT 5 ppm/ C T A = -2 C to +7 C Resistance 1 ppm/ C T A = -4 C to +85 C Tempco 15 ppm/ C T A = -4 C to +125 C Ratiometeric ΔV WB /ΔT 15 ppm/ C Code = Midscale (3Fh) Tempco Resistor Terminal Input Voltage Range (Terminals A, B and W) V A, V W, V B Vss V DD V Note 4, Note 5 Maximum current through Terminal (A, W or B) Note 5 Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C T A +125 C (extended) All parameters apply across the specified operating ranges unless noted. V DD = +2.7V to 5.5V, 5 kω, 1 kω, 5 kω, 1 kω devices. Typical specifications represent values for V DD = 5.5V, T A = +25 C. Parameters Sym Min Typ Max Units Conditions I T 2.5 ma Terminal A I AW, W = Full Scale (FS) 2.5 ma Terminal B I BW, W = Zero Scale (ZS) 2.5 ma Terminal W I AW or I BW, W = FS or ZS 1.38 ma I AB, V B = V, V A = 5.5V, R AB(MIN) = ma I Terminal A AB, V B = V, V A = 5.5V, R AB(MIN) = 8 and.138 ma I Terminal B AB, V B = V, V A = 5.5V, R AB(MIN) = 4.69 ma I AB, V B = V, V A = 5.5V, R AB(MIN) = 8 Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V W with V A = V DD and V B = V SS. 3: MCP418 device only, includes V WZSE and V WFSE. 4: Resistor terminals A, W and B s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R W ), which changes significantly over voltage and temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network 29 Microchip Technology Inc. DS22147A-page 5

6 AC/DC CHARACTERISTICS (CONTINUED) DC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C T A +125 C (extended) All parameters apply across the specified operating ranges unless noted. V DD = +2.7V to 5.5V, 5 kω, 1 kω, 5 kω, 1 kω devices. Typical specifications represent values for V DD = 5.5V, T A = +25 C. Parameters Sym Min Typ Max Units Conditions Full Scale Error (MCP418 only) (code = 7Fh) Zero Scale Error (MCP418 only) (code = h) Potentiometer Integral Non-linearity Potentiometer Differential Nonlinearity Bandwidth -3 db (See Figure 2-83, load = 3 pf) V WFSE LSb 5 kω 2.7V V DD 5.5V LSb 1 kω 2.7V V DD 5.5V LSb 5 kω 2.7V V DD 5.5V LSb 1 kω 2.7V V DD 5.5V V WZSE LSb 5 kω 2.7V V DD 5.5V LSb 1 kω 2.7V V DD 5.5V LSb 5 kω 2.7V V DD 5.5V LSb 1 kω 2.7V V DD 5.5V INL -.5 ± LSb 2.7V V DD 5.5V MCP418 device only (Note 2) DNL -.25 ± LSb 2.7V V DD 5.5V MCP418 device only (Note 2) BW 2 MHz 5 kω Code = 3Fh 1 MHz 1 kω Code = 3Fh 26 khz 5 kω Code = 3Fh 1 khz 1 kω Code = 3Fh Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V W with V A = V DD and V B = V SS. 3: MCP418 device only, includes V WZSE and V WFSE. 4: Resistor terminals A, W and B s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R W ), which changes significantly over voltage and temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22147A-page 6 29 Microchip Technology Inc.

7 AC/DC CHARACTERISTICS (CONTINUED) DC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C T A +125 C (extended) All parameters apply across the specified operating ranges unless noted. V DD = +2.7V to 5.5V, 5 kω, 1 kω, 5 kω, 1 kω devices. Typical specifications represent values for V DD = 5.5V, T A = +25 C. Parameters Sym Min Typ Max Units Conditions Rheostat Integral Non-linearity MCP418 (Note 3) MCP417 and MCP419 devices only (Note 3) Rheostat Differential Nonlinearity MCP418 (Note 3) MCP417 and MCP419 devices only (Note 3) R-INL -2. ± LSb 5 kω 5.5V, I W = 9 µa LSb 2.7V, I W = 43 µa (Note 6) See Section 2. LSb 1.8V (Note 6) -2. ± LSb 1 kω 5.5V, I W = 45 µa LSb 2.7V, I W = 215 µa (Note 6) See Section 2. LSb 1.8V (Note 6) ± LSb 5 kω 5.5V, I W = 9 µa LSb 2.7V, I W = 43 µa (Note 6) See Section 2. LSb 1.8V (Note 6) -.8 ± LSb 1 kω 5.5V, I W = 45 µa LSb 2.7V, I W = 21.5 µa (Note 6) See Section 2. LSb 1.8V (Note 6) R-DNL -.5 ± LSb 5 kω 5.5V, I W = 9 ma LSb 2.7V, I W = 43 µa (Note 6) See Section 2. LSb 1.8V (Note 6) -.5 ± LSb 1 kω 5.5V, I W = 45 µa LSb 2.7V, I W = 215 µa (Note 6) See Section 2. LSb 1.8V (Note 6) ± LSb 5 kω 5.5V, I W = 9 µa ± LSb 2.7V, I W = 43 µa (Note 6) See Section 2. LSb 1.8V (Note 6) ± LSb 1 kω 5.5V, I W = 45 µa ± LSb 2.7V, I W = 21.5 µa (Note 6) See Section 2. LSb 1.8V (Note 6) Capacitance (P A ) C AW 75 pf f =1 MHz, Code = Full Scale Capacitance (P w ) C W 12 pf f =1 MHz, Code = Full Scale Capacitance (P B ) C BW 75 pf f =1 MHz, Code = Full Scale Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V W with V A = V DD and V B = V SS. 3: MCP418 device only, includes V WZSE and V WFSE. 4: Resistor terminals A, W and B s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R W ), which changes significantly over voltage and temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network 29 Microchip Technology Inc. DS22147A-page 7

8 AC/DC CHARACTERISTICS (CONTINUED) DC Characteristics Digital Inputs/Outputs (SDA, SCK) Schmitt Trigger High Input Threshold V IH.7 V DD V 1.8V V DD 5.5V Schmitt Trigger Low Input Threshold Hysteresis of Schmitt Trigger Inputs (Note 5) Output Low Voltage (SDA) V IL -.5.3V DD V V HYS.1V DD V All inputs except SDA and SCL N.A. V SDA 1 khz V DD < 2.V N.A. V V DD 2.V and.1 V DD V SCL 4 khz V DD < 2.V.5 V DD V V DD 2.V V OL V SS.2V DD V V DD < 2.V, I OL = 1 ma V SS.4 V V DD 2.V, I OL = 3 ma Input Leakage I IL -1 1 µa V IN = V DD and V IN = V SS Current Pin Capacitance C IN, C OUT 1 pf f C = 4 khz RAM (Wiper) Value Value Range N h 7Fh hex Wiper POR/BOR N POR/BOR 3Fh hex Value Power Requirements Power Supply Sensitivity (MCP418 only) Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C T A +125 C (extended) All parameters apply across the specified operating ranges unless noted. V DD = +2.7V to 5.5V, 5 kω, 1 kω, 5 kω, 1 kω devices. Typical specifications represent values for V DD = 5.5V, T A = +25 C. Parameters Sym Min Typ Max Units Conditions PSS.5.35 %/% V DD = 2.7V to 5.5V, V A = 2.7V, Code = 3Fh Note 1: Resistance is defined as the resistance between terminal A to terminal B. 2: INL and DNL are measured at V W with V A = V DD and V B = V SS. 3: MCP418 device only, includes V WZSE and V WFSE. 4: Resistor terminals A, W and B s polarity with respect to each other is not restricted. 5: This specification by design. 6: Non-linearity is affected by wiper resistance (R W ), which changes significantly over voltage and temperature. 7: POR/BOR is not rate dependent. 8: Supply current is independent of current through the resistor network DS22147A-page 8 29 Microchip Technology Inc.

9 1.1 I 2 C Mode Timing Waveforms and Requirements SCL SDA START Condition STOP Condition FIGURE 1-1: I 2 C Bus Start/Stop Bits Timing Waveforms. TABLE 1-1: I 2 C AC Characteristics Param. No. I 2 C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C TA +125 C (Extended) Operating Voltage V DD range is described in Section 2. Typical Performance Curves Symbol Characteristic Min Max Units Conditions F SCL Standard Mode 1 khz C b = 4 pf, 1.8V - 5.5V Fast Mode 4 khz C b = 4 pf, 2.7V - 5.5V D12 Cb Bus capacitive loading 1 khz mode 4 pf 4 khz mode 4 pf 9 TSU:STA START condition 1 khz mode 47 ns Only relevant for repeated Setup time 4 khz mode 6 ns START condition 91 THD:STA START condition 1 khz mode 4 ns After this period the first Hold time 4 khz mode 6 ns clock pulse is generated 92 TSU:STO STOP condition 1 khz mode 4 ns Setup time 4 khz mode 6 ns 93 THD:STO STOP condition 1 khz mode 4 ns Hold time 4 khz mode 6 ns SCL SDA In SDA Out Note 1: FIGURE 1-2: Refer to specification D12 (Cb) for load conditions. I 2 C Bus Data Timing. 29 Microchip Technology Inc. DS22147A-page 9

10 TABLE 1-2: I 2 C BUS DATA REQUIREMENTS (SLAVE MODE) I 2 C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 4 C TA +125 C (Extended) Operating Voltage VDD range is described in AC/DC characteristics Parameter Sym Characteristic Min Max Units Conditions No. 1 T HIGH Clock high time 1 khz mode 4 ns 1.8V-5.5V 4 khz mode 6 ns 2.7V-5.5V 11 T LOW Clock low time 1 khz mode 47 ns 1.8V-5.5V 4 khz mode 13 ns 2.7V-5.5V 12A (5) T RSCL SCL rise time 1 khz mode 1 ns Cb is specified to be from 4 khz mode 2 +.1Cb 3 ns 1 to 4 pf 12B (5) T RSDA SDA rise time 1 khz mode 1 ns Cb is specified to be from 4 khz mode 2 +.1Cb 3 ns 1 to 4 pf 13A (5) T FSCL SCL fall time 1 khz mode 3 ns Cb is specified to be from 4 khz mode 2 +.1Cb 4 ns 1 to 4 pf 13B (5) T FSDA SDA fall time 1 khz mode 3 ns Cb is specified to be from 4 khz mode 2 +.1Cb (4) 3 ns 1 to 4 pf 16 THD:DAT Data input hold time 17 TSU:DAT Data input setup time 19 T AA Output valid from clock 1 khz mode ns 1.8V-5.5V, Note 6 4 khz mode ns 2.7V-5.5V, Note 6 1 khz mode 25 ns (2) 4 khz mode 1 ns 1 khz mode 345 ns (1) 4 khz mode 9 ns 11 T BUF Bus free time 1 khz mode 47 ns Time the bus must be free 4 khz mode 13 ns before a new transmission can start T SP Input filter spike 1 khz mode 5 ns Philips Spec states N.A. suppression 4 khz mode 5 ns (SDA and SCL) Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 3 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (4 khz) I 2 C-bus device can be used in a standard-mode (1 khz) I 2 C-bus system, but the requirement tsu; DAT 25 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;dat = = 125 ns (according to the standard-mode I 2 C bus specification) before the SCL line is released. 3: The MCP418/MCP419 device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I 2 C specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pf for the calculations. 5: Not Tested. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. DS22147A-page 1 29 Microchip Technology Inc.

11 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V DD = +1.8V to +5.5V, V SS =GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Specified Temperature Range T A C Operating Temperature Range T A C Storage Temperature Range T A C Thermal Package Resistances Thermal Resistance, 5L-SC7 θ JA 331 C/W (Note 1) Thermal Resistance, 6L-SC7 θ JA TBD C/W Note 1: Package Power Dissipation (PDIS) is calculated as follows: P DIS = (T J - T A ) / θ JA, where: T J = Junction Temperature, T A = Ambient Temperature. 29 Microchip Technology Inc. DS22147A-page 11

12 NOTES: DS22147A-page Microchip Technology Inc.

13 2. TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. I DD (µa) khz, 5.5V 4 khz, 2.7V 1 khz, 5.5V 1 khz, 2.7V Temperature ( C) I DD Interface Inactive (µa) V V Temperature ( C) FIGURE 2-1: Interface Active Current (I DD ) vs. SCL Frequency (f SCL ) and Temperature (V DD = 1.8V, 2.7V and 5.5V). FIGURE 2-2: Interface Inactive Current (I SHDN ) vs. Temperature and V DD. (V DD = 1.8V, 2.7V and 5.5V). 29 Microchip Technology Inc. DS22147A-page 13

14 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Wiper Resistance (R W ) (ohms) INL -4C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL -4 C 25 C 85 C 125 C DNL R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL R W -4 C 85 C 125 C 25 C INL DNL Error (LSb) Wiper Setting (decimal) Wiper Setting (decimal) -.3 FIGURE 2-3: 5. kω : Pot Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V). (A = V DD, B = V SS ). FIGURE 2-6: 5. kω : Rheo Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V).(I W = 1.4mA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 125 C 85C DNL 125C DNL 85 INL -4 C 25 C DNL Wiper Setting (decimal) R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 85 C 125 C 25 C -4 C DNL R W Wiper Setting (decimal) INL Error (LSb) FIGURE 2-4: 5. kω : Pot Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V). (A = V DD, B = V SS ) FIGURE 2-7: 5. kω : Rheo Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V).(I W = 45uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL RW INL DNL Wiper Setting (decimal) Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL RW INL Wiper Setting (decimal) Error (LSb) Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. FIGURE 2-5: 5. kω : Pot Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (A = V DD, B = V SS ) FIGURE 2-8: 5. kω : Rheo Mode R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (I W = TBD, B = V SS ) DS22147A-page Microchip Technology Inc.

15 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Full-Scale Error (FSE) (LSb) V V Ambient Temperature ( C) R BW Tempco (PPM) V 5.5V Wiper Setting (decimal) FIGURE 2-9: 5. kω : Full Scale Error (FSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-12: 5. kω : R BW Tempco ΔR WB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) V V Ambient Temperature ( C) FIGURE 2-1: 5. kω : Zero Scale Error (ZSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-13: Response Time. 5. kω : Power-Up Wiper Nominal Resistance (R AB ) (Ohms) V V V Ambient Temperature ( C) Wiper V DD FIGURE 2-11: 5. kω : Nominal Resistance (Ω) vs. Temperature and V DD. FIGURE 2-14: 5. kω : Digital Feedthrough (SCL signal coupling to Wiper pin). 29 Microchip Technology Inc. DS22147A-page 15

16 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. FIGURE 2-15: 5. kω : Write Wiper (4h 3Fh) Settling Time (V DD =5.5V). FIGURE 2-18: 5. kω : Write Wiper (FFh h) Settling Time (V DD =5.5V). FIGURE 2-16: 5. kω : Write Wiper (4h 3Fh) Settling Time (V DD =2.7V). FIGURE 2-19: 5. kω : Write Wiper (FFh h) Settling Time (V DD =2.7V). FIGURE 2-17: 5. kω : Write Wiper (4h 3Fh) Settling Time (V DD =1.8V). FIGURE 2-2: 5. kω : Write Wiper (FFh h) Settling Time (V DD =1.8V). DS22147A-page Microchip Technology Inc.

17 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL -4 C DNL 85 C 125 C 25 C INL R W Error (LSb) Wiper Resistance (R W ) (ohms) C -4C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 85 C 125 C 25 C INL DNL R W Error (LSb) Wiper Setting (decimal) Wiper Setting (decimal) -.3 FIGURE 2-21: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V). (A = V DD, B = V SS ) FIGURE 2-24: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V).(I W = 45uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL -4 C INL 25 C 85 DNL Wiper Setting (decimal) 125 C R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 25 C -4 C 85 C 125 C DNL INL Wiper Setting (decimal) R W Error (LSb) FIGURE 2-22: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V). (A = V DD, B = V SS ) FIGURE 2-25: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V).(I W = 21uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL RW DNL INL Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL RW DNL INL Error (LSb) Wiper Setting (decimal) Wiper Setting (decimal) -1 Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. FIGURE 2-23: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (A = V DD, B = V SS ) FIGURE 2-26: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (I W = TBD, B = V SS ) 29 Microchip Technology Inc. DS22147A-page 17

18 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Full-Scale Error (FSE) (LSb) V V Ambient Temperature ( C) FIGURE 2-27: 1 kω : Full Scale Error (FSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). R BW Tempco (PPM) V 5.5V Wiper Setting (decimal) FIGURE 2-3: 1 kω : R BW Tempco ΔR WB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) V V Ambient Temperature ( C) FIGURE 2-28: 1 kω : Zero Scale Error (ZSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-31: Response Time. 1 kω : Power-Up Wiper 12 Nominal Resistance (R AB ) (Ohms) V 5.5V Ambient Temperature ( C) FIGURE 2-29: 1 kω : Nominal Resistance (Ω) vs. Temperature and V DD. 2.7 Wiper V DD FIGURE 2-32: 1 kω : Digital Feedthrough (SCL signal coupling to Wiper pin). DS22147A-page Microchip Technology Inc.

19 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. FIGURE 2-33: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD =5.5V). FIGURE 2-36: 1 kω : Write Wiper (FFh h) Settling Time (V DD =5.5V). FIGURE 2-34: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD =2.7V). FIGURE 2-37: 1 kω : Write Wiper (FFh h) Settling Time (V DD =2.7V). FIGURE 2-35: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD =1.8V). FIGURE 2-38: 1 kω : Write Wiper (FFh h) Settling Time (V DD =1.8V). 29 Microchip Technology Inc. DS22147A-page 19

20 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL -4 C INL 85 C 125 C DNL 25 C R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 85 C 125 C -4 C 25 C DNL INL R W Error (LSb) Wiper Setting (decimal) Wiper Setting (decimal) -.3 FIGURE 2-39: 5 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V). FIGURE 2-42: 5 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V).(I W = 9uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL C -4 C 25 C DNL INL Wiper Setting (decimal) R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 25 C 85 C -4 C 125 C DNL Wiper Setting (decimal) R W INL Error (LSb) FIGURE 2-4: 5 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V). FIGURE 2-43: 5 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V).(I W = 45uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL INL RW Wiper Setting (decimal) Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL RW INL Wiper Setting (decimal) Error (LSb) Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. FIGURE 2-41: 5 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). FIGURE 2-44: 5 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (I W = TBD, B = V SS ) DS22147A-page 2 29 Microchip Technology Inc.

21 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Full-Scale Error (FSE) (LSb) V 1.8V Ambient Temperature ( C) R BW Tempco (PPM) V 5.5V Wiper Setting (decimal) FIGURE 2-45: 5 kω : Full Scale Error (FSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-48: 5 kω : R BW Tempco ΔR WB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) V 1.8V Ambient Temperature ( C) FIGURE 2-46: 5 kω : Zero Scale Error (ZSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-49: Response Time. 5 kω : Power-Up Wiper 498 Nominal Resistance (R AB ) (Ohms) V 2.7V 5.5V Ambient Temperature ( C) Wiper V DD FIGURE 2-47: 5 kω : Nominal Resistance (Ω) vs. Temperature and V DD. FIGURE 2-5: 5 kω : Digital Feedthrough (SCL signal coupling to Wiper pin). 29 Microchip Technology Inc. DS22147A-page 21

22 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. FIGURE 2-51: 5 kω : Write Wiper (4h 3Fh) Settling Time (V DD =5.5V). FIGURE 2-54: 5 kω : Write Wiper (FFh h) Settling Time (V DD =5.5V). FIGURE 2-52: 5 kω : Write Wiper (4h 3Fh) Settling Time (V DD =2.7V). FIGURE 2-55: 5 kω : Write Wiper (FFh h) Settling Time (V DD =2.7V). FIGURE 2-53: 5 kω : Write Wiper (4h 3Fh) Settling Time (V DD =1.8V). FIGURE 2-56: 5 kω : Write Wiper (FFh h) Settling Time (V DD =1.8V). DS22147A-page Microchip Technology Inc.

23 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Wiper Resistance (R W ) (ohms) C -4C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 85 C 125 C 25 C INL DNL R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 85 C 125 C DNL -4 C 25 C INL R W Error (LSb) Wiper Setting (decimal) Wiper Setting (decimal) -.3 FIGURE 2-57: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V). FIGURE 2-6: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 5.5V). (I W = 45uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL -4 C 25 C C INL Wiper Setting (decimal) R W Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL 125 C INL 85 C -4 C 25 C DNL Wiper Setting (decimal) R W Error (LSb) FIGURE 2-58: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V). FIGURE 2-61: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 2.7V). (I W = 21uA, B = V SS ) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL RW INL Wiper Setting (decimal) Error (LSb) Wiper Resistance (R W ) (ohms) C Rw 25C Rw 85C Rw 125C Rw -4C INL 25C INL 85C INL 125C INL -4C DNL 25C DNL 85C DNL 125C DNL DNL RW Wiper Setting (decimal) INL Error (LSb) Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. FIGURE 2-59: 1 kω Pot Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). Note: Refer to AN18 for additional information on the characteristics of the wiper resistance (R W ) with respect to device voltage and wiper setting value. FIGURE 2-62: 1 kω Rheo Mode : R W (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Temperature (V DD = 1.8V). (I W = TBD, B = V SS ) 29 Microchip Technology Inc. DS22147A-page 23

24 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. Full-Scale Error (FSE) (LSb) V V Ambient Temperature ( C) R BW Tempco (PPM) V 5.5V Wiper Setting (decimal) FIGURE 2-63: 1 kω : Full Scale Error (FSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-66: 1 kω : R BW Tempco ΔR WB / ΔT vs. Code. Zero-Scale Error (ZSE) (LSb) V 1.8V Ambient Temperature ( C) FIGURE 2-64: 1 kω : Zero Scale Error (ZSE) vs. Temperature (V DD = 5.5V, 2.7V, 1.8V). FIGURE 2-67: Response Time. 1 kω : Power-Up Wiper Nominal Resistance (R AB ) (Ohms) V V V Ambient Temperature ( C) Wiper V DD FIGURE 2-65: 1 kω : Nominal Resistance (Ω) vs. Temperature and V DD. FIGURE 2-68: 1 kω : Digital Feedthrough (SCL signal coupling to Wiper pin). DS22147A-page Microchip Technology Inc.

25 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. FIGURE 2-69: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD = 5.5V). FIGURE 2-72: 1 kω : Write Wiper (FFh h) Settling Time (V DD = 5.5V). FIGURE 2-7: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD = 2.7V). FIGURE 2-73: 1 kω : Write Wiper (FFh h) Settling Time (V DD = 2.7V). FIGURE 2-71: 1 kω : Write Wiper (4h 3Fh) Settling Time (V DD = 1.8V). FIGURE 2-74: 1 kω : Write Wiper (FFh h) Settling Time (V DD = 1.8V). 29 Microchip Technology Inc. DS22147A-page 25

26 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. V IH (V) V V V Temperature ( C) V OL (mv) V (@ 3mA) V (@ 3mA).1 1.8V (@ 1mA) Temperature ( C) FIGURE 2-75: Temperature. V IH (SCL, SDA) vs. V DD and FIGURE 2-77: Temperature. V OL (SDA) vs. V DD and V 2.7V V V IL (V) V V DD (V) V Temperature ( C) Temperature ( C) FIGURE 2-76: Temperature. V IL (SCL, SDA) vs. V DD and FIGURE 2-78: and Temperature. POR/BOR Trip point vs. V DD DS22147A-page Microchip Technology Inc.

27 Note: Unless otherwise indicated, T A = +25 C, V DD = 5V, V SS = V. db 1 Code = 7Fh Code = 3Fh -1-2 Code = Fh Code = 1Fh -3 Code = 1h , 1, Frequency (khz) db 1 Code = 7Fh -1 Code = 3Fh Code = 1Fh -2 Code = Fh -3 Code = 1h , 1, Frequency (khz) FIGURE 2-79: (-3dB). 5kΩ Gain vs. Frequency FIGURE 2-82: Frequency (-3dB). 1 kω Gain vs. db Code = Fh Code = 1h Code = 1Fh Code = 7Fh Code = 3Fh 2.1 Test Circuits +5V V IN A W B V V OUT , 1, Frequency (khz) FIGURE 2-8: (-3dB). 1 kω Gain vs. Frequency FIGURE 2-83: (-3dB). Gain vs. Frequency Test db 1 Code = 7Fh -1 Code = 3Fh -2 Code = 1Fh Code = Fh -3 Code = 1h , 1, Frequency (khz) FIGURE 2-81: (-3dB). 5 kω Gain vs. Frequency 29 Microchip Technology Inc. DS22147A-page 27

28 NOTES: DS22147A-page Microchip Technology Inc.

29 3. PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. Additional descriptions of the device pins follow. TABLE 3-1: Pin Name MCP417 (SC7-6) PINOUT DESCRIPTION FOR THE MCP417/18/19 Pin Number MCP418 (SC7-6) MCP419 (SC7-5) Pin Type Buffer Type Function V DD P Positive Power Supply Input V SS P Ground SCL I/O ST (OD) I 2 C Serial Clock pin SDA I/O ST (OD) I 2 C Serial Data pin B 5 I/O A Potentiometer Terminal B W I/O A Potentiometer Wiper Terminal A 6 I/O A Potentiometer Terminal A Legend: A = Analog input ST (OD) = Schmitt Trigger with Open Drain I = Input O = Output I/O = Input/Output P = Power 29 Microchip Technology Inc. DS22147A-page 29

30 3.1 Positive Power Supply Input (V DD ) The V DD pin is the device s positive power supply input. The input power supply is relative to V SS and can range from 1.8V to 5.5V. A de-coupling capacitor on V DD (to V SS ) is recommended to achieve maximum performance. While the device s voltage is in the range of 1.8V V DD < 2.7V, the Resistor Network s electrical performance of the device may not meet the data sheet specifications. 3.2 Ground (V SS ) The V SS pin is the device ground reference. 3.3 I 2 C Serial Clock (SCL) The SCL pin is the serial clock pin of the I 2 C interface. The MCP41X acts only as a slave and the SCL pin accepts only external serial clocks. The SCL pin is an open-drain output. Refer to Section 5. Serial Interface - I 2 C Module for more details of I 2 C Serial Interface communication. W pin can support both positive and negative current. The voltage on terminal W must be between V SS and V DD. 3.7 Potentiometer Terminal A The terminal A pin (available on some devices) is connected to the internal potentiometer s terminal A. The potentiometer s terminal A is the fixed connection to the Full Scale (x7f tap) wiper value of the digital potentiometer. The terminal A pin is available on the MCP418 devices. The terminal A pin does not have a polarity relative to the terminal W pin. The terminal A pin can support both positive and negative current. The voltage on Terminal A must be between V SS and V DD. The terminal A pin is not available on the MCP417 and MCP419 devices. For these devices, the potentiometer s terminal A is internally floating. 3.4 I 2 C Serial Data (SDA) The SDA pin is the serial data pin of the I 2 C interface. The SDA pin has a Schmitt trigger input and an open-drain output. Refer to Section 5. Serial Interface - I 2 C Module for more details of I 2 C Serial Interface communication. 3.5 Potentiometer Terminal B The terminal B pin (available on some devices) is connected to the internal potentiometer s terminal B. The potentiometer s terminal B is the fixed connection to the Zero Scale (x tap) wiper value of the digital potentiometer. The terminal B pin is available on the MCP417 device. The terminal B pin does not have a polarity relative to the terminal W pin. The terminal B pin can support both positive and negative current. The voltage on terminal B must be between V SS and V DD. The terminal B pin is not available on the MCP418 and MCP419 devices. For these devices, the potentiometer s terminal B is internally connected to V SS. 3.6 Potentiometer Wiper (W) Terminal The terminal W pin is connected to the internal potentiometer s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal DS22147A-page 3 29 Microchip Technology Inc.

31 4. GENERAL OVERVIEW The MCP417/18/19 devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. This Data Sheet covers a family of three Digital Potentiometer and Rheostat devices. The MCP418 device is the Potentiometer configuration, while the MCP417 and MCP419 devices are the Rheostat configuration. Applications generally suited for the MCP41X devices include: Set point or offset trimming Sensor calibration Selectable gain and offset amplifier designs Cost-sensitive mechanical trim pot replacement As the Device Block Diagram shows, there are four main functional blocks. These are: POR/BOR Operation Serial Interface - I 2 C Module Resistor Network The POR/BOR operation and the Memory Map are discussed in this section and the I 2 C and Resistor Network operation are described in their own sections. The Serial Commands commands are discussed in Section POR/BOR Operation The Power-on Reset is the case where the device is having power applied to it from V SS. The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. The devices RAM retention voltage (V RAM ) is lower than the POR/BOR voltage trip point (V POR /V BOR ). The maximum V POR /V BOR voltage is less then 1.8V. When V POR /V BOR < V DD < 2.7V, the Resistor Network s electrical performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its volatile memory if the proper serial command is executed. Table 4-1 shows the digital pot s level of functionality across the entire V DD range, while Figure 4-1 illustrates the Power-up and Brown-out functionality BROWN-OUT RESET When the device powers down, the device V DD will cross the V POR /V BOR voltage. Once the V DD voltage decreases below the V POR /V BOR voltage the following happens: Serial Interface is disabled If the V DD voltage decreases below the V RAM voltage the following happens: Volatile wiper registers may become corrupted As the voltage recovers above the V POR /V BOR voltage see Section Power-on Reset. Serial commands not completed due to a Brown-out condition may cause the memory location to become corrupted WIPER REGISTER (RAM) The Wiper Register is volatile memory that starts functioning at the RAM retention voltage (V RAM ). The Wiper Register will be loaded with the default wiper value when V DD will rise above the V POR /V BOR voltage DEVICE CURRENTS The current of the device can be classified into two modes of the device operation. These are: Serial Interface Inactive (Static Operation) Serial Interface Active Static Operation occurs when a Stop condition is received. Static Operation is exited when a Start condition is received POWER-ON RESET When the device powers up, the device V DD will cross the V POR /V BOR voltage. Once the V DD voltage crosses the V POR /V BOR voltage, the following happens: Volatile wiper register is loaded with the default wiper value (3Fh) The device is capable of digital operation 29 Microchip Technology Inc. DS22147A-page 31

32 TABLE 4-1: DEVICE FUNCTIONALITY AT EACH V DD REGION (NOTE 1) V DD Level Serial Interface Potentiometer Terminals V DD < V BOR < 1.8V Ignored unknown Unknown V BOR V DD < 1.8V Unknown Operational with reduced electrical specs 1.8V V DD < 2.7V Accepted Operational with reduced electrical specs Wiper Setting Wiper Register loaded with POR/BOR value Wiper Register determines Wiper Setting Comment Electrical performance may not meet the data sheet specifications. 2.7V V DD 5.5V Accepted Operational Wiper Register Meets the data sheet specifications determines Wiper Setting Note 1: For system voltages below the minimum operating voltage, the customer will be recommended to use a voltage supervisor to hold the system in reset. This will ensure that MCP417/18/19 commands are not attempted out of the operating range of the device. Normal Operation Range V DD Outside Specified AC/DC Range Normal Operation Range 2.7V 1.8V V POR/BOR V RAM V SS Analog Characteristics not specified Device s Serial Interface is Not Operational Analog Characteristics not specified V BOR Delay Wiper Forced to Default POR/BOR setting FIGURE 4-1: Power-up and Brown-out. DS22147A-page Microchip Technology Inc.

33 5. SERIAL INTERFACE - I 2 C MODULE A 2-wire I 2 C serial protocol is used to write or read the digital potentiometer s wiper register. The I 2 C protocol utilizes the SCL input pin and SDA input/output pin. The I 2 C serial interface supports the following features. Slave mode of operation 7-bit addressing The following clock rate modes are supported: - Standard mode, bit rates up to 1 kb/s - Fast mode, bit rates up to 4 kb/s Support Multi-Master Applications The serial clock is generated by the Master. The I 2 C Module is compatible with the Phillips I 2 C specification. Phillips only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content for the MCP417, MCP418, and MCP419 devices are defined in this section of the Data Sheet. Figure 5-1 shows a typical I 2 C bus configurations. Single I 2 C Bus Configuration Host Controller Device 1 Device 3 Device n Device 2 Device I 2 C I/O Considerations I 2 C specifications require active low, passive high functionality on devices interfacing to the bus. Since devices may be operating on separate power supply sources, ESD clamping diodes are not permitted. The specification recommends using open drain transistors tied to V SS (common) with a pull-up resistor. The specification makes some general recommendations on the size of this pull-up, but does not specify the exact value since bus speeds and bus capacitance impacts the pull-up value for optimum system performance. Common pull-up values range from 1 kω to a max of ~1 kω. Power sensitive applications tend to choose higher values to minimize current losses during communication but these applications also typically utilize lower V DD. The SDA and SCL float (are not driving) when the device is powered down. A "glitch" filter is on the SCL and SDA pins when the pin is an input. When these pins are an output, there is a slew rate control of the pin that is independent of device frequency SLOPE CONTROL The device implements slope control on the SDA output. The slope control is defined by the fast mode specifications. For Fast (FS) mode, the device has spike suppression and Schmidt trigger inputs on the SDA and SCL pins. FIGURE 5-1: Configurations. Typical Application I 2 C Bus Refer to Section 2. Typical Performance Curves, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. 29 Microchip Technology Inc. DS22147A-page 33

34 5.2 I 2 C Bit Definitions I 2 C bit definitions include: Start Bit Data Bit Acknowledge (A) Bit Repeated Start Bit Stop Bit Clock Stretching Figure 5-8 shows the waveform for these states START BIT The Start bit (see Figure 5-2) indicates the beginning of a data transfer sequence. The Start bit is defined as the SDA signal falling when the SCL signal is High. SDA SCL S FIGURE 5-2: Start Bit DATA BIT The SDA signal may change state while the SCL signal is Low. While the SCL signal is High, the SDA signal MUST be stable (see Figure 5-3). SDA SCL S FIGURE 5-3: 1st Bit 1st Bit Data Bit. 2nd Bit 2nd Bit ACKNOWLEDGE (A) BIT The A bit (see Figure 5-4) is a response from the Slave device to the Master device. Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave device will supply an A response after the Start bit and 8 data bits have been received. The A bit will have the SDA signal low. If the Slave Address is not valid, the Slave Device will issue a Not A (A). The A bit will have the SDA signal high. If an error condition occurs (such as an A instead of A) then an START bit must be issued to reset the command state machine. TABLE 5-1: Event General Call Slave Address valid Slave Address not valid MCP417/18/19 A / A RESPONSES Acknowledge Bit Response A A A REPEATED START BIT Comment Bus Collision N.A. I 2 C Module Resets, or a Don t Care if the collision occurs on the Masters Start bit. The Repeated Start bit (see Figure 5-5) indicates the current Master Device wishes to continue communicating with the current Slave Device without releasing the I 2 C bus. The Repeated Start condition is the same as the Start condition, except that the Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer sequence and is defined as the SDA signal falling when the SCL signal is High. Note 1: A bus collision during the Repeated Start condition occurs if: SDA is sampled low when SCL goes from low to high. SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". SDA SCL 8 D A 9 SDA 1st Bit FIGURE 5-4: Acknowledge Waveform. SCL Sr = Repeated Start FIGURE 5-5: Waveform. Repeat Start Condition DS22147A-page Microchip Technology Inc.