R&D White Paper WHP 031. Reed-Solomon error correction. Research & Development BRITISH BROADCASTING CORPORATION. July C.K.P.

Transcription

1 R&D White Paper WHP 03 July 00 Reed-olomon error correction C.K.P. Clarke Research & Deelopment BRITIH BROADCATING CORPORATION

2

3 BBC Research & Deelopment White Paper WHP 03 Reed-olomon Error Correction C. K. P. Clarke Abstract Reed-olomon error correction has seeral applications in broadcasting, in particular forming part of the specification for the ETI digital terrestrial teleision standard, known as DVB-T. Hardware implementations of coders and decoders for Reed-olomon error correction are complicated and require some knowledge of the theory of Galois fields on which they are based. This note describes the underlying mathematics and the algorithms used for coding and decoding, with particular emphasis on their realisation in logic circuits. Worked examples are proided to illustrate the processes inoled. Key words: digital teleision, error-correcting codes, DVB-T, hardware implementation, Galois field arithmetic BBC 00. All rights resered.

4

5 BBC Research & Deelopment White Paper WHP 03 Reed-olomon Error Correction C. K. P. Clarke Contents Introduction... Background Theory.... Classification of Reed-olomon codes.... Galois fields Galois field elements Galois field addition and subtraction The field generator polynomial Constructing the Galois field Galois field multiplication and diision Constructing a Reed-olomon code The code generator polynomial Worked example based on a (5, ) code The code specified for DVB-T Reed-olomon Encoding The encoding process The message polynomial Forming the code word Basis for error correction Encoding example Polynomial diision Pipelined ersion Encoder hardware General arrangement Galois field adders Galois field constant multipliers Dedicated logic constant multipliers Look-up table constant multipliers Code shortening Theory of error correction Introducing errors The syndromes...6 BBC 00. All rights resered.

6 4.. Calculating the syndromes Horner's method Properties of the syndromes The syndrome equations The error locator polynomial Finding the coefficients of the error locator polynomial The direct method Berlekamp's algorithm The Euclidean algorithm The syndrome polynomial The error magnitude polynomial The key equation Applying Euclid's method to the key equation oling the error locator polynomial - the Chien search Calculating the error alues Direct calculation The Forney algorithm The deriatie of the error locator polynomial Forney's equation for the error magnitude Error correction... 5 Reed-olomon decoding techniques Main units of a Reed-olomon decoder Including errors in the worked example yndrome calculation Worked examples for the (5, ) code Hardware for syndrome calculation Code shortening Forming the error location polynomial using the Euclidean algorithm Worked example of the Euclidean algorithm Euclidean algorithm hardware Full multipliers Diision or inersion oling the error locator polynomial - the Chien search Worked example Hardware for polynomial solution Code shortening Calculating the error alues Forney algorithm Example Error alue hardware Error correction Correction example Correction hardware Implementation complexity Conclusion...33

7 7 References Appendix Berlekamp's algorithm The algorithm Worked example pecial cases in the Euclidean algorithm arithmetic ingle errors Errors that make 3 zero Arithmetic look-up tables for the examples...39

8 White Papers are distributed freely on request. Authorisation of the Chief cientist is required for publication. BBC 00. All rights resered. Except as proided below, no part of this document may be reproduced in any material form (including photocopying or storing it in any medium by electronic means) without the prior written permission of BBC Research & Deelopment except in accordance with the proisions of the (UK) Copyright, Designs and Patents Act 988. The BBC grants permission to indiiduals and organisations to make copies of the entire document (including this copyright notice) for their own internal use. No copies of this document may be published, distributed or made aailable to third parties whether by paper, electronic or other means without the BBC's prior written permission. Where necessary, third parties should be directed to the releant page on BBC's website at for a copy of this document.

9 BBC Research & Deelopment White Paper WHP 03 Reed-olomon Error Correction C. K. P. Clarke Introduction Many digital signalling applications in broadcasting use Forward Error Correction, a technique in which redundant information is added to the signal to allow the receier to detect and correct errors that may hae occurred in transmission. Many different types of code hae been deised for this purpose, but Reed-olomon codes [] hae proed to be a good compromise between efficiency (the proportion of redundant information required) and complexity (the difficulty of coding and decoding). A particularly important use of a Reed-olomon code for teleision applications is in the DVB-T transmission standard []. Hitherto, modulators and demodulators for DVB-T hae, in general, used custom chips to proide the Reed-olomon encoding and decoding functions. Howeer, there are circumstances (such as for digital radio cameras) where it would be beneficial to include these processes in gate array designs for the transmitter and receier. This would then proide the flexibility to modify the encoding parameters to suit the particular requirements of the radio camera application without sacrificing the compactness of single-chip implementation. Although custom core designs for gate arrays are aailable, the charges are significant and can complicate further exploitation of the intellectual property embodied in a design. Although Reed-olomon codes are described in many books on coding theory and hae been the subect of many ournal papers, the description of the hardware techniques inoled is generally superficial, if described at all. The principal aim of this paper is to proide the basic information needed for the design of hardware implementations of Reed-olomon coders and decoders, particularly those for the DVB-T system. The mathematical basis for Reed-olomon codes is complicated, but it is necessary to hae a reasonable understanding of at least what needs to be done, if not why it is done. Therefore this paper first proides some essential background to the theory of Reed-olomon codes and the Galois field arithmetic on which the codes are based. Then the process of encoding is described, first mathematically and then in terms of logic circuits. This is followed by an explanation of the basis of error correction and then by some of the decoding algorithms commonly applied in error correction hardware. Although some proofs are included, some results are ust stated as a means of controlling the length of the document. At each stage, the techniques used are illustrated with worked examples.

10 Background Theory. Classification of Reed-olomon codes There are many categories of error correcting codes, the main ones being block codes and conolutional codes. A Reed-olomon code is a block code, meaning that the message to be transmitted is diided up into separate blocks of data. Each block then has parity protection information added to it to form a self-contained code word. It is also, as generally used, a systematic code, which means that the encoding process does not alter the message symbols and the protection symbols are added as a separate part of the block. This is shown diagrammatically in Figure. code word (n symbols) symbol (m bits) original message (k symbols) parity (n-k=t symbols) Figure - Reed-olomon code definitions Also, a Reed-olomon code is a linear code (adding two code words produces another code word) and it is cyclic (cyclically shifting the symbols of a code word produces another code word). It belongs to the family of Bose-Chaudhuri-Hocquenghem (BCH) codes [3, 4], but is distinguished by haing multi-bit symbols. This makes the code particularly good at dealing with bursts of errors because, although a symbol may hae all its bits in error, this counts as only one symbol error in terms of the correction capacity of the code. Choosing different parameters for a code proides different leels of protection and affects the complexity of implementation. Thus a Reed-olomon code can be described as an (n, k) code, where n is the block length in symbols and k is the number of information symbols in the message. Also n m -... () where m is the number of bits in a symbol. When () is not an equality, this is referred to as a shortened form of the code. There are n-k parity symbols and t symbol errors can be corrected in a block, where or t = (n-k)/ t = (n-k-)/ for n-k een for n-k odd. Unfortunately, the notation used in the literature on error correcting codes, although generally similar, is not uniersally consistent. Although the notation used here is representatie of that used elsewhere, the reader should be aware that confusing differences in terminology can arise. It is therefore particularly important to be clear about how the parameters of a code are specified.

11 . Galois fields To proceed further requires some understanding of the theory of finite fields, otherwise known as Galois fields after the French mathematician... Galois field elements A Galois field consists of a set of elements (numbers). The elements are based on a primitie element, usually denoted α, and take the alues: 0, α 0, α, α,..., α N-... () to form a set of m elements, where N= m -. The field is then known as GF( m ). The alue of α is usually chosen to be, although other alues can be used. Haing chosen α, higher powers can then be obtained by multiplying by α at each step. Howeer, it should be noted that the rules of multiplication in a Galois field are not those that we might normally expect. This is explained in ection..5. In addition to the powers of α form, shown in (), each field element can also be represented by a polynomial expression of the form: a m m x... ax a0 where the coefficients a m- to a 0 take the alues 0 or. Thus we can describe a field element using the binary number a m-... a a 0 and the m field elements correspond to the m combinations of the m-bit number. For example, in the Galois field with 6 elements (known as GF(6), so that m=4), the polynomial representation is: a 3 0 3x ax ax a0x with a 3 a a a 0 corresponding to the binary numbers 0000 to. Alternatiely, we can refer to the field elements by the decimal equialents 0 to 5 as a short-hand ersion of the binary numbers. Arithmetic in a finite field has processes of addition, subtraction, multiplication and diision, but these differ from those we are used to with normal integers. The effect of these differences is that any arithmetic combination of field elements always produces another field element... Galois field addition and subtraction When we add two field elements, we add the two polynomials: where m 0 m 0 m 0 ( am x... ax a0x ) ( bm x... b x b0 x ) = cm x... cx c0x c i = a i b i for 0 i m-. Howeer, the coefficients can only take the alues 0 and, so c i = 0 for a i = b i and c i = for a i b i... (3) Thus two Galois field elements are added by modulo-two addition of the coefficients, or in binary form, producing the bit-by-bit exclusie-or function of the two binary numbers. 3

12 For example, in GF(6) we can add field elements x 3 x and x 3 x to produce x x. As binary numbers, this is: 00 0 = 0 or as decimals 0 3 = 7 which can be seen from: 00 (0) 0 (3) 0 (7) Because of the exclusie-or function, the addition of any element to itself produces zero. o we should not be surprised that in a Galois field: = 0. Table 7 in Appendix 8.3 proides a look-up table for additions in GF(6). ubtraction of two Galois field elements turns out to be exactly the same as addition because although the coefficients produced by subtracting the polynomials take the form: c i = a i - b i for 0 i m- the resulting alues for c i are the same as in (3). o, in this case, we get the more familiar result: - = 0 and for our other example: 0-3 = 7. It is useful to realise that a field element can be added or subtracted with exactly the same effect, so minus signs can be replaced by plus signs in field element arithmetic...3 The field generator polynomial An important part of the definition of a finite field, and therefore of a Reed-olomon code, is the field generator polynomial or primitie polynomial, p(x). This is a polynomial of degree m which is irreducible, that is, a polynomial with no factors. It forms part of the process of multiplying two field elements together. For a Galois field of a particular size, there is sometimes a choice of suitable polynomials. Using a different field generator polynomial from that specified will produce incorrect results. For GF(6), the polynomial 4 p ( x) = x x... (4) is irreducible and therefore will be used in the following sections. An alternatie which could hae been used for GF(6) is 4 3 p ( x) = x x...4 Constructing the Galois field All the non-zero elements of the Galois field can be constructed by using the fact that the primitie element α is a root of the field generator polynomial, so that 4

13 p(α) = 0. Thus, for GF(6) with the field generator polynomial shown in (4), we can write: or α 4 α = 0 α 4 = α (remembering that and are the same in a Galois field). Multiplying by α at each stage, using α to substitute for α 4 and adding the resulting terms can be used to obtain the complete field as shown in Table. This shows the field element alues in both index and polynomial forms along with the binary and decimal short-hand ersions of the polynomial representation. If the process shown in Table is continued beyond α 4, it is found that α 5 = α 0, α 6 = α,... so that the sequence repeats with all the alues remaining alid field elements. index form polynomial form binary form decimal form α α α 000 α α α 3 α α 4 α 00 3 α 5 α α 00 6 α 6 α 3 α 00 α 7 α 3 α 0 α 8 α 00 5 α 9 α 3 α 00 0 α 0 α α 0 7 α α 3 α α 0 4 α α 3 α α 5 α 3 α 3 α 0 3 α 4 α Table - The field elements for GF(6) with p(x) = x 4 x..5 Galois field multiplication and diision traightforward multiplication of two polynomials of degree m- results in a polynomial of degree m-, which is therefore not a alid element of GF( m ). Thus multiplication in a Galois field is defined as the product modulo the field generator polynomial, p(x). The product modulo p(x) is obtained by diiding the product polynomial by p(x) and taking the remainder, which ensures that the result is always of degree m- or less and therefore a alid field element. For example, if we multiply the alues 0 and 3 from GF(6) represented by their polynomial expressions, we get: ( x 3 x)( x 3 x ) = x = x 6 6 x x 5 5 x x 3 4 x 4 x x 5 3 x... (5)

14 To complete the multiplication, the result of (5) has to be diided by x 4 x. Diision of one polynomial by another is similar to conentional long diision. Thus it consists of multiplying the diisor by a alue to make it the same degree as the diidend and then subtracting (which for field elements is the same as adding). This is repeated using the remainder at each stage until the terms of the diidend are exhausted. The quotient is then the series of alues used to multiply the diisor at each stage plus any remainder left at the final stage. This can be shown more easily by arranging the terms of the polynomials in columns according to their significance and then the calculation can be made on the basis of the coefficient alues (0 or ) as shown below. x 6 x 5 x 4 x 3 x x x 0 diidend: diisor x : 0 0 diisor x: diisor : o the quotient is x x and the remainder, which is the product of 0 and 3 that we were originally seeking, is x 3 x (binary 0 or decimal ). o we can write: 0 3 =. Table 8 in Appendix 8.3 proides a look-up table for multiplications in GF(6) with the field generator polynomial of equation (4). Alternatiely the process of equation (5) can be performed using the coefficients of the polynomials in columns. First shifted ersions of x 3 x are added according to the non-zero coefficients of x 3 x. Then, instead of the diision process, we can use substitutions taken from Table for any non-zero terms that exceed the degree of the field elements and add these as shown: x 6 x 5 x 4 x 3 x x x 0 x 3 : 0 0 x : 0 0 : x 4 = x 0 0 x 5 = x x 0 0 x 6 = x 3 x A further alternatie technique for multiplication in a Galois field, which is also conenient for diision, is based on logarithms. If the two numbers to be multiplied are represented in index form, then the product can be obtained by adding the indices modulo m -. For example, by inspecting the alues in Table we find: so 0 = α 9 and 3 = α = α 9 α 3 = α (93)mod 5 = α ()mod 5 = α 7. Again by inspection using Table we find that: α 7 = 6

15 giing the result obtained by multiplying the polynomials. A slight disadantage of the logarithmic method is that field element 0 cannot be represented in index form. The method therefore has to sense the presence of zero alues and force the result accordingly. The logarithmic technique can also be used for diision: 0 = α 7 α 9 = α (7-9)mod 5 = α (-)mod 5 = α 3 = 3. Howeer, diision of two field elements is often accomplished by multiplying by the inerse of the diisor. The inerse of a field element is defined as the element alue that when multiplied by the field element produces a alue of (= α 0 ). It is therefore possible to tabulate the inerse alues of the field elements using Table. For example, 0 = α 9, so its inerse is α (-9)mod 5 = α 6 = from Table. o we can write: 0 = and then the product can be calculated by any of the methods aboe to be 3..3 Constructing a Reed-olomon code The alues of the message and parity symbols of a Reed-olomon code are elements of a Galois field. Thus for a code based on m-bit symbols, the Galois field has m elements..3. The code generator polynomial An (n, k) Reed-olomon code is constructed by forming the code generator polynomial g(x), consisting of n-k=t factors, the roots of which are consecutie elements of the Galois field. Choosing consecutie elements ensures that the distance properties of the code are maximised. Thus the code generator polynomial takes the form: b b b t g( x) = ( x α )( x α )...( x α )... (6) It should be noted that this expression is often quoted in the literature with subtle ariations to catch the unwary. For example, the factors are often written as (x α i ), which emphasises that g(x) = 0 when x = α i and those familiar with Galois fields realise that α i is exactly the same as α i. Also, some choose roots starting with α 0 (b=0 in equation 6), while many others start with α, the primitie element (b= in equation 6). While each is alid, it results in a completely different code requiring changes in both the coder and decoder operation. If the chosen alue of b is near m -, m then some of the roots may reach or exceed α. In this case the index alues modulo m - can be substituted. mall reductions in the complexity of hardware implementations can result by choosing b=0, but this is not significant..3. Worked example based on a (5, ) code pecific examples are ery helpful for obtaining a full understanding of the processes inoled in Reed-olomon coding and decoding. Howeer, the (55, 39) code used in DVB-T is too unwieldy to be used for an example. In particular, the message length of seeral hundred symbols leads to polynomials with seeral hundred terms! In iew of this, the much simpler (5, ) code will be used to go through the full process of coding and decoding using methods that can be extended generally to other Reed-olomon codes. Definition details of the (55, 39) code used for DVB-T are shown in ection

16 For a (5, ) code, the block length is 5 symbols, of which are information symbols and the remaining 4 are parity words. Because t=, the code can correct errors in up to symbols in a block. ubstituting for n in: n = m - gies the alue of m as 4, so each symbol consists of a 4-bit word and the code is based on the Galois field with 6 elements. The example will use the field generator polynomial of equation (4), so that the arithmetic for the code will be based on the Galois field shown in Table. The code generator polynomial for correcting up to error words requires 4 consecutie elements of the field as roots, so we can choose: g(x) = (x α 0 ) (x α ) (x α ) (x α 3 ) = (x ) (x ) (x 4) (x 8) using the index and decimal short-hand forms, respectiely. This expression has to be multiplied out to produce a polynomial in powers of x, which is done by multiplying the factors and adding together terms of the same order. As multiplication is easier in index form and addition is easier in polynomial form, the calculation inoles repeatedly conerting from one format to the other using Table. This is best done with a computer program for all but the simplest codes. Alternatiely, we can take it factor by factor and use the look-up tables of Appendix 8.3 to gie: g(x) = (x ) (x ) (x 4) (x 8) = (x 3x ) (x 4) (x 8) = (x 3 7x 4x 8) (x 8) = x 4 5x 3 3x x... (7). This can also be expressed as: g(x) = α 0 x 4 α x 3 α 4 x α 0 x α 6 with the polynomial coefficients in index form..3.3 The code specified for DVB-T The DVB-T standard [] specifies a (55, 39, t=8) Reed-olomon code, shortened to form a (04, 88, t=8) code, so that the 88 bytes of the input packet will be extended with 6 parity bytes to produce a coded block length of 04 symbols. For this code, the Galois field has 56 elements (m=8) and the polynomial representation of a field element is: a x a6x a5x a4x a3x ax ax a0x corresponding to the binary numbers to. Alternatiely, we can use the decimal equialents 0 to 55. The specification also mentions the field generator polynomial, gien as: p ( x) = x x x x... (8). This allows us to construct a table of field element alues for GF(56) as shown in Table. This shows how the field element alues can be built up row by row for the 56 element Galois field in a similar manner to the construction of Table. At each step the binary number representing the 8

17 polynomial coefficient alues is shifted to the left by one position (equialent to multiplying by x) and 0 is added in the x 0 column. If the shift causes a to be lost at the left-hand side, then 0000 is added to the columns, this being the substitution for x 8 obtained from the field generator polynomial (8) as x 8 = x 4 x 3 x. Clearly the full table for this field would be extensie. index polynomial form decimal form x 7 x 6 x 5 x 4 x 3 x x x α α α α α α α α α α α Table - Construction of the Galois field of 56 elements The DVB-T specification shows the code generator polynomial as: g(x) = (xλ 0 ) (xλ ) (xλ )... (xλ 5 ) where λ = 0 HE. This identifies the primitie element of the Galois field as, represented by the symbol λ rather than the more usual α, and corresponds to the b=0 ersion of equation (6). When multiplied out, the DVB-T code generator polynomial becomes: g(x) = x 6 59x 5 3x 4 04x 3 89x 68x 09x 0 30x 9 3 Reed-olomon Encoding 8x 8 63x 7 65x 6 4x 5 9x 4 98x 3 50x 36x 59. The Galois field theory of ection proides the grounding to the processes of Reed-olomon encoding and decoding described in this and the following sections. In particular, the arithmetic processes on which hardware implementations are based rely heaily on the preceding theory. 3. The encoding process 3.. The message polynomial The k information symbols that form the message to be encoded as one block can be represented by a polynomial M(x) of order k-, so that: M(x) = M k- x k-... M x M 0 9

18 where each of the coefficients M k-,..., M, M 0 is an m-bit message symbol, that is, an element of GF( m ). M k- is the first symbol of the message. 3.. Forming the code word To encode the message, the message polynomial is first multiplied by x n-k and the result diided by the generator polynomial, g(x). Diision by g(x) produces a quotient q(x) and a remainder r(x), where r(x) is of degree up to n-k-. Thus: n k M ( x) x r( x) = q( x)... (9) g( x) g( x) Haing produced r(x) by diision, the transmitted code word T(x) can then be formed by combining M(x) and r(x) as follows: T(x) = M(x) x n-k r(x) = M k- x n-... M 0 x n-k r n-k- x n-k-... r 0 which shows that the code word is produced in the required systematic form Basis for error correction Adding the remainder, r(x), ensures that the encoded message polynomial will always be diisible by the generator polynomial without remainder. This can be seen by multiplying equation (9) by g(x): and rearranging: n k M ( x) x = g( x) q( x) r( x) n k M ( x) x r( x) = g( x) q( x) whereupon we note that the left-hand side is the transmitted code word, T(x), and that the right-hand side has g(x) as a factor. Also, because the generator polynomial, equation (6), has been chosen to consist of a number of factors, each of these is also a factor of the encoded message polynomial and will diide it without remainder. Thus, if this is not true for the receied message, it is clear that one or more errors has occurred. 3. Encoding example We can now choose a message consisting of eleen 4-bit symbols for our (5, ) code, for example, the alues,, 3, 4, 5, 6, 7, 8, 9, 0, which we wish to encode. These alues are represented by a message polynomial: x 0 x 9 3x 8 4x 7 5x 6 6x 5 7x 4 8x 3 9x 0x... (0). The message polynomial is then multiplied by x 4 to gie: x 4 x 3 3x 4x 5x 0 6x 9 7x 8 8x 7 9x 6 0x 5 x 4 to allow space for the four parity symbols. This polynomial is then diided by the code generator polynomial, equation (7), to produce the four parity symbols as a remainder. This can be accomplished in columns as a long diision process as shown before, except that in this case, the coefficients of the polynomials are field elements of GF(6) instead of binary alues, so the process is more complicated. 0

19 3.. Polynomial diision At each step the generator polynomial is multiplied by a factor, shown at the left-hand column, to make the most significant term the same as that of the remainder from the preious step. When subtracted (added), the most significant term disappears and a new remainder is formed. The steps of the diision process are as follows: x 4 x 3 x x x 0 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x x x x x x x x x x x x x and the diision produces the remainder: r(x) = 3x 3 3x x. The quotient, q(x), produced as the left-hand column of multiplying alues is not required and is discarded. The encoded message polynomial T(x) is then: x 4 x 3 3x 4x 5x 0 6x 9 7x 8 8x 7 9x 6 0x 5 x 4 3x 3 3x x... () or, written more simply:,, 3, 4, 5, 6, 7, 8, 9, 0,, 3, 3,,.

20 3.. Pipelined ersion Hardware encoders usually operate on pipelined data, so the diision calculation is made in a slightly altered form using the message bits one at a time as they are presented: x 4 x 3 x x x 0 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x x x g(x) g(x) g(x) g(x) g(x) g(x) g(x) g(x) g(x) g(x) g(x) With this arrangement, the first message alue is added to the contents of the most significant column, initially zero. The resulting alue,, is then multiplied by the remaining coefficients of the generator polynomial 5, 3,, to gie the alues to be added to the contents of the remaining columns, which are also initially zero. Then the second message alue,, is added to the contents of the next most significant column, 5, to produce 3. This alue is multiplied by the generator polynomial coefficients to gie the alues 7, 4, 3, and 3, and so on.

21 3.3 Encoder hardware 3.3. General arrangement The pipelined calculation shown in section 3.. is performed using the conentional encoder circuit shown in Figure. All the data paths shown proide for 4-bit alues. 3 5 KE D D D D GF adder input output GF multiplier control Figure - A (5, ) Reed-olomon encoder During the message input period, the selector passes the input alues directly to the output and the AND gate is enabled. After the eleen calculation steps shown aboe hae been completed (in eleen consecutie clock periods) the remainder is contained in the D-type registers. The control waeform then changes so that the AND gate preents further feedback to the multipliers and the four remainder symbol alues are clocked out of the registers and routed to the output by the selector Galois field adders The adders of Figure perform bit-by-bit addition modulo- of 4-bit numbers and each consists of four -input exclusie-or gates. The multipliers, howeer, can be implemented in a number of different ways Galois field constant multipliers ince each of these units is multiplying by a constant alue, one approach would be to use a full multiplier and to fix one input. Although a full multiplier is significantly more complicated, with an FPGA design, the logic synthesis process would strip out at least some of the unused circuitry. More will be said of full multipliers in ection The other two approaches that come to mind are either to work out the equialent logic circuit or to specify it as a look-up table, using a read-only memory Dedicated logic constant multipliers For the logic circuit approach, we can work out the required functionality by using a general polynomial representation of the input signal a 3 α 3 a α a α a 0. This is then multiplied by the polynomials represented by the alues 5, 3, and from Table. This inoles producing a shifted ersion of the input for each non-zero coefficient of the multiplying polynomial. Where the shifted ersions produce alues in the α 6, α 5 or α 4 columns, the 4-bit equialents (from Table ) are substituted. The bit alues in each of the α 3, α, α and α 0 columns are then added to gie the required input bit contributions for each output bit. 3

22 For example, for multiplication by 5 (= α 3 α α ): α 6 α 5 α 4 α 3 α α α 0 α 3 a 3 a a a α a 3 a a a α a 3 a a a 0 0 a 3 a a a 0 a 3 a a 3 a a a a a a 3 a a a 3 0 a a 3 a a 3 0 a 3 a a 0 a a a 0 a a 0 a 0 a a a 3 The input bits contributing to a particular output bit are identified by the summation at the foot of each column. imilar calculations can be performed for multiplication by 3 (= α ), (=) and (= α 3 α ) and gie the results: α 3 α α α 0 3 a a 3 a a a 0 a a 3 a 0 a 3 a 3 a a a 0 a 0 a a 3 a 0 a a a 3 a a As the additions are modulo, these are implemented with exclusie-or gates as shown in Figure 3. multiply by 5 multiply by 3 multiply by multiply by a 3 o 3 a 3 o 3 a 3 o 3 a 3 o 3 a o a o a o a o a o a o a o a o a 0 o 0 a 0 o 0 a 0 o 0 a 0 o 0 Figure 3 - Multipliers for the circuit of Figure Look-up table constant multipliers Alternatiely, each multiplier can be implemented as a look-up table with m = 6 entries. The entry alues can be obtained by cyclically shifting the non-zero elements from Table according to the index of the multiplication factor. This is because the multiplying index is added to the index of the input, modulo 5, thus shifting the results according to the multiplying alue. Howeer, the binary alues of the polynomial coefficients of the input need to be arranged in ascending order to match the binary addressing of the look-up table memory. When this is done the alues shown in Table 3 are produced. 4

23 3.4 Code shortening input 5 = α 3 = α 4 = α 0 = α 6 index form decimal form decimal form decimal form decimal form decimal form α α 3 6 α α α α α α α α α α α α α Table 3 - Look-up tables for the fixed multipliers of Figure For a shortened ersion of the (5, ) code, for example a (, 8) code, the first three terms of the message polynomial, equation (0), would be set to zero. The effect of this on the pipelined calculation in section 3.. is that all the columns would contain zero until the first non-zero input alue associated with the x term. The calculation would then proceed as if it had been started at that point. Because of this, the circuit arrangement of Figure can be used for the shortened code as long as the control waeform is high during the input data period, in this case eight clock periods instead of eleen. 4 Theory of error correction 4. Introducing errors Errors can be added to the coded message polynomial, T(x), in the form of an error polynomial, E(x). Thus the receied polynomial, R(x), is gien by: where R(x) = T(x) E(x)... () E(x) = E n- x n-... E x E 0 and each of the coefficients E n-... E 0 is an m-bit error alue, represented by an element of GF( m ), with the positions of the errors in the code word being determined by the degree of x for that term. Clearly, if more than t = (n-k)/ of the E alues are non-zero, then the correction capacity of the code is exceeded and the errors are not correctable. 5

24 4. The syndromes 4.. Calculating the syndromes In section 3..3 it was shown that the transmitted code word is always diisible by the generator polynomial without remainder and that this property extends to the indiidual factors of the generator polynomial. Therefore the first step in the decoding process is to diide the receied polynomial by each of the factors (x α i ) of the generator polynomial, equation (6). This produces a quotient and a remainder, that is: R( x) i = Q ( x) i i i x α x α for b i b t... (3) where b is chosen to match the set of consecutie factors in (6). The remainders i resulting from these diisions are known as the syndromes and, for b=0, can be written as 0... t-. Rearranging (3) produces: i = Q ( x) ( x α ) R( x) i i so that when x = α i this reduces to: i = R(α i ) = R n- (α i ) n- R n- (α i ) n-... R α i R 0... (4) where the coefficients R n-... R 0 are the symbols of the receied code word. This means that each of the syndrome alues can also be obtained by substituting x = α i in the receied polynomial, as an alternatie to the diision of R(x) by (x α i ) to form the remainder. 4.. Horner's method Equation (4) can be re-written as: i = (... (R n- α i R n- )α i... R )α i R 0 In this form, known as Horner's method, the process starts by multiplying the first coefficient R n- by α i. Then each subsequent coefficient is added to the preious product and the resulting sum multiplied by α i until finally R 0 is added. This has the adantage that the multiplication is always by the same alue α i at each stage Properties of the syndromes ubstituting in equation (): R(α i ) = T(α i ) E(α i ) in which T(α i ) = 0 because xα i is a factor of g(x), which is a factor of T(x). o: R(α i ) = E(α i ) = i... (5). This means that the syndrome alues are only dependent on the error pattern and are not affected by the data alues. Also, when no errors hae occurred, all the syndrome alues are zero. 6

25 7 4.3 The syndrome equations While the relationship in equation (4) between the syndromes and the receied code word allows the syndrome alues to be calculated, that in equation (5) between the syndromes and the error polynomial can be used to produce a set of simultaneous equations from which the errors can be found. To do this, the error polynomial E(x) is re-written to include only the terms that correspond to errors. o assuming errors hae occurred, where t: e e e x x x x E =... ) ( where e,... e identify the locations of the errors in the code word as the corresponding powers of x, while,... represent the error alues at those locations. ubstituting this in (5) produces i i i ie ie ie i i E = = = ) ( α α α α where e e α α = =,..., are known as error locators. Then the t syndrome equations can be written as: = t t t t M K M M M M M M K K M M (6). It is important to note here that the syndromes are written as 0... t- to correspond with the roots α 0... α t- and the powers of are dependent on haing chosen those roots in equation (6). 4.4 The error locator polynomial The next step is to introduce the error locator polynomial. This turns out to be one of the more confusing steps in Reed-olomon decoding because the literature defines two different, but related, expressions as the error locator polynomial. One form, often denoted σ(x), is constructed to hae the error locators... as its roots, that is, factors of the form (x ) for = to. When expanded, these factors produce a polynomial of degree with coefficients σ... σ : x x x x x x x σ σ σ σ = =... ) )...( )( ( ) ( The alternatie form is usually denoted Λ(x). This is constructed to hae factors of the form ( x) and therefore has the inerses -,..., - of the error locators as its roots. When expanded, these factors produce a polynomial of degree with coefficients Λ... Λ : ) )...( )( ( ) ( x x x x = Λ x x x Λ Λ Λ = (7). Howeer, it turns out that

26 8 Λ = x x x ) ( σ so the coefficients σ... σ are the same as Λ... Λ. 4.5 Finding the coefficients of the error locator polynomial 4.5. The direct method For each error, there is a corresponding root - that makes Λ(x) equal to zero. o 0... = Λ Λ Λ or multiplied through by i : 0... = Λ Λ Λ i i i i. imilar equations can be produced for all the errors (different alues of ) and the terms collected so that: = = = = Λ Λ i i i 0... or 0... = Λ Λ i i i recognising that the summation terms are the syndrome alues using (6). imilar equations can be deried for other alues of i so that: 0... = Λ Λ i i i for i = 0,..., t--... (8) so producing a set of t- simultaneous equations, sometimes referred to as the key equations, with Λ... Λ as unknowns. To sole this set of equations for Λ... Λ, we can use the first equations, represented by the matrix equation (9), except that, at this point, is unknown: Λ Λ Λ Λ = M L M M M M L L L M (9). Because of this, it is necessary to calculate the determinant of the matrix for each alue of, starting at =t and working down, until a non-zero determinant is found. This indicates that the equations are independent and can be soled. The coefficients of the error locator polynomial Λ... Λ can then be found by inerting the matrix to sole the equations Berlekamp's algorithm Berlekamp's algorithm [5, 6] is a more efficient iteratie technique of soling equations (8) that also oercomes the problem of not knowing. This is done by forming an approximation to the error locator polynomial, starting with Λ(x)=. Then at each stage, an error alue is formed by

27 substituting the approximate coefficients into the equations corresponding to that alue of. The error is then used to refine a correction polynomial, which is then added to improe the approximate Λ(x). The process ends when the approximate error locator polynomial checks consistently with the remaining equations. A statement of the algorithm and a worked example is included in the Appendix as ection The Euclidean algorithm Another efficient technique for obtaining the coefficients of the error location polynomial is based on Euclid's method for finding the highest common factor of two numbers [7]. This uses the relationship between the errors and the syndromes expressed in the form of an equation based on polynomials. This is also often referred to as the fundamental or key equation and requires two new polynomials, the syndrome and error magnitude polynomials, to be introduced The syndrome polynomial For use in the key equation, the syndrome polynomial is defined as: (x) = bt- x t-... b x b where the coefficients are the t syndrome alues calculated from the receied code word using equation (4), or its equialent for other alues of b The error magnitude polynomial The error magnitude polynomial can be written as: Ω(x) = Ω - x -... Ω x Ω 0 This is sometimes referred to as the error alue or error ealuator polynomial The key equation The key equation can then be written as: Ω(x) = [(x) Λ(x)] mod x t where (x) is the syndrome polynomial and Λ(x) is the error locator polynomial. Any terms of degree x t or higher in the product are ignored, so that Ω 0 = b Ω = b b Λ M Ω - = b- b- Λ... b Λ Applying Euclid's method to the key equation Euclid's method [7] can find the highest common factor d of two elements a and b, such that: ua b = d... (0) where u and are coefficients produced by the algorithm. The product of (x), which has degree t-, and Λ(x), which has degree, will hae degree t-. o the product can be expressed as: 9

28 (x) Λ(x) = F(x) x t Ω(x) in which the terms of x t and aboe are represented by the F(x) term and the remaining part is represented by Ω(x). This can be rearranged as: Λ(x) (x) F(x) x t = Ω(x) so that the known terms (x) and x t correspond to the a and b terms of (0). The algorithm then consists of diiding x t by (x) to produce a remainder. (x) then becomes the diidend and the remainder becomes the diisor to produce a new remainder. This process is continued until the degree of the remainder becomes less than t. At this point, both the remainder Ω(x) and the multiplying factor Λ(x) are aailable as terms in the calculation. 4.6 oling the error locator polynomial - the Chien search Haing calculated the coefficient alues, Λ... Λ, of the error locator polynomial, it is now possible to find its roots. If the polynomial is written in the form: Λ(x) = (x - ) (x - )... then clearly the function alue will be zero if x = -, -,..., that is: e e x = α, α,... The roots, and hence the alues of..., are found by trial and error, known as the Chien search [8], in which all the possible alues of the roots (the field alues α i, 0 i n-) are substituted into equation (7) and the results ealuated. If the expression reduces to zero, then that alue of x is a root and identifies the error position. ince the first symbol of the code word corresponds to the x n- term, the search begins with the alue α -(n-) (=α ), then α -(n-) (=α ), and continues to α 0, which corresponds to the last symbol of the code word. 4.7 Calculating the error alues 4.7. Direct calculation When the error locations... are substituted into the syndrome equations (6), the first equations can be soled by matrix inersion to produce the error alues The Forney algorithm This is an alternatie means of calculating the error alue haing established the error locator polynomial Λ(x) and the error alue polynomial Ω(x). If Berlekamp's algorithm has been used to find Λ(x), then Ω(x) can be found by using the relationships in ection The algorithm makes use of the deriatie of the error locator polynomial The deriatie of the error locator polynomial For a polynomial f(x) gien by: f(x) = f x f x... f x the deriatie is gien by: f '(x) = f f x... f x - Howeer, for the error locator polynomial Λ(x), for x = -, the deriatie reduces to: 0

29 Λ'( - ) = Λ Λ 3 - Λ which amounts to setting een-powered terms of the error locator polynomial to zero and diiding through by x = Forney's equation for the error magnitude Methods of calculating the error alues... based on Forney's algorithm are more efficient than the direct method of soling the syndrome equations as described in section According to Forney's algorithm, the error alue is gien by: b Ω( ) =...() Λ'( ) where Λ'( - ) is the deriatie of Λ(x) for x = -. When b=, the -b term disappears, so the formula is often quoted in the literature as simply Ω/Λ', which gies the wrong results for b=0 and other alues. (The alue of b is defined in equation (6).) It should be noted that equation () only gies alid results for symbol positions containing an error. If the calculation is made at other positions, the result is generally non-zero and inalid. The Chien search is therefore still needed to identify the error positions. 4.8 Error correction Haing located the symbols containing errors, identified by, and calculated the alues of those errors, the errors can be corrected by adding the error polynomial E(x) to the receied polynomial R(x). It should be remembered that conentionally the highest degree term of the receied polynomial corresponds to the first symbol of the receied code word. 5 Reed-olomon decoding techniques Whereas the preious section has dealt with the underlying theory and, in some cases, identified seeral alternatie approaches to some processes, this section will describe a specific approach to decoding hardware based around the Euclidean algorithm. 5. Main units of a Reed-olomon decoder The arrangement of the main units of a Reed-olomon decoder reflects, for the most part, the processes of the preious ection. input R data delay output calculate the syndromes form the error location polynomial: Euclid Ω, Λ' calculate the error alues: Forney method Ω/Λ' Λ Chien search for error positions Figure 4 - Main processes of a Reed-olomon decoder

30 Thus, in Figure 4, the first process is to calculate the syndrome alues from the incoming code word. These are then used to find the coefficients of the error locator polynomial Λ... Λ and the error alue polynomial Ω 0... Ω - using the Euclidean algorithm. The error locations are identified by the Chien search and the error alues are calculated using Forney's method. As these calculations inole all the symbols of the receied code word, it is necessary to store the message until the results of the calculation are aailable. Then, to correct the errors, each error alue is added (modulo ) to the symbol at the appropriate location in the receied code word. 5.. Including errors in the worked example. The steps in the decoding process are illustrated by continuing the worked example of the (5, ) Reed-olomon code that was used with the encoding process in ection 3. Introducing two errors in the sixth (x 9 term) and thirteenth (x term) symbols of the coded message produces an error polynomial with two non-zero terms: E(x) = E 9 x 9 E x and we can choose, for example, E 9 = 3 and E =, so that three bits of the sixth symbol are altered while only one bit of the thirteenth symbol is affected. Although there are four bits in error, in terms of the error correcting capacity of the code this constitutes only two errors because this is based on the number of symbols in error. Therefore these errors should be correctable. Addition of the errors makes the receied message: R(x) = (x 4 x 3 3x 4x 5x 0 6x 9 7x 8 8x 7 9x 6 0x 5 x 4 3x 3 3x x ) (3x 9 x ) = x 4 x 3 3x 4x 5x 0 x 9 7x 8 8x 7 9x 6 0x 5 x 4 3x 3 x x... () or, more simply,, 3, 4, 5,, 7, 8, 9, 0,, 3,,,. 5. yndrome calculation 5.. Worked examples for the (5, ) code ection 4. showed that the syndrome corresponding to each root α i of the generator polynomial could be calculated either by diiding the receied polynomial R(x) by x α i, or by ealuating R(α i ). In the latter case, Horner's method proes an efficient technique. For the direct diision process, we would use a method of calculation similar to that of ection 3... Howeer, the pipelined approach of ection 3.. is more suitable for hardware, so the calculation of 0, corresponding to root α 0, consists of the following steps where, in this case, the multiplication by α 0 (= ) is triial:

31 x 4 x 3 x x x 0 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x x x 0 0 R 4 α 0 R 3 α R 3 α R 4 α R 0 5 α 0 R 9 α R 8 7 α R 7 8 α R 6 9 α 0 R 5 0 α R 4 α R 3 3 α R α R α R 0 5 giing 0 = 5. Alternatiely, we can use substitution of the root alue in equation (), so for, substituting α for x and using the equialences of Table, we obtain: = (α ) 4 (α ) 3 3(α ) 4(α ) 5(α ) 0 (α ) 9 7(α ) 8 8(α ) 7 9(α ) 6 0(α ) 5 (α ) 4 3(α ) 3 (α ) (α ) = 3 Or if we use Horner's method: = ((((((((((((( α ) α 3) α 4) α 5) α ) α 7) α 8) α 9) α 0) α ) α 3) α ) α ) α = 4 3

32 Alternatiely Horner's method can be written as a series of intermediate steps. o, for 3 where α 3 = 8: ( 0 ) 8 = 8 ( 8 ) 8 = 5 ( 5 3 ) 8 = 0 ( 0 4 ) 8 = 9 ( 9 5 ) 8 = 0 ( 0 ) 8 = 8 ( 8 7 ) 8 = ( 8 ) 8 = 4 ( 4 9 ) 8 = ( 0 ) 8 = ( ) 8 = 3 ( 3 3 ) 8 = 9 ( 9 ) 8 = ( ) 8 = 0 0 = so that 3 =. 5.. Hardware for syndrome calculation The hardware arrangement used for syndrome calculation, shown in Figure 5, can be interpreted either as a pipelined polynomial diision or as an implementation of Horner's method. α i i D control input Figure 5 - Forming a syndrome In the case of polynomial diision, the process is basically the same as that described for encoding in section 3.. (and shown in Figure ), except much simpler because the degree of the diisor polynomial is one. Thus there is only one feedback term with one multiplier, multiplying by α i, and only one register. As before, the input alues are added to the output of the register and all the data paths are m-bit signals. The only difference in this case is that the AND-gate is used to preent the contents of the register contributing at the start of the code word, which was achieed in Figure by clearing the registers at the start of each block. Alternatiely, this circuit can be seen as a direct implementation of Horner's method, in which the incoming symbol alue is added to the contents of the register before being multiplied by α i and the result returned to the register. Clearly, all n symbols of the code word hae to be accumulated before the syndrome alue is produced. Also, t circuits of the form of Figure 5 are required, one for each alue of α i, each 4

33 corresponding to a root of the generator polynomial. The Galois field adders and fixed multipliers can be implemented using the techniques described in ections 3.3. and Code shortening If the code is used in a shortened form, such as with a (, 8) code as described in ection 3.4, then the first part of the message is not present. Thus the pipelined calculation need only begin when the first element of the shortened message is present. The same arrangement can therefore be used for the shortened code proided that the AND gate is controlled to preent the register contents contributing to the first addition. 5.3 Forming the error location polynomial using the Euclidean algorithm 5.3. Worked example of the Euclidean algorithm To continue the worked example to find the coefficients of the error locator polynomial, it is first necessary to form the syndrome polynomial. The syndrome alues obtained in ection 5.. are: 0 = 5, = 3, = 4 and 3 = so the syndrome polynomial is: (x) = 3 x 3 x x 0 = x 3 4x 3x 5 The first step of the algorithm (described in ection ) is to diide x t (in this case x 4 ) by (x). This inoles multiplying (x) 0x (0 = /) and subtracting (adding), followed by (x) 6 (6 = 4/) and subtracting. This gies the remainder 6x 6x 4. In the right hand process, the initial alue is multiplied by the same alues used in the diision process and added to an initial sum alue of zero. o the right-hand calculation produces 0 (0x 6) = 0x 6. x 4 x 3 x x x 0 x x x 0 diidend: diisor 0x: diisor 6: remainder: Haing completed the first diision, the degree of the remainder is not less than t (= ), so we do a new diision using the preious diisor as the diidend and the remainder as the diisor, that is, diiding (x) by the remainder 6x 6x 4. First the remainder is multiplied by x ( = /6) and subtracted, then multiplied by 3 (3 = 8/6) and subtracted to produce the remainder 3x 4. At the right hand side, the preious initial alue () becomes the initial sum alue and the preious result (0x 6) is multiplied by the alues used in the diision process. This produces (0x 6) (x 3) = 7x 7x 9. x 4 x 3 x x x 0 x x x 0 diidend: diisor x: diisor 3: remainder:

34 In general, the process would continue repeating the steps described aboe, but now the degree of the remainder (= ) is less than t (= ) so the process is complete. The two results 7x 7x 9 and 3x 4 are in fact γ Λ(x) and γ Ω(x), respectiely, where in this case the constant factor γ=9. o diiding through by 9 gies the polynomials in the defined forms: and Λ(x) = 4x 4x Ω(x) = 6x 5. Further examples of the Euclidean algorithm, which result in somewhat different sequences of operations, are shown in Appendix Euclidean algorithm hardware The Euclidean algorithm can be performed using the arrangement of Figure 6 in which all data paths are 4 bits wide. This arrangement broadly follows the calculation of ection 5.3. so that the lower part of the diagram performs the diision (the left-hand side of the calculation) while the upper part performs the multiplication (the right-hand side). Initially, the B register is loaded to contain the diidend and the A register to contain the syndrome alues. Also, the C register is set to and the D register, set to the initial sum, zero. At each step, the contents of B 3 is diided by A 3 (that is, multiplied by the inerse of A 3 ) and the result used in the remaining multipliers. The results of the multiplications are then added to the contents of the B and D registers to form the intermediate results. At step one, the results are loaded back into the B and D registers and the contents of the A and C registers are retained. At step two, the contents of the A and C registers are transferred to the B and D registers and the calculation results are loaded into the A and C registers. Where necessary, the alues are shifted between registers of different significance to take account of multiplications by x. Table 4 shows the contents of the registers at intermediate steps in the calculation. step A 3 A A A 0 B 3 B B B 0 C C 0 D D D Table 4 - Register contents in the calculation of ection 5.3. It should be noted that Figure 6 represents a simplification of the process and, as shown, will not produce the correct results for some error patterns. This occurs when the contents of A 3 is zero, potentially resulting in diision by zero. ome examples of this are shown in the Appendix, ection 8.. Additional circuitry is required to sense these conditions and to alter the calculation sequence of Figure 6 accordingly. A further point is that the Λ and Ω outputs produced when the calculation is complete do not include the final diision shown in Thus these alues are multiplied by a constant (γ) relatie to their defined alues. The arrangement of Figure 6 shows the Euclidean algorithm in a highly parallel form and there is considerable scope for reducing the hardware requirements by re-using circuit elements, particularly the multipliers. A commonly used arrangement is to recognise that the upper and lower circuits of Figure 6 are ery similar. Because of this, it is possible to use one circuit with duplicated registers and to interleae the steps of the calculation accordingly. 6

35 0 D 0 γ 0 D γλ D C 0 C s h i f t γλ B 0 B B B 3 γω 0 γω A 0 A A A 3 in Figure 6 - The Euclidean processor 7

36 5.3.. Full multipliers The Galois field multipliers described up to this point hae inoled multiplication by a constant, whereas those of Figure 6 are full multipliers. Full multipliers can be implemented by similar techniques to those described in ection 3.3.3, either as dedicated logic multipliers or as look-up tables, although with m locations, the latter technique rapidly becomes inefficient as the alue of m increases. It is also possible to use look-up tables with m locations to conert to logarithms, which can then be added modulo m - and the result conerted back with an inerse look-up table. The need to sense zero inputs and produce a modulo m - result generally makes this technique more complicated than the shift-and-add approach. a 3 a a a 0 o 3 o o o 0 b 3 b b b 0 Figure 7 - A full multiplier for GF(6) Figure 7 shows the arrangement of a 4-bit by 4-bit shift-and-add multiplier, drawn to emphasise the three underlying processes. First the array of AND gates generates the set of shifted product terms, producing seen leels of significance. Next the first column of exclusie-or gates sums (modulo ) the products at each leel. Finally, the three upper leels beyond the range of field alues are conerted to fall within the field, using the relationships of Table, and the contributions added by the three pairs of exclusie-or gates Diision or inersion Haing designed a multiplier, then it is probably most straightforward to implement Galois field diision using a look-up table with m locations to generate the inerse and then to multiply. The inerses are easily calculated as shown in Table 5 using field elements in index form. This shows the element alues in ascending order to correspond with the addressing of the look-up table. 8

37 input (decimal) input (index) inerse (index) α 0 α 0 α α - = α α 4 α -4 = α 4 4 α α - = α α 8 α -8 = α 7 6 α 5 α -5 = α α 0 α -0 = α α 3 α -3 = α 5 9 α 4 α -4 = α 0 α 9 α -9 = α 6 α 7 α -7 = α 8 5 α 6 α -6 = α α 3 α -3 = α 4 4 α α - = α α α - = α 3 8 inerse (decimal) Table 5 - Look-up table for inerse alues in GF(6) The table includes 0 as the Galois field inerse of oling the error locator polynomial - the Chien search 5.4. Worked example To try the first position in the code word, corresponding to e =4, we need to substitute α -4 into the error locator polynomial: Λ(x) = 4x 4x Λ(α -4 ) = 4(α -4 ) 4(α -4 ) = 4(α ) 4(α ) = α α α α α 0 = α 3 α α 0 = 3 5 = 3 and the non-zero result shows that the first position does not contain an error. For subsequent positions, the power of α to be substituted will adance by one for the x term and by two for the x term, so we can tabulate the calculations as shown in Table 6. 9

38 x x term x term unity sum α -4 α 3 α 3 α -3 α 0 α 3 3 α - α α 4 α - α 4 α 0 3 α -0 α 6 α 5 α -9 α 8 α 0 α -8 α 0 α 3 4 α -7 α α 4 3 α -6 α 4 α 5 4 α -5 α α 6 5 α -4 α 3 α 7 α -3 α 5 α 8 α - α 7 α 9 0 α - α 9 α 0 α 0 α α Table 6 - Terms in the Chien search example Haing deried the alues for the first row (multiplying Λ by α and Λ by α), each new row can be obtained from the preious row in the same way. Adding the terms together then produces the sum for each row. The two sum alues of zero in Table 6 identify the error positions correctly as the 6th and 3th symbols, corresponding to the x 9 and x terms, respectiely, of the code word polynomial. Checking these results by multiplying out the factors, we obtain: (α 9 x )(α x ) = α x (α 9 α )x = 4x 4x = Λ(x) as before Hardware for polynomial solution The calculations of Table 6 form the basis of the method used to find the roots of the error locator polynomial shown in Figure 8. The alue of each term in the polynomial is calculated by loading the coefficient alue γλ and multiplying it by the appropriate power of α. Then at each successie clock period, the next alue of the term is produced by multiplying the preious result by the power of α. Adding the alues of the indiidual terms together produces the alue of the polynomial for each symbol position in turn. Detecting zero alues of the sum identifies symbol positions containing errors and is not affected by the presence of the multiplying factor γ. It may be noted that in the case of b=0 the top term simplifies to holding the γ alue in the register Code shortening For shortened codes, because the polynomial alue is calculated from the start of the full-length code word, a correction to the initial alue of each term is needed to take account of the multiplications by α, α,... which would hae occurred at the missing symbol positions. 30

39 γ α 0 D =0 error position γλ α D γλ'(α - ) α α γλ D 5.5 Calculating the error alues Figure 8 - The Chien search 5.5. Forney algorithm Example The Forney method consists of calculating the quotient of two polynomials, Ω(x) and Λ'(x), the deriatie of Λ(x), for x = -. The deriatie is obtained by setting een powers of x to zero in: Λ(x) = 4x 4x and diiding by x, so that: Λ'( - ) = 4 - / - = 4. o from equation () we can derie that: 6 5 = 4 Knowing the positions of the errors from ection 5.4. as the 6th (x 9 term) and 3th (x term) the error alues can be calculated for = α 9 as: 9 9 6α 5 = α = 3 4 and for = α 6α 5 = α = 4 which match the alues introduced in section

40 5.5. Error alue hardware Hardware calculation of the two polynomials, Ω(x) and Λ'(x), can be performed in a similar manner to that for the Chien search shown in Figure 8, in particular, the function alue is calculated for each symbol position in the code word in successie clock periods. γω 0 α 0 D error alue α γω D γλ'(α - ) α error position in Figure 9 - Calculating error alues Thus in Figure 9, there are two circuits producing the alues of the Ω and Ω 0 terms, which are added together. Howeer, the arrangement includes some simplifications, so that the deriatie term is obtained directly from the Chien search circuit in Figure 8. It turns out that when code generator polynomial roots beginning with α 0 are chosen (b=0), the sum of the odd terms of Λ(x) can be used directly. This proides Λ'(α - )/α directly, which eliminates the need to multiply Ω(α - ) by α. Thus the error alue can be obtained by diision of the two terms, shown in Figure 9 as inersion and multiplication. A further point is that the hardware arrangement operates without diiding through by the constant γ as shown at the end of ection This step is not needed because the multiplying factor cancels in the diision so that the error alue results are not affected. 5.6 Error correction Errors are corrected by adding the error alues, to the receied symbols R at the positions located by the alues Correction example The error alues and positions can be formed into an error ector and added to the receied code word to produce the corrected message: x 4 x 3 x x x 0 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x x x

41 5.6. Correction hardware The AND gate of Figure 9 is enabled at the error positions identified by the Chien search circuit of Figure 8 so that the alid error alues are added modulo- to the appropriately delayed symbol alues of the code word, as shown in Figure Implementation complexity Haing come this far, the reader will appreciate that the error correction capacity, t, has a strong influence on the complexity of the equations. Also, the number of bits in a symbol, m, affects the complexity of the Galois field arithmetic. Because of the full multiplications inoled, the calculations to find the coefficients of the error location polynomial Λ(x) and the error magnitude polynomial Ω(x) form the most complicated part of the decoding process. It is difficult to proide meaningful gate-count figures for hardware implementations of the coder and decoder because these will depend strongly on the degree of parallelism that is used in the circuitry. It is also possible to exchange complexity for delay in the decoding process. If the logic family is able to support clock rates at a large multiple of the symbol rate (such as 8 times), then the complexity of many parts of the circuit are capable of being reduced by that factor. Also, some designers may feel that a processor-based implementation is appropriate. For the DVB-T system, the Reed-olomon coder represents only a small part (say -3%) of the whole modulator. The decoder is much more significant, amounting to perhaps about 7% of the demodulator. Considering that the demodulator may be approaching three times the complexity of the modulator, the Reed-olomon decoder is probably up to ten times the complexity of the coder. To gie a different perspectie, the Reed-olomon decoder may be about one quarter of the complexity of the Fast Fourier Transform required for DVB-T. o far, no mention has been made of erasure processing, in which the locations of the errors are known (through some separate indication from the receier) but the error alues are not. This doubles the error correction capacity of the code and consequently doubles the number of equations to be soled. It therefore represents a substantial increase in complexity oer the basic correction process. 6 Conclusion This note has described the theory and methods of Reed-olomon coding and decoding with a iew to facilitating implementation in dedicated hardware. This has particular releance in implementations of the DVB-T standard. Reed-olomon coding circuits for DVB-T hae already been implemented in hardware as part of the Digital Radio Camera proect. For the decoder, the techniques described hae been tested in software for the DVB-T standard and in hardware for simpler codes. It is belieed that this has identified many of the pitfalls inoled in these processes. 7 References [] Reed, I.. and olomon, G., 960. Polynomial Codes oer Certain Finite Fields, J. IAM., Vol. 8, pp , 960. [] ETI, 997. Digital broadcasting systems for teleision, sound and data serices; Framing structure, channel coding and modulation for digital terrestrial teleision. European Telecommunication tandard ET [3] Bose, R. C. and Chaudhuri, D. K. R., 960. On a class of error-correcting binary group codes. Inf. Control, Vol. 3,

42 [4] Hocquenghem, A., 959. Codes correcteurs d'erreurs, Chiffres., Vol., 959. [5] Berlekamp, E. R. Algebraic Coding Theory. McGraw-Hill, New ork, 968. [6] Purser, M., 995. Introduction to error-correcting codes. Artech House, Boston, London, 995. [7] Pretzel, O. 99. Error-correcting codes and finite fields. Clarendon Press, Oxford, 99. [8] Chien, R. T Cyclic decoding procedures for Bose-Chaudhuri-Hocquenghem codes. IEEE Transactions on Information Theory, Vol. IT-0, pp Appendix 8. Berlekamp's algorithm 8.. The algorithm Berlekamp's algorithm [6] consists of a series of steps based on improing an approximation to the error locator polynomial Λ(x) using a correction polynomial C(x) and the syndrome alues 0... t- as inputs. It also requires a step parameter K and a parameter L which tracks the order of the equations. Initially we set: K =, L = 0, Λ(x) = and C(x) = x. Then each step consists of first calculating an error alue e using: e = 0 L i= Λi K i o initially e = 0. Then, proided that e is non-zero, we produce Λ * (x), a new approximation to the error locator polynomial, gien by: Λ * (x) = Λ(x) e C(x). If L < K, we set L = K - L and form a new correction polynomial from: C(x) = Λ(x) e. If e is zero, these calculations are omitted. Then we produce a new C(x) by multiplying the old correction polynomial by x, replace Λ(x) by Λ * (x) and increment K. The next step starts with the new alues of K, L, Λ(x) and C(x) until K > t in which case Λ(x) is the required error locator polynomial. 34

43 8.. Worked example The syndrome alues calculated in ection 5.. are: tep : 0 = 5, = 3, = 4 and 3 = K L C C C 0 Λ Λ Λ e = 0 = L < K, so we set L = K - L = and diide C(x) by e: /e = /5 = 8 C C C 0 8 Λ(x) Multiply C(x) x Increment K t = 4, so continue. tep : K L C C C 0 Λ Λ Λ e = Λ 0 = 35 5 = L = K, so we skip some steps, then: C C C 0 x C(x) Increment K 3 t = 4, so continue. tep 3: K L C C C 0 Λ Λ Λ e = Λ = 4 3 = L < K, so we set L = K - L = and diide C(x) by e: /e = /0 = C C C 0 Λ(x) 0 3 x C(x) 3 0 Increment K 4 t = 4, so continue. 35

44 tep 4: K L C C C 0 Λ Λ Λ e = 3 Λ Λ = 45 3 = L = K, so we skip some steps, then: C C C 0 x C(x) 0 0 Increment K 5 > t = 4, so the process is complete and Λ(x) = 4x 4x as before. 8. pecial cases in the Euclidean algorithm arithmetic There are particular combinations of error alues which cause the Euclidean algorithm calculations to depart from the steps shown in ection 5.3. and so require the processor of Figure 6 to follow a different sequence. This is necessary when leading zero alues occur in the diisor. 8.. ingle errors Instead of the two errors introduced in ection 5.., we will introduce only one, so that: E(x) = E 9 x 9 and we make E 9 = 3 as before. Then the syndrome alues obtained are: 0 = 3, =, = and 3 = 7 so the syndrome polynomial is: (x) = 3 x 3 x x 0 = 7x 3 x x 3 As before, the first step of the algorithm is to diide x t by (x), but this time we multiply (x) 6x (6 = /7) and subtract, followed by multiplying (x) 4 (4 = /7) and subtracting. This gies the remainder 0. In the right hand process, the initial alue is multiplied by the same alues used in the diision process and added to an initial sum alue of zero. o the right-hand calculation produces 0 (6x 4) = 6x 4. x 4 x 3 x x x 0 x x x 0 diidend: diisor 6x: diisor 4: remainder: In this case, the degree of the remainder (=0) is already less than t (= ) so that the required alues are: and γλ(x) = 6x 4 γω(x) = 0. 36

45 When these alues are used in the subsequent processes, the location and alue of the error are identified correctly. o for = α 9 we find: γλ(α -9 ) = 6(α -9 ) 4 = 6(α 6 ) 4 = 0 and the error alue is calculated as: 9 0 = α = Errors that make 3 zero If we change one of the original error alues, so that: E(x) = E 9 x 9 E x but we make E 9 = 7, instead of 3, while E =, as before. Then the syndrome alues obtained are: 0 = 5, =, = and 3 = 0 and the syndrome polynomial is: (x) = 3 x 3 x x 0 = x x 5 This time we hae to multiply (x) 5x (5 = /) and subtract, followed by (x) 5x (5 = /) and subtracting, and then multiply (x) 5 (5 = 3/) and subtract. This gies the remainder x 6. In the right hand process, the initial alue is multiplied by the same alues used in the diision process and added to an initial sum alue of zero. o the right-hand calculation produces 0 (5x 5x 5) = 5x 5x 5. x 4 x 3 x x x 0 x x x 0 diidend: diisor 5x : diisor 5x: diisor 5: remainder: In this case, after a three step diision, the degree of the remainder (=) is already less than t (= ) so that the required alues are: γλ(x) = 5x 5x 5 and γω(x) = x 6. Again these alues lead to the correct locations and alues of the errors. o for = α 9 we find: γλ(α -9 ) = 5(α -9 ) 5(α -9 ) 5 37

46 = 5(α 6 ) 5(α 6 ) 5 = 0 and the error alue is calculated as: -9 9 α 6 = α = 7 5 Also for = α we find: γλ(α - ) = 5(α - ) 5(α - ) 5 = 5(α 3 ) 5(α 3 ) 5 = 0 and the error alue is calculated as: = α - α 6 = 5 38

47 8.3 Arithmetic look-up tables for the examples Tables 7 and 8 below show the results for addition of two field elements (Table 7) and multiplication of two field elements (Table 8) in the sixteen element Galois field with the field 4 generator polynomial p ( x) = x x Table 7 - Addition table for use in the worked examples Table 8 - Multiplication table for use in the worked examples 39