Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0

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2 Advanced Validation & Testing of PCIe Gen 2 Agilent Technologies Sandy Chang / Project Manager Yen Yi Fu / Project Manager July, 8 & 10, 2008 Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization B1-1

3 Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Introduction Testing and Validation When using a standard technology such as PCI Express, detailed testing and validation is critical to ensure devices will interoperate with each other Implementation of a proper test plan can significantly reduce cost later. For example: How much does an ASIC spin cost when a bug is found after a device is in the field? B1-2

4 Introduction Basic vs Advanced Testing Basic Testing PCI-SIG Compliance Advanced Testing From the Link Layer Test Specification At this point this specification does not describe the full set of PCI Express tests for all link layer requirements. Going forward, as the testing gets mature, it is expected that more tests may be added as deemed necessary. Ensuring your device is fully validated against the specifications Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization B1-3

5 Introduction PCI-SIG Compliance Testing Physical Layer Validate Signal Quality of TX, Ref Clock and PLL Loop Bandwidth Configuration Space Verify required fields and values behave as specified Link Layer & Transaction Layer Exercise protocol, error and boundary layer conditions Platform Configuration Validate BIOS correctly handles different topologies of PCI Express Devices Demonstrated Interoperability Show that device drives load and device operates in actual PCI Express System Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization B1-4

6 Introduction Physical Layer Testing Goals for PCIe 2.0 Goals for PHY testing are unchanged from PCI Express 1.0 Achieving those goals is more challenging Additional requirements added to increase confidence that designs are robust Verify designs achieve critical specification targets Jitter Eye mask Reference Clock Voltage and Jitter margining Receiver Margining 2.0 changes Changes Implemented under the 2.0 Specs - Physical Layer Changes to the PCIe Base Specification 5GT/s Different de-emphasis levels PLL bandwidth testing Backward compatibility with PCIe 1.1 PCIe Card Electromechanical (CEM) Specification Changes Rj / Dj tables and new jitter budgets Changes to Reference clock phase jitter specification 2 port measurement method for systems B1-5

7 2.0 changes Signal Level and BW 2.5G de-emphasis = /- 0.5 db 5G de-emphasis = /- 0.5 OR /- 0.5 db Low swing voltage levels = no de-emphasis BW dependant peaking requirements 3dB for 8 to 16MHz 1dB for 5 to 8MHz 2.5G same as 1.1 spec. (1.5M to 22MHz Loop BW with no more than 3dB peaking) PCIe 2.0 PLL Loop Bandwidth Testing External Ref Clock Input Equipment Required: Sine Wave Source (1GHz min) Modulated Pulse Generator (100MHz) Spectrum Analyzer (3 GHz min) Modified CBB2 Steps: Sweep source Mhz (-20dBM) SA: 35KHz Res BW, 40MHz Span, 2.5 GHz center Set display to peak hold Normalize response to note 3dB point Measure PLL BW B1-6

8 5GT/s challenges CEM Spec targets connector System Board TX Clarification of measurement location Compared to 1.1 Chip + Interconnect Add-in Card TX 5GT/s challenges 5GT/s jitter challenges Jitter measurement more complex! Jitter decomposition required +/ For BER Speed dependant phase jitter filters 2.5G = 1 pole HPF 5G = step band pass filter Error correction needed to measure TX at pins B1-7

9 Error Correction De-embedding New Transmitter base specification requirement - Measurements at 5.0 GT/s must de-embed the test fixture - It is also acceptable to use a common test fixture and deembed it for measurements at both 2.5 and 5.0 GT/s. What does it mean to de-embed? - Measurement at 5.0 GT/s must de-convolve effects of compliance test board to yield an effective measurement at Tx pins. PCI-SIG Developers Conference 2008 June B1-8

10 Error Correction Source of Measurement Inaccuracies impedance mismatches probing effects smaller geometries test cables and adapters fixturing device packaging, etc. SCOPE NOISE FLOOR! Why is error correction needed to measure at TX pins? There are multiple ways to offset these measurement impairments. calibration methods mathematical signal processing de-embedding/embedding techniques Measurement system noise will be amplified by de-embedding techniques Error Correction Error Correction Techniques Pre-measurement operations Post-measurement operations S-parameters Skew Calibration Probe Attenuation/offset Channel Vertical Cal Channel Trigger Cal Calibrating the Scope DSO91304A 13GHz Oscilloscope De-embedding the CLB/CBB N5230A PNA-L Network Analyzer B1-9 Fixture effects Removed

11 Error Correction De-embedding Loss Compensation or Gain Function Compensate for Probing and Fixture Loss Add Margin to Transmitter Characterization Allows more accurate measurement of de-emphasis levels at transmitter Compliance Requirement for Gen 2 De-embedded Eye Measured Eye V Measured Waveform Tx PHY Channel Rx PHY De-Convolve Function De-embedded Waveform 2008 Agilent Measurement Agilent Restricted Forum Page 19 Test Tool and Fixture Changes SQ Test Tool Requirements System Board Use of CLB 2.0 SMP to SMA adapter, phase matched SMA cables Terminate all lanes except the lane under test Measure transmitted clock and data waveforms simultaneously with high speed oscilloscope Use compliance pattern 1M UI of data Sample rate of 40GS/s (25ps) Compute: eye diagram, Rj, Dj, Tj@10^-12 BER, average data rate, rise/fall time, mode toggle Measure all lanes of all 5GT/s capable slots B1-10

12 Test Tool and Fixture Changes Test Tool Requirements Add-in Card Use of CBB 2.0 SMP for all lanes, phase matched SMA cables Terminate all lanes except the lane under test Measure transmitted waveform with high speed oscilloscope Use compliance pattern 1M UI of data Sample rate of no more than 25 ps Compute: eye diagram, Rj, Dj, BER, average data rate, rise/fall time, mode toggle Measure all lanes Agilent Tools What to Look for in PCI Express Compliance Automation Key Requirements: - 1M UI automated data acquisition - Batch run capability for greater testing coverage or quick spot checking - Implement measurements that respect the PCIe Specification - Automated tools should self-scale to ensure top accuracy for each measurement performed - Results must be consistent with PCI-SIG tools used at Compliance Workshops B1-11

13 Agilent Tools Test Results with the Agilent N5393B HTML based automatic report generator allows you to easily share test results. Select the version to test Select the test point Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Month ##, 200X B1-12

14 Protocol Test Considerations Logical Physical Layer testing Link Training issues I start link training but I cannot establish a link I plugged my 1.1 card into a 2.0 system and it does not work, why? I plugged my 2.0 card into a 1.1 system and it does not work I pass electrical compliance but I still cannot link Although a card may successfully pass the electrical requirements, it may not be possible to link for other reasons. This is critical for interoperability! Month ##, 200X Protocol Test Considerations Logical Physical Layer testing Some suggested reasons why a link may not successfully train Presence Detect: Are the PRSNT1# and PRSNT2# pins wired correctly on both the system slot and the add in card? Does the system support Hot-Plug? This is especially critical when the link width of the card and the mechanical and electrical link width of the slot do not match Reference Clock: Are the reference clocks on both sides compatible? Link Width: Does the link train to the desired width? Does it link in all required widths? Reserved bits in Training Sequences: When the reserved bits are used in the TS1 and TS2 ordered sets (for example, Gen 2 uses some bits which were reserved in Gen 1), do the devices still train successfully? Month ##, 200X B1-13

15 Protocol Test Considerations Electrical Testing vs. Protocol Testing Electrical testing forces the device into a special compliance mode designed to create the worst case scenario electrical characteristics. The device is connected to a piece of test equipment which measures the electrical characteristics Protocol Testing requires that the device link up with another device. Testing this requires 2 types of tester - Protocol Analyzer - Stimulus tool, such as exerciser The PCISIG has an extensive list of test assertions which can be used to verify that a device is compliant to the specification Month ##, 200X PCI-SIG Compliance Goals for PCIe 2.0 Compliance Testing Goals for Protocol testing are unchanged from PCI Express 1.0 Verify devices have met the critical specification targets for : Config space test specification Link layer test specifications Transaction layer test specifications Platform Bios test specifications Additional testing regarding reserved bits usage Month ##, 200X B1-14

16 PCI-SIG Compliance Link and Transaction Layer Testing Test descriptions are not changed for Gen 2 Link and Transaction Layer tests with the exception of the Reserved bits test New for PCIe 2.0 devices All Gen 2 devices will be tested at 2.5GT/s AND 5GT/s where appropriate Gen 2, 2.5G only devices will be tested using the Gen 2 PTC Reserved bits test tries to link up with all reserved bits set in training sequences Month ##, 200X PCI-SIG Compliance Link and Transaction Layer Tests Link Layer tests are a subset of the compliance checklist a cross section of tests which if the device is compliant would indicate a reasonable chance of interoperability. Includes Error checking, and dealing with Link stability problems List of Link Layer and Transaction Layer Tests BadLCRC CorruptedDLLPs DuplicateTLPSeqNum LinkRetrainOnRetryFailNoAckNak LinkRetrainOnRetryFail ReXmitOnNak ReplayNumTest ReplayTLPOrder ReplayTimerTest RequestCompletion ReserverdFieldsDLLPReceive UndefinedDLLPEncoding WrongSeqNumInAckDLLP Month ##, 200X B1-15

17 PCI-SIG Compliance PCI-SIG Test Specification Documents Test Number Event the test checks for Detailed description of the test case Month ##, 200X Agilent Tools Test Hardware Setup Card being tested for compliance Agilent PTC 2.0 approved by the PCI-SIG for Protocol Gold Suite testing. Agilent protocol analyzer for troubleshooting any issues that come up Month ##, 200X B1-16

18 Agilent Tools Agilent PTC II Software 1. Matching test case names to easily identify which tests are being run 3. Color coded to easily identify what the test results 4. Report tab, with detailed execution and reason for pass/fail 2. Matching test descriptions to the test spec. 5. Message framing to allow the analyzer to easily capture the key parts of the test execution Month ##, 200X 2.0 Changes Reserved Bit Testing the reserved bits in Training Sequences In the 1.1 base specification, there are several reserved bits in the TS1 ordered set. Some of these bits are now used in the 2.0 specification mainly in relation to the speed change and capability, in the Data Rate Identifier field: 1.1 Specification 2.0 Specification Month ##, 200X B1-17

19 2.0 Changes Reserved Bit Testing the Reserved Bits in Training Sequences It has been observed that many cards built to the 1.1 specification do not in fact ignore the reserved bits when used by a 2.0 device. This can cause the link not to train and is a severe interoperability issue The PCISIG has introduced an official test in the Link Layer test specification which ensures that devices can link when these reserved bits are used This test can be done with the Agilent Gen 2 PTC card or any of the Agilent Gen 2 Exerciser products Since official 1.1 testing will not change in the foreseeable future, this test can be run on 1.1 cards and is a very strong indicator whether the device will operate in a 2.0 system. Month ##, 200X Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Month ##, 200X B1-18

20 2.0 Changes - LTSSM Protocol Changes in the 2.0 Specs Changes to the PCIe Base Specification Physical Layer : Logical Sub Block 5GT/s Support LTSSM use of Recovery state to Change to 5G speed Link up/down configure Dynamic Link Width change Data Link Layer Replay timers for 5GT/s support Transaction Layer Principally unchanged the test specification is identical Configuration Space Reserved bit usage, new registers to support different speed options Month ##, 200X 2.0 Changes - LTSSM How does link training work? Device A... TS TS TS TS TS TS TS TS... Device B Two PCI Express devices exchange Training Sequences to negotiate link parameters like lane polarity link number set of lanes that belong to the link lane numbers scrambler enabled or disabled link speed number of fast training sequences required... Training Sequences are also used to switch the link to low power states. Month ##, 200X B1-19

21 2.0 Changes - LTSSM How does link training work? Example from the PCI Express 2.0 specification, Polling.Active state (p. 196): Transmitter sends TS1 Ordered Sets with Lane and Link numbers set to PAD (K23.7) on all lanes... Next state is Polling.Configuration after at least 1024 TS1 Ordered Sets were transmitted, and all Lanes... receive eight consecutive TS1 or TS2 Ordered Sets... Otherwise, after a 24 ms timeout the next state is: Polling.Configuration if,... Polling.Compliance if... Else Detect if the conditions to transition to Polling.Configuration and Polling Compliance are not met. Month ##, 200X LTSSM Test Challenges What are the LTSSM test challenges? The LTSSM with all its states, substates, transitions and conditions is quite complex. The number of possible scenarios is immense. Link training is a dynamic process. The sequence and timing of state transitions is not fixed. The sequence differs with different lane ordering different timing behavior signal integrity (occasional bit errors) violations of the standard (error scenarios) implementation specific behavior Month ##, 200X B1-20

22 LTSSM Test Challenges New Challenges for Gen 2 Speed Change! Key features: Recovery state used for speed change from Gen 1 to Gen 2 Dynamic link width negotiation now possible, allowing the link to train up or down on the fly. Specific tests available for testing the LTSSM Gen 2 is backwards compatible with Gen 1 It is possible to plug a Gen 2 device into a Gen 1 slot and the link will negotiate to the highest common value. Month ##, 200X Agilent Tools Agilent LTSSM Tester Month ##, 200X B1-21

23 Tracing LTSSM Changes Link upconfigure Before the downconfigure, a x4 link After the downconfigure, a x1 link Month ##, 200X Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Month ##, 200X B1-22

24 AER Test Challenges Link & Transaction Layer Advanced Testing Large number of features/capabilities mandated by specification Each requirement has many branches and many actions Example : Advanced Error Reporting Time consuming to create these test cases, and also time consuming to troubleshoot and validate results Month ##, 200X AER Test Challenges Advanced Error Reporting (AER) Validation of all the different branches is required : Need to initialize the devices Need to create different types of errors, using exerciser test tool Need to check that the device under test (DUT) sets all the right bits in the right registers Need to make sure the right messages are sent with protocol analyzer Month ##, 200X B1-23

25 Agilent Tools Example AER Test Case 1. Each test case walks through one of the branches in the requirements table/diagram 2. Sets up the initial required conditions 3. Creates the error 4. Validates the device being tested reacts with the right behavior Part of the Compliance Assured Test Package Month ##, 200X Agilent Tools PTC II (E2969B) Compliance Assured Test Package (N5309A-COM) PTC II (E2969B) March 24, Agilent Technologies Inc. today announced that its Protocol Test Card (PTC) 2.0 has been approved by the PCI-SIG(r) (PCI Special Interest Group) for PCI Express(r) (PCIe(r)) 2.0 protocol testing. Includes all add-in card tests from the Gen1 PTC (22 tests) The Agilent PTC II will enable device compliance with the PCI- SIG by providing 13 mandatory test cases. Upgradable to X1 exerciser in the future Compliance Assured Test Package (N5309A-COM) Compliance Assured Test Package (N5309A-COM), is available and adds an additional 180 recommended tests. The Compliance Assured Test Package includes transaction layer, link layer, electrical layer and configuration space tests. Month ##, 200X B1-24

26 Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Month ##, 200X Introduction What is Power Management Power savings by going into low power states State Description Recovery Time L0 Fully Active N/A L0s Standby ns L1 L2 L3 Low Power Standby Low Power Sleep Off (zero power) us ms ms Month ##, 200X B1-25

27 Test Challenges Power Management (ASPM) Testing Drivers : Windows Vista supports the low power states for medium power saving and high power saving modes Cost savings in terms of power consumption, heating/cooling in datacenters Drive towards green devices Challenges : Many devices have problems going in and out of the electrical idle states L0s and L1 The link is technically still active in these cases even although it is in Electrical idle Getting devices into these low power states on demand, and waking them up on demand Month ##, 200X Agilent Tools Power Management Testing Exerciser L0s support; ensure one direction only goes into L0s L1 support Trigger other device to enter into L1 state Month ##, 200X B1-26

28 Agilent Tools Power Management Testing Analyzer PM packet decodes Fast sync times to track devices going into and out of PM states Month ##, 200X Agenda Introduction Compliance Testing Physical Layer Compliance Testing Protocol Layer Compliance Testing : Agilent PTC 2.0 Advanced Protocol Test Topics LTSSM Validation Link & Transaction Layer Advanced Testing Power Management Testing IO Virtualization Month ##, 200X B1-27

29 New Specs - IOV What is I/O Virtualization I/O Virtualization (IOV) The capability for a single physical I/O unit [e.g. NIC card] to be shared by more than one system image (SI). SR-IOV : Single Root IOV MR-IOV : Multi Root IOV Standards are an overlap, however, application drivers for SR-IOV and MR-IOV are very different Month ##, 200X 2.0 Changes - IOV SR-IOV Drivers Better server utilization through : Software virtual machines on one physical server ; VMWare, Parallels, etc I/O end points does not need to know about virtualization Challenges of current technology Requires software/firmware intermediary The intermediary is involved in all transactions; configuration, I/O transfers, which lowers the performance Month ##, 200X B1-28

30 2.0 Changes - IOV MR-IOV Drivers Current blade server Server Server. Server Enet FC Enet FC Enet FC FC Switch FC Switch Enet Switch Enet Switch I/O consolidated blade server Server Server. Server RC RC RC PCIe Switch PCIe Switch FCoE FCoE Cost reduction I/O Purchase cost :each blade server goes from 28 NIC cards and 4 switches to 4 NIC cards and 2 switches Cost of power and cooling to the data center IO Consolidation : Moving from multiple technologies to single -> Ethernet & FC to FCoE Month ##, 200X Agilent Tools MR-IOV on Protocol Analyzer MR-IOV fields decoded for easy analysis Month ##, 200X B1-29

31 The Agilent E2960B Series for PCI Express 2.0 Unique In The Industry API Automation Exerciser LTSSM x16 X16 Device Emulation & Error Insertion Compliance Assured Test Package spec checklist tests PTCII Approved by PCI-SIG Probing Midbus 2.0 x16 Interposer x16 Flying Lead 2.0 x16 One Analyzer Two Use Models Logic Analysis Solution FSB Memory Bus General Purpose Extended P2L gateway Lane Analyzer Protocol Analyzer Per-lane display Packet & transaction views 8B/10B decode Easy flow technology Triggering on ordered set Advanced Triggering Power Management New standards support; IOV, Link upconfigure, etc Agilent PCI Express 1.0 & 2.0 Solution Protocol Analysis Solution Fibre Channel PCI Express ASI The Digital Application Month ##, 200X For further information You will find more information on PCI Express 2.0 and Agilent solutions for PCI Express at: PCI-SIG Website, Specification, S/W Tools, Agilent Test Procedure Agilent Protocol Test Card 2.0 (PTCII) for Protocol Compliance Testing. Agilent tools to help you succeed with your PCI Express design such as the N5393A Compliance application. Agilent PCI Express 2.0 Protocol Test Solutions Agilent tools to help you master signal integrity challenges Month ##, 200X B1-30

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34 Characterizing Your PLL-based Designs To Manager System Jitter Agilent Technologies Francis Liu Senior Project Manager Jul. 8 th, 10 th, 2008 Page 1 Outline A review of digital communications system receiver architectures The important role of Phase locked Loops (PLL) and how they impact jitter performance Characterizing performance (emphasis on PLL s) B2-1

35 Digital receivers need a clock to control the time when the decision is made on each incoming bit Data Input Decision Circuit Data Output Clock Input Where does the receiver clock come from? Clock embedded in the data stream Clock distributed as a lower rate reference clock Transmitter clock sent directly to the receiver A Phase-locked Loop is often used to create the receiver clock B2-2

36 Clock Multiplier PLL converts a Reference Clock to a full-rate System Clock for the Receiver Reference Clock Input Phase Detector VCO Full rate clock used at either the transmitter or the receiver Frequency Divider N Receiver PLL can derive a clock from the incoming data stream Data Input D-Flip Flop Data Output Phase Detector VCO B2-3

37 What is the behavior of the PLL when the input signal has jitter? Closed loop gain in out A( s) 1 A( s) G( s) G( s) e j ( s) Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock VCO can track the jitter of the incoming signal Closed loop gain in out A( s) 1 A( s) G( s) G( s) e j ( s) Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock The phase detector effectively extracts the jitter from the input data and tunes the VCO allowing it to track the jittered input B2-4

38 Jitter tracking is frequency dependent Closed loop gain in out A( s) 1 A( s) G( s) G( s) e j ( s) Data Input Phase Detector Phase Error Amplifier Voltage Controlled Oscillator (VCO) Recovered Clock Loop gain A(s) is frequency dependent and generally is large at low frequencies (closed loop gain ~1) and diminishes at high frequencies (closed loop gain approaches 0) Low frequency jitter is transferred to the clock output and high frequency jitter is not PLL Jitter Transfer Function (JTF) indicates how the jitter on the recovered clock tracks the jitter of the input Closed loop out gain in A( s) 1 A( s) G( s) G( s) e j ( s) Loop Response and OJTF Jitter Multiplier E E E+3 1.0E E E+6 Frequency (Hz) B2-5

39 What impact does the JTF have on a receiver and its ability to tolerate jitter? Data Input Decision Circuit Data Output Clock Input Allowing jitter to transfer from the data to the receiver clock can be a good thing. This allows the decision circuit to track the jittered data and still make decisions in the center of the bit period What is the effective jitter from the perspective of the receiver decision circuit? Jitter Multiplier Loop Response and OJTF E E E+3 1.0E E E+6 Frequency (Hz) As the jitter frequency increases, jitter transferred to the recovered clock rolls off Jitter tracking at the decision circuit is reduced B2-6

40 From the receiver s perspective, the PLL performs a jitter high-pass Jitter Multiplier OJTF 1-G( s) 1 G( s) e j ( s) Loop Response and OJTF E E E+3 1.0E E E+6 Frequency (Hz) All the higher frequency jitter on the data stream is observed at the decision circuit Jitter observed at the decision circuit is effectively the complement of the PLL jitter transfer function The receiver Observed Jitter Transfer Function (OJTF) effectively acts like a jitter high-pass filter To take advantage of the PLL jitter filtering properties, it is useful to observe jitter in the frequency domain Magnitude Frequency Offset frequency B2-7

41 E5052B (SSA : Signal Source Analyzer) provides a wide variety of clock oscillator measurements including the phase noise/jitter spectrum Component Evaluation Reference Source Phase Noise VCO Phase Noise AM Noise Tuning Sensitivity Oscillator/PLL Circuit Design Loop Filter (PLL Response) Phase Noise RF Transient Spurs Harmonics Verification/Test at Operating Conditions Microphonic Phase-hits Using the hardware clock recovery system of the 86100C DCAj wide-bandwidth sampling oscilloscope ADC Data or Clock Input Phase Detector VCO Similar to PLL s discussed earlier, the output of the phase detector is effectively the demodulated jitter of the input. Monitoring this signal with an analog-to-digital converter and transforming the results into the frequency domain provides the jitter spectrum B2-8

42 Spectral lines indicate periodic jitter elements Jitter Spectrum SSC and its odd harmonics 1E-6 100E-9 10E-9 Seconds (rms) 1E-9 100E E-12 1 MHz PJ (and harmonics) 1E E E khz 1 MHz 1E-15 1E+3 10E+3 100E+3 1E+6 10E+6 100E+6 Delta Frequency (Hz) Jitter Spectrum / Phase Noise Application Rev 0.5 Jitter magnitude in seconds rms versus jitter frequency in Hz (log-log scale) The floor of the signal (without tones) is effectively the spectrum of the random jitter Jitter Spectrum 1E-6 100E-9 10E-9 1E-9 Seconds (rms) 100E E-12 1E E E-15 1E-15 1E+3 10E+3 100E+3 1E+6 10E+6 100E+6 Delta Frequency (Hz) Jitter Spectrum / Phase Noise Application Rev 0.5 B2-9

43 Measuring the Jitter Transfer (and Observed Jitter Transfer) Functions Jitter transfer definition: The amount of jitter at the output of a device compared to the jitter that was on the input of the device Provide a jittered signal at the DUT input and measure the jitter at the output Pattern Generator Data D.U.T Frequency Synthesizer (Clock) Clock (for calibration) Sinusoid Generator (Jitter modulation) Jitter receiver (clock recovery) B2-10

44 Stimulus: N4903 JBERT (jittered clock or data) Alternate: Any PG or source that can be modulated with a function generator (81134, 81142A etc.) Stimulus: N5182A MXG (jittered clock) B2-11

45 Response receiver: 86100C DCAj with or 83496B Examples of device types Clock recovery circuit Clock multiplier circuit Transmitter with ref. clock Repeater circuit B2-12

46 Measurement result examples 10 Jitter Transfer Function Bandwidth =3.54E+6 Hz Peaking =0.20 db Magnitude (db) E+3 1E+6 10E+6 100E+6 Frequency (Hz) System software/control: 86100C Jitter Spectrum and Phase Noise Application Rev 2.0 Spreadsheet application controls both stimulus and response Performs calibrations and displays results Free download at agilent.com 86100C web page (Rev 2.0 available May 2008) (Also provides jitter spectrum results) B2-13

47 Increasing JTF measurement accuracy What are the main sources of inaccuracy? Jitter source flatness and repeatability Jitter receiver flatness and repeatability Measurement calibration removes source and receiver unflatness Since the source and receiver are used in both the input and the output measurements, the system unflatness can be determined with a through calibration Calibration measurement response DUT measurement response Jitter transfer= Jitter output/jitter input =(Jitter source)(cables)(jitter receiver) =(Jitter source)(cables)(dut jitter output response)( jitter receiver) =DUT measurement/cal measurement B2-14

48 Calibration when input and output rates do not match If the input to the DUT is at one rate, and the output is another (e.g. clock multiplier) how can a valid calibration be performed? Example: PCI-Express 5 Gb/s transmitter with a 100 MHz reference clock input Jitter receiver needs to observe 2 rates, possible source of measurement uncertainty Solution: Set receiver at 5 Gb/s. Create 100 MHz reference clock with 25 1 s and 25 0 s pattern from BERT What if DUT jitter conflicts with jitter stimulus? If DUT has a significant periodic jitter tone at one of the stimulus frequencies, jitter transfer result could be distorted Solution: 86100C jitter receiver can observe the DUT un-stimulated jitter spectrum and has the opportunity to adjust stimulus frequencies to avoid a collision B2-15

49 Putting the puzzle together Knowing both the jitter spectrum and the jitter transfer allows a system level analysis of how jitter is propagating and being controlled in a communications system The jitter spectrum (left) combined with the JTF/OJTF results with the jitter spectrum as seen by the receiver (right). PLL OJTF performs a jitter high-pass Low-jitter components contribute to overall jitter budget, but can be difficult to measure Examples: VCO and/or divider circuits in PLL s Residual jitter of the oscilloscope can be larger than the jitter of the DUT B2-16

50 New capabilities for analyzing very low jitter circuit elements (clock or data) Residual jitter of sampling scopes hit ~200 fs in 2002 (Agilent Precision Timebase) When precision timebase is integrated with sampling channels and the HW clock recovery system, scope jitter floor is below 60 fs Allows ultra-low jitter measurements of precision devices 86108A Precision Waveform Analyzer: A gold standard for waveform analysis New plug-in module for the 86100C DCAj 2 CH at >33 GHz Low noise, ultra-low jitter Precision waveform measurements Integrated clock recovery for single connection measurement (no trigger required) Jitter transfer/spectrum ~0 trigger to sample delay allows accurate analysis in the presence of SSC B2-17

51 Conclusions PLL s provide opportunities to manage jitter in high-speed serial bus communications Combining knowledge of the jitter spectrum and the jitter transfer/observed jitter transfer can lead to optimal designs Test systems available to provide accurate analysis FAQs Q1 : Is the PLL filtering out the jitter, or enhancing the jitter? Q2 : How does the CDR remove the high frequency jitter Q3 : What is the best way to quantify RJ, like PJ, which should be unbounded? Sorry if I am saying that wrong. Q4 : Could you provide a bit more insight into how exactly the jitter transfer measurement is done? How are the points on the curve calculated? B2-18

52 Extending Agilent Infiniium Oscilloscopes using MATLAB Software ~ MATLAB Integration and More ~ Agilent Technologies Roger Lo Application Program Manager Jul, 8 th,10 th, 2008 Page 1 Agilent at a Glance $5.0 billion annual revenue 19,000 employees Customers in 110+ countries 60+ year heritage of invention and innovation Page 2 B3-1

53 MATLAB A well respected software environment and technical computing language Over 1,000,000 users world-wide in many industries 2-D and 3-D data analysis and visualization environment The de facto industry-standard high-level programming language for algorithm development Toolboxes for data acquisition and instrument control Toolboxes for signal processing, filter design, statistics, optimization, symbolic math, and other areas Page 3 Reasons MATLAB is Used with Agilent Instruments 1. Analyze measurements acquired by oscilloscopes 2. Develop GUI-based or command-based applications 3. Develop interactive or automated test systems 4. Automatically generate reports to share results Page 4 B3-2

54 Agenda Market Trends and Demands Solution Part 1: Integrating MATLAB Analysis Power Using An Infiniium User-Defined Function Solution Part 2: High Speed Digital Signal Measurements: How Can We Help You? A Glance at Agilent Product Offerings Summary Page 5 Market Trends & Market Demands The parallels are moving to serial buses. No doubt, signal rates are increasing rapidly! USB 2.0 (480Mbps) Serial ATA I (1.5Gbps) PCI Express Gen I (2.5Gbps) HDMI 1.3 (up to 3.4Gbps) Serial ATA II & III (3 & 6Gbps) PCI Express Gen II (5Gbps) And so on. More standards are adopting the embedded clock. Designing, prototyping, and testing systems has become increasingly complex. Page 6 B3-3

55 Market Trends & Market Demands (Continues) Too many new and hot standards. I cannot learn all details on all compliance stuff! Different application standards have different speeds. Would I need different bandwidth tools for each, or the widest one works for all? Okay, pre-emphasis is one of the solution for ISI and evaluate (for PCI Express, at least). What about a tool to evaluate and emulate the equalizations? My bus is a proprietary one. Sorry, I cannot disclose the info, so you need to provide me the tool to create my own solution. There s a lot more specific & special measurements and analysis I want to perform, way beyond the standard features provided by the T&M vendors. Help! Page 7 A Question to Begin with: Question 1: Why is there a difference in two eye patterns? Both signals are probed at the Rx end of a transmission line thru SMA connection. Hint: Only one signal is actually probed. One seems to have less ISI effect than the other Tx Rx Page 8 B3-4

56 Answer to Q1: For Example, How About a Signal Equalization Solution to Start Out With? An Experiment with PCI Express 2.5Gbps signal with a compliance pattern (no emphasis control) Tx ISI emulator using 4m BNC cable Rx Tx Eye Pattern created using software clock data recovery available in Infiniium oscilloscope Page 9 Rx Eye Pattern created using software clock data recovery. Large effect of ISI observed. De-embedding Loss Compensation or Gain Function Compensate for Probing and Fixture Loss Add Margin to Transmitter Characterization PCI Express 2, SATA, and Custom Compliance Requirement for Gen 2 Tx PHY Channel Rx PHY Page 10 Page 10 B3-5

57 Using UDF with de-embed functions: choosing your function Measure channel frequency response with VNA or TDR and import result to oscilloscope VNA sparameter file is most accurate but TDR response is easiest to obtain Page 11 Signal Equalization Through 5 Tap FIR Filter to Simulate HW Equalizer Embedded in Rx Chip An Experiment with PCI Express 2.5Gbps signal with a compliance pattern (no emphasis control) Tx ISI emulator using 4m BNC cable Rx Page 12 Clearly, a wider eye opening is observed after the equalization filter. B3-6

58 A Quick Jitter Comparison via Histogram Measurement Raw Signal with ISI Raw Signal with ISI Equalized Eye Pattern Equalized Eye Pattern A Clear Jitter Reduction Achieved. But which components? Page 13 So, This Equalization Function Feature Must Require a Huge Programming Effort, Isn t it? Actually, only two simple files are needed for Infiniium User-Defined Function (UDF) to work. XML Function Descriptor MATLAB script (M-File) UDF talks a full advantage of powerful MATLAB pre-defined functions! Let s take a look at actual programming! Page 14 B3-7

59 XML Function Descriptor for FIR (5 Tap EQ) User-Defined Function Page 15 M-File for FIR (5 Tap EQ) User-Defined Function Only 30+ line programming and you have the FIR equalization filter! Page 16 B3-8

60 Powerful MATLAB Functions and Features in Signal Processing Toolkit Enabled Below UDF Examples Butterworth Low Pass Filter FIR (Finite Impulse Response, 5 Tap EQ) LFE (Linear Feedforward Equalization) RTEye (Plot a real time eye in MATLAB) SqrtSumOfSquares Convolution Correlation Exponential Gate (amplitude level gating) Log Max of 2 Sources Threshold Time Reverse (reversing the time tag info) Page 17 XML file and M-File for the RTEye Example Page 18 B3-9

61 XML file and M-File for the Butterworth Example Page 19 Agilent Infiniium User-Defined Function Integration MATLAB Analysis Power For On-Demand Solutions Agilent and The MathWorks teamed up to deliver a brand new customer solution development environment using Infiniium oscilloscope from Agilent and MATLAB from The MathWorks to address customer s critical needs. Several example files are provided including FIR equalization. No need to share your company secret any more. You can develop special solution to meet your specific requirement. Page 20 B3-10

62 User-Defined Function Data Types Overview of available data types: 1 Source 2 Source Clock Data Sampled Clock Data Description of input/output parameters Page 21 Data Type: 1 Source FunctionType: 1 Source SourceType: Channel, Function, Memory, Bus Used for: Generic User-Defined Function, Filtering, Chart timing Inputs: SrcXInc, SrcXFirst, SrcYScale, SrcYMiddle, SrcData Outputs: FnXInc, FnXFirst, FnYScale, FnYMiddle, FnData Page 22 B3-11

63 Data Type: 2 Source FunctionType: 2 Source SourceType: Channel, Function, Memory Used for: Generic User-Defined Function, SQRT sum of squares Inputs: Src1YScale, Src1YMiddle, Src1Data, Src2YScale, Src2YMiddle, Src2Data Outputs: FnYScale, FnYMiddle, FnData Page 23 Data Type: Clock Data Page 24 FunctionType: Clock Data SourceType: Channel, Function, Memory Used for: RTEye, high speed serial decode Inputs: SrcXInc, SrcXFirst, SrcYScale, SrcYMiddle, SrcData, ClockData Outputs: FnXInc, FnXFirst, FnYScale, FnYMiddle, FnData B3-12

64 Data Type: Sampled Clock Data FunctionType: Sampled Clock Data SourceType Channel, Function, Memory, Bus Used for: High speed serial decode, Chart state Inputs: SrcYScale, SrcYMiddle, SrcData, ClockData Outputs: FnYScale, FnYMiddle, FnData Page 25 Input Variables SrcXInc: : The time difference of two adjacent samples of SrcData.. (1/Sample Rate) SrcXFirst: : The time of the first value of SrcData. SrcYScale: : The potential full scale voltage range of the source waveform. SrcYMiddle: : The voltage at the center of the voltage range for the source waveform. SrcData[]: The input waveform. Values are typically in volts. ClockData[]: The locations in time of the clocks. Control1: The current value of the user defined control 1 in the e user interface. Control2: The current value of the user defined control 2 in the e user interface. Reset: This variable will have the value 1 when the source waveform's scale has changed or if clear display has been pressed. Page 26 B3-13

65 Output Variables FnXInc: The time difference of two adjacent samples of FnData. (1/Sample Rate) FnXFirst: The time of the first value of FnData. FnYScale: The potential full scale voltage range of the function waveform. FnYMiddle: The voltage at the center of the voltage range for the function waveform. FnData[]: The output waveform. Page 27 Agenda Market Trends and Demands Solution Part 1: Integrating MATLAB Analysis Power Using A New Infiniium User-Defined Function Solution Part 2: High Speed Digital Signal Measurements: How Can We Help You? A Glance at Agilent Product Offerings Summary Page 28 B3-14

66 Question 2: Eye Patterns from the SAME device. Why is there a difference? Device Under Test: USB2.0 Hi-Speed (480Mbps) Hub (Downstream port) The same DUT but I see some noise differences in the measurement.. Why? Page 29 Question 3: Is this a PCI Express Compliance Pattern? Which One Is the Correct One? I don t want count 0s and 1s. Any great tool? PCI Express Compliance Pattern Page 30 B3-15

67 Question 4: The Eye Pattern Failed in the Mask Test! What s Would You Do Next? Better start working on my signal integrity Page 31 Question 5: A LVDS/T.M.D.S. Signal Too Many Eye Patterns per Clock. How Would You Analyze Your Eye Patterns? No point of investigating each eye pattern individually. What should I do? Page 32 B3-16

68 Agenda Market Trends and Demands Solution Part 1: Integrating MATLAB Analysis Power Using A New Infiniium User-Defined Function Solution Part 2: High Speed Digital Signal Measurements: How Can We Help You? A Glance at Agilent Product Offerings Summary Page 33 High Speed Digital Measurement and Analysis Systems: Advance Features Help Your Trouble Shooting Faster Key Questions/Demands Addressing Here: Features addressing the scope bandwidth vs. noise floor concerns All the different application standards have different speeds. Would I need different bandwidth tools for each application? Actually too many new and hot standards. I cannot learn all details on compliance stuff! Features making 8b10b coded bus trouble shoot easier. Features help you when you encounter mask pattern violations Advanced serial data analysis / clock data recovery features addressing new needs for evaluating embedded clock standards. Page 34 B3-17

69 Answer to Q2: Will it help to have as much bandwidth as possible for the BEST measurements? The Answer The top waveform is USB2.0 eye pattern measured with 3GHz bandwidth scope Page 35 The bottom waveform is measured with 12GHz bandwidth scope Noisy part of the waveform is the high frequency noise from the scope front end, not from DUT Too much bandwidth will only increase the noise Measured with 3GHz Scope Measured with 12GHz Scope Answer to Q2: More Bandwidth Is Better? (continues) Page 36 FFT analysis revealed more info. Select an adequate bandwidth for each application to avoid unnecessary noise. So, you need different bandwidth scopes for each application? B3-18

70 Measurement Stability Comparison: 480Mbps (240MHz) USB2.0 Hi-Speed 0101 Data Pattern DSA90804A 8GHz Scope DSA90804A With 2GHz BW Reduction Feature Page 37 Having a lower noise floor and using an adequate bandwidth for the specific application really improves measurement stability and repeatability Agilent 500 Digital ps Transition Measurement Time Forum Converter Utilities Compliance Analysis Jitter Popular Application Software Packages (29 total) Software Applications Comments E2681A EZJIT Jitter Analysis Measurements, histograms, measurement trending, jitter spectrum N5400A EZJIT Plus Jitter Analysis Dj/Rj jitter separations and bit error rate projections. E2690B M1 Oscilloscope Tools Most advanced and flexible jitter analysis package. (Third Party: Amherst Systems) E2688A SDA Serial Data Analysis Multiple clock recovery modes, mask testing, real-time eyes, 8b/10b decode & trigger N5414A InfiniiScan Event ID (HOT!) Event identification software trigger: glitch, serial, zones, measurement limits, etc A Vector Signal Analysis Ultra-wide-band, multi-port vector signal analysis. N5391A Low Speed SDA Decode, search & trigger on I2C and SPI low speed serial bus protocols N5402A Automotive Serial Analysis (NEW) Decode, search & trigger on CAN and FlexRay serial bus protocol. N5416A USB Compliance USB2.0 LS/FS/HS and OTG compliance N5392A Ethernet Compliance Compliance solution for 10BaseT, 100BaseT, and 1000BaseT (Gigabit Ether). Fire-Wire Compliance FireWire IEEE1394 compliance solution from 3 rd party partner. N5394A DVI Compliance DVI compliance solution (available only for Infiniium DSO/DSA80000 series) N5399A HDMI Compliance First HMDI 1.3 solution in the world, listed in CTS1.3b. U7232A DisplayPort Compliance (NEW) Industry s first DisplayPort compliance app solution N5393A PCI Express Compliance Test selection, configuration, connection, execution, results. (SDA Req.). N5413A DDR2 Full Compliance Industry s only DDR2 full compliance software U7231A DDR3 Full Compliance (NEW) Industry s only DDR3 full compliance software U7233A DDR1 Full Compliance (NEW) Industry s only DDR1 full compliance software N5409A Fully Buffered DIMM Wizard based test framework as above (SDA & EZJIT Plus Required) N5410A Fiber Channel Comp. Wizard based test framework as above (SDA & EZJIT Plus Required) N5411A Serial ATA Compliance Wizard based test framework as above (SDA & EZJIT Plus Required) N5412A SAS Compliance Wizard based test framework as above (SDA & EZJIT Plus Required) N5431A XAUI Compliance (NEW) Industry s first wizard based test framework for XAUI and XAUI-based standards N5430A User Defined Function (NEW) Seamless linkage to MATLAB to support custom, on-demand function development N5403A Noise Reduction and BW Control DSP noise reduction capability E2625A Comms Mask Test Kit Low speed electrical mask testing for ANSI and ITU standards E2699A My Infiniium Customize Infiniium user interface to launch 3 rd party executables N5435A Infiniium App Server License (NEW) Industry s first server based scope app solution, providing max investment protection N5452A Infiniium App Remote Program Interface Enable Infiniium compliance app remote programming. Available in spring 2008 (estimate) The Infiniium software suite currently offers 29 (and more in near future) powerful packages to match the scope and probing system to the target application. Page 38 B3-19

71 Answer to Q3: Which one is PCI Express Compliance Pattern? Page 39 8b10b decode feature makes trouble shooting much faster. Serial Data Analysis Solutions (E2688A): 8b10b Trigger, Decode, Search and Listing Feature PCI Express Compliance Pattern Page 40 No need to count 1 and 0s any more! B3-20

72 Serial Data Analysis Solutions (E2688A): 8b10b Trigger, Decode, Search and Listing Feature SW Trigger with K28.5 SW Sequential Trigger w/ K28.5 => D10.2 Page 41 Answer to Q4: Let s Start the Trouble Shooting from the Mask Unfold Feature (E2688A)! Click!! Page 42 B3-21

73 Serial Data Analysis Solutions (E2688A): Mask Unfold Feature Navigation icons for scrolling through each failure Quick guidance on # of failure and failure index. Page 43 Serial Data Analysis Solutions (E2688A): Mask Unfold Feature + 8b10b Decode to Find More! Page 44 Identified and isolated that 5 th mask violation was the first bit of D12.0 (-) B3-22

74 Answer to Q5: Use the Explicit Clock Recovery Technique to Evaluate Every Eye Instead of Only the Worst Bit (Eye) Page 45 SerDes Structure - T.M.D.S. Link / LVDS Display Link 10bit Tx In Encoder 10:1 (T.M.D.S.) 10:1 7:1 (LVDS) Tx Out TData / Data Rx In 1:10 (T.M.D.S.) 1:10 1:7 (LVDS) Decoder Rx Out 10bit TClock / Clock? CRU /? Up to silicon/chip vendor. Usually vendor s know how works here. CRU for T.M.D.S., Up to silicon vendor for LVDS. CRU Clock Recovery Unit Page 46 B3-23

75 Data Clock to Data Relationship Clock Page 47 Eye Pattern and Jitter on T.M.D.S. / LVDS Clock to Data Relationship Ends Up with 10 Unique Eye Patterns Data x Clock No one eye pattern represents true eye pattern (signal quality) of all data patterns. Page 48 B3-24

76 Traditional Way Finding the Worst Eye: Bit Specification Method Magnify the worst bit Which one is the worst bit? Evaluate through the histogram? Page 49 Finally, run the mask test on the worst bit This method assumes if the worst bit of all 10 eye pattern does not violate the mask, there will be no error in the system, as this cannot qualify all data. Composite Eye: A Solution with The Explicit Clock Feature Multiply The Clock Frequency and Create Virtual Edges explicit X10(each pixel clock) Fold every bits Page 50 Now, you can evaluate every eye pattern for a fast and the most accurate data signal quality measurement B3-25

77 Resulting Eye Pattern Using Explicit Clock An example for T.M.D.S. based technology (DVI / HDMI) An example for LVDS based technology Page 51 When a clock multiplier does not match up the specification, no eye pattern is created. Page 52 Agenda Some Questions to Begin With Market Trends and Demands Solution Part 1: Integrating MATLAB Analysis Power Using A New Infiniium User-Defined Function Solution Part 2: High Speed Digital Signal Measurements: How Can We Help You? A Glance at Agilent Product Offerings Summary B3-26

78 Superior Signal Integrity Waveform Measurement System Infiniium DSO/DSA90000A Series Real Time Oscilloscope Industry s s lowest noise/ jitter floor GHz Bandwidth Superior trigger jitter at < 500fs Bandwidth upgradeable line up 256 level intensity graded touch screen display > 23 application packages Agilent: The Total High Speed Digital Solution Partner Signal Integrity Starts from the Probing Tip!! InfiniiMax I & II Soft Touch Pro E540xA World s s widest system bandwidth = 13GHz The Newest Lineup from the Agilent, Impedance and Jitter Analysis are the One probe, two rolls (differential & single end) the Logic Analyzer Authority Essential for High Speed Digital Support various probe heads Connector-less probing with Soft Touch Pro 16800/16900 Logic Analyzer System Infiniium DCAj 86100C 3 or 6 slots of Sampling Oscilloscope measurement module Max Bandwidth = 80GHz Max 1.5Gbps state / Supports InfiniiMax 4GHz timing analysis probing using N1022A Industry s s only FPGA Automatic Dj and Rj dynamic probing separation and Tj calculations Supports PCI Express, SATA measurements. S-parameter analysis with TDR feature opt 202 Ultimate Board Characterization Solution for TDR/Network Analyzer N1900B series Physical Layer Test System Signal integrity analysis with TDT/TDR and freq domain. Characterization for different modes; SE, diff, common mode, High accuracy analysis with wide dynamic range Ideal Stimulus Testing with Pulse Pattern Generator / BERT 811xxA series PPG & N490xA/B SerBERT/J-BERT 3.3GHz, best match PPG for high speed digital testing with ultra low residual jitter. Industry s s only calibrated jitter generation solution with controllable ISI, DCD, Rj, and Pj injection. Page 53 Agilent Realtime Oscilloscope Family Line-up Agilent Oscilloscope Innovations! High-Bandwidth Sampling High-Performance Lab Infiniium DCA-J Series U1600A Series - Source: Prime Data Sept. 10, 2007 High-Performance Portable General-Purpose Portable Economy Handheld DSO 3000 Series DSO 5000 InfiniiVision Series General-Purpose Lab High-Performance Portable MSO/DSO InfiniiVision 6000 Series MSO/DSO InfiniiVision 7000 Series UDF Ready Infiniium 8000 Series Infiniium Series Page 54 B3-27

79 Summary Needs from High Speed Digital design market is changing rapidly More customization, customer specific features More features to address serial bus standards Together with MATLAB, Agilent Infiniium User-Defined Function opens a new opportunity for developing custom solutions, ondemand. Agilent is committed to provide solutions addressing specific needs for the High Speed Digital and Digi/RF community. Agilent and MATLAB are the Total High Speed Digital Solution Partner Thank you for your attendance!! Page 55 For More Information Download the Technical Data Sheet N5430A Infiniium User-Defined Function using MATLAB : EN.pdf Visit the Agilent resource page on MathWorks.com: Page 56 B3-28

80 Product Information Infiniium DSO90000A 2.5GHz 13GHz, 40GSa/s Oscilloscope N5430A Infiniium User-Defined Function A 7.0GHz Serial Pattern Generator Page 57 B3-29

81 B3-30

82 Memory testing from DDR1/2/3 to XDR Agilent Technologies Ryan Lu Project Manager Jul, 8 th,10 th, 2008 Page 1 Page 1 : How to Solve DDR Parametric/Protocol Measurement Challenges and XDR Parametric Issues Page 2 B4-1

83 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 3 DDR Memory Technology Everywhere Embedded Designs for HDTV, printers, phones, projectors, cars, base stations, etc. SO-DIMM (Small Outline Dual In-line Memory Module) for Mobile PC FPGA Design DDR DRAM DIMM (Dual In-line Memory Module) for Regular PC Page 4 B4-2

84 Comparison for DDR 1, 2, 3 Specification DDR1 DDR2 DDR3 Operating Voltage V 1.8 V 1.5 V Clock Frequency MHz MHz MHz Data Transfer Rate MT/s MT/s MT/s Pin Count Package TSOP/BGA BGA BGA Backward Compatibility No No No Page 5 DDR Nomenclature as defined by JEDEC DDR SDRAM Chip Specification (for Embedded) D D R DDR Technology Designation DDR Technology Generation Data Transfer Rate (MT/s) Clock Rate is ½ Data Transfer Rate = 800 MHz DDR DIMM Specification (for Computer) P C DDR used in PC Designation DDR Technology Generation Memory Bandwidth (MB/s) Data Rate (1600) x 8 = 12,800 MB/s Page 6 B4-3

85 Impact on Design and Validation Clock Speeds reaching 1GHz Parallel buses reaching the speeds of serial technology Tighter timing margins require calibration and bus training for DRAM, controller, and analyzer capture Crosstalk, impedance, EMI, and jitter issues Noise susceptibility Probe load effects are critical I m becoming a microwave designer! Memory Speed Roadmap SDR 100 MT/s DDR 400 MT/s 2000 DDR2 800 MT/s 2002 DDR3 1.6 GT/s 2005 DDR4 3.2 GT/s Benefits of good signal integrity Guarantees interoperability with different vendors Improved device performance More design margin Page 7 Page 7 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 8 B4-4

86 Probing Requirement Memory Controller DRAM Ideal Probing Points DRAM Ballout DIMM PCB trace DIMM Connector JEDEC defines the DDR spec at the DRAM ballout. To fully comply with the specification, probing is recommended to be made at the DRAM ballout for most accurate results. Page 9 Probing Challenges Where to probe? If probing at the BGA signals is not difficult enough, new design with higher density and limited board space post an even bigger challenge. Designing special probe points or vias on the board is no longer an option. Page 10 B4-5

87 Alternative Probing Options and Issues for Oscilloscope Probing at the center of the trace DRAM Memory Controller Many engineers will find other alternative points to probe at the DDR signals. One example above is probing at the transmission line. However, there is a risk of signal reflection and other signal integrity issues. Page 11 Issues with Current Probing Solution on LA Complete Protocol validation with the logic analyzer requires access to all the buses. Current probing method does not address individual DRAM probing Flying leads and midbus probing methods require design-in footprints and connectors Not practical for boards with tight board space especially on an embedded system Tedious setup Page 12 B4-6

88 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 13 Ideal Probing with DDR2 and DDR3 BGA Probe Adapters DDR2 BGA Probe Adapter for Scope and Logic Analyzer DDR3 BGA Probe Adapter for Scope Key Features and Benefits: Easiest way to access your DDR signals Superior signal integrity probing for most accuracy in measurement W A (each ship with a kit of 4 probes) W A (each ship with a kit of 10 probes) Compatible with parametric and protocol measurements Page 14 B4-7

89 Key Feature 1: Easiest way to access your DDR signals No designated probe points DDR2 BGA Probe Adapter Probe Here Probe Here Where to probe? Probe Here Probe Here High density board DDR3 BGA Probe Adapter DDR2 and DDR3 BGA probe adapters provide signal access points. Page 15 Key Feature 2: Superior signal integrity probing with embedded resistors in BGA probe Probe Here DRAM Probe Here DDR2/3 BGA Probe PCB Embedded Resistors Embedded resistor provides isolation of the probe loading and the live signal. Embedded resistor isolates the probe loading effect from the signals. Page 16 B4-8

90 Key Feature 2: Superior signal integrity probing for most accuracy in measurement Sample Test Results from Key Customer on DDR3 BGA probe Customer s Quote: These attenuations of waveforms are acceptable and comprehensible. Therefore, W2635A can be used for the measurements. Without BGA Probe With BGA Probe Probing directly at the signals and BGA probes yield similar results. Page 17 Key Feature 3: Compatible with parametric and protocol measurements Waveform / Data Analysis with Logic Analyzer DDR2 and DDR3 BGA Probe Adapters InfiniiMax Probes E5384A & E5826/7A LA Cable Adapters Parametric Measurement with Infiniium Scopes Compatible with our scope and logic analyzer probes Page 18 B4-9

91 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 19 Functional Validation Challenges Signal Integrity issues create inaccurate timing and protocol measurement. We need to be able to access and analyze all the buses at the same time to obtain an overview of the bit error rate and SI issues. Accurate Read and write data capture for protocol analysis. We need to be able to sample at the correct sampling position on both read and write data valid window to enable accurate state capture. Spending a lot of time on the work bench, trying to analyze the raw command, bank address and read/write data from the captured trace. Page 20 B4-10

92 EyeScan Feature for Quick SI Check EyeScan result gives a superior and quick SI insight to all the memory buses including Address, Command, Control and Data. Page 21 Protocol Decode Tool Protocol Decode provides the following for easy memory bus analysis: Command Bank Address Column Address Read or Write Data Page 22 B4-11

93 NEW DDR3 EyeFinder SW The DDR3 EyeFinder software helps you position the sampling points for accurate read and write data capture. The software triggers on valid read and write commands with your system executing any memory test suite or stimulus program. The software will then display read and write data valid window as a result of the scan. Page 23 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 24 B4-12

94 Scope Required Bandwidth for DDR Validation Rise Time Memory App Signal Rate Fundamental Frequency Calculated Fastest Tr/Tf from JEDEC spec Real Signal Tr/Tf Optimum Bandwidth Most likely Material DDR1 DDR2 DDR3 Up to 400MT/s Up to 800MT/s Up to 1.6GT/s 200MHz 155ps (20-80%) 600 (20-80%) 600MHz - 1GHz FR4 400MHz 100ps (20-80%) 200 (20-80%) 2GHz - 4GHz FR4 800MHz 60ps (20-80%) 100 (20-80%) 4GHz - 8GHz FR4 No mention of signal rise/fall time or bandwidth specification in JEDEC DDR spec. Bandwidth requirement is a function of rise time. Rise time is a function of signal slew rate and amplitude. Using the information in spec, the fastest rise time can be calculated. Although the calculated fastest rise time looks aggressive for silicon, the real performance is much slower. This is due to the cheaper FR4 materials and connectors used in the real product design and manufacturing. The actual signal bandwidth is lower with the higher signal harmonics filtered. Page 25 Challenges That Needs to be Addressed Today Probing system response. We have the BGA probes to address signal accessibility. Is that all? Actually, the entire probing system (including the probe and scope) has effect on the measurement results. Read and write signal separation on the same bus. We need to trigger using the controls signals, but sometimes scope channels are not enough to get a stable trigger. We need to do many single acquisitions. Not productive, too much time and effort required. Engineers need to manually making measurements of the signals. The maximum measurements is limited. Too much effort to put all results into a test report. Page 26 B4-13

95 Probing System Response Magenta: SMA direct Green: Probing Performance of probing system is a combination of both scope and probe. You need the flattest probing response for full confidence in DDR measurement results. Select a probing where the signals track directly with the signals measured with SMA connection. As DDR signals are mostly single-ended, probing is a major consideration for accurate and repeatable measurement. Choose a probing solution you are confidence with. Evaluate its performance if you have to. You need to have the full confidence especially if you are validating a new design. Magnitude (db) Agilent DSA N5381A Frequency (GHz) Solder-in Magnitude (db) Company X+ Various Solder-ins Frequency (GHz) High BW 00D High BW 90D Short Solder-in Med Solder-in Long Solder-in Page 27 More InfiniiMax Probe Innovations Need temperature characterization? N5450A InfiniiMax Extreme Temperature Cable Extension Solution with Gore Cable Extension specially developed for InfiniiMax Perfect solution for the environmental chamber testing Agilent exclusive solution with 36 inches long (92cm) reach Two Different Operating Temp depending of the probe head N5381A solder-in: -55 to +150 C E2677A solder-in: -25 to +80 C Need probing with larger pitch size? N5451A InfiniiMax Long Wire ZIF Tip Wider span than standard ZIF Tip to probe signal like DDR system with larger pitch size. Need to reach to the ground point on the board. Two different wire length: 7 mm (>6GHz) and 11 mm (>4.5GHz) Page 28 B4-14

96 Use InfiniiScan to separate Read and Write signals There is no rule how to use the zones to separate the read or write signals. It depends on the silicon characteristics and DIMM loading which shows distinctive difference between the read and write signals. High Impedance State DQS read or write normal bits DQS read or write normal bits High impedance state DQS read or write preamble bit Use InfiniiScan Zone Qualify to trigger on Read and Write distinctive waveform pattern. Page 29 Read-Write Separation Step 1 A Must Not Intersect zone is drawn on the DQS waveform to discard the normal bits or idle state signals. With the Must Not Intersect zone drawn, the scope consistently tracks the preamble bits of the read and write signals. Page 30 DQ signal is tracked at the beginning of the read or write burst, but not separated yet. B4-15

97 Read-Write Separation Step 2 Drawing a Must Intersect zone at the upper pre-amble bit voltage isolates the Write separation. Compare the DQS and DQ edges. Write Separation Edges not aligned Drawing a Must Intersect zone at the lower pre-amble bit voltage isolates the Read separation. Compare the DQS and DQ edges. Read Separation Edges are aligned Read and Write separation made easy with InfiniiScan Zone Qualify Page 31 Page 32 List of JEDEC DDR3 Test Parameters Specification JESD79-3 DDR3 SDRAM Specifications Table 26 Single Ended AC and DC Input Levels (Page 103) Table 27 Differential AC and DC input levels (Page 105) Table 28 Cross Point Voltage for Differential Input Signals (CK, DQS) (Page 105) Table 31 Single Ended AC and DC Output Levels (Page 109) Table 32 Differential Output Slew Rate (Page 109) Table 34 Output Slew Rate (Single-Ended) (Page 110) Table 36 Differential Output Slew Rate (Page 111) Table 37 AC Overshoot/Undershoot Specification for Address and Control Pins (Page 113) Table 38 AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask (Page 114) Table 66 Timing Parameters by Speed Bin (Page 153) Test Parameters Vih(dc), Vil(dc), Vih(ac), Vih(dc) VIHdiff, VILdiff Vix Voh(dc), Vom(dc), Vol(dc), Voh(ac), Vol(ac) VOHdiff(ac), VOLdiff(ac) SRQse SRQdiff Maximum peak amplitude for overshoot area, Maximum peak area for undershoot area, Maximum overshoot area above VDD, Maximum undershoot area below VSS Maximum peak amplitude for overshoot area, Maximum peak area for undershoot area, Maximum overshoot area above VDDQ, Maximum undershoot area below VSSQ tck(avg), tjit(per), tjit(cc), terr(2per), terr(3per), terr(4per), terr(5per), terr(nper), terr(nper2), tch(avg), tcl(avg), tjit(duty), tac, tdqsck, tdqsq, tqh, tdqss, tdss, tdsh, thzdq, thzdqs, tlzdq, tlzdqs, twpre, twpst, trpre, trpst, tdqsh, tdqsl, tds(base), tdh(base), tis(base), tih(base) Huge list of DDR3 test parameters that have to be verified. B4-16

98 Setting Up the DDR App for Measurements - 1 Select the DDR speed grade. Selecting the tests. Configure the apps before the measurements. Page 33 Setting Up the DDR App for Measurements - 2 Making sure you have made the right connections to your device and scope. User can choose to repeat the measurements. Run the tests. Result summary page. Includes margin analysis on how close your device passes of fails the spec. Page 34 B4-17

99 Example of Automated Measurements Eye-Diagram Analysis Write Preamble Width DQ Setup Time Falling Edge Slew Rate Page 35 Automated HTML Report Generation The app automatically generates a HTML report for sharing with others or result archiving purpose. Page 36 B4-18

100 Debugging Clock Jitter Issues with EZJIT tool Analyze Jitter spectrum Find Correlation 25MHz oscillator 50MHz oscillator Power switching line Clock error trend EZJIT is a great tool to debug clock jitter issues. Analyzing the clock error spectrum, you can identify the source of the clock jitter coupled to your DDR clock signal. Comparing the low-pass filtered jitter trend with signals like power line, you can correlate the clock jitter with power switching line with EZJIT. Page 37 Agenda DDR Memory Technology Overview DDR Probing Challenges New DDR BGA Probe Adapters Solves Probing Challenges DDR Protocol Validation Challenges, and Solutions DDR Parametric Measurement Challenges, and Solutions XDR Parametric Challenges, and Solutions Questions and Answers Page 38 B4-19

101 XDR Overview XDR Technologies: ODR (octal data rate), 8 data bit per clock edge. Flex Phase, make able to adjust controller-dram skew within 2.5ps, every DQ bit independently. Point-to-Point architecture provides good signal quality. CFM (Clock) 400MHz RQ (ADD/CMD) 400Mbps DQ 4.0Gbps No DQS Higher transfer rate than DDR. No need of trace matching with Flex Phase. Easier implementation than DDR for users. Page 39 Challenges In Debugging XDR Interface Probing system response. The entire probing system You have (including seen in the the probe DDR and section scope) how has effect to select on the the measurement probe response results. for We most need to guarantee accurate good signal measurement. integrity with the XDR data transfer rate reaching 3.2Gbps. Read and write signal separation on the same bus. We need to trigger using the controls signals, but sometimes scope channels are not enough to get a stable trigger. We need to do many single acquisitions. Tools for validation and debug. We need tools to effectively validate the XDR interface if they have good signal integrity. Besides that, if there are failures, we need tools to tell the root cause. Page 40 B4-20

102 Using InfiniiScan to separate Read and Write DQ 3.2Gbps Must Not Intersect Zone Write Waveform Must Not Intersect Zone Using an edge trigger and infinite persistence, both Read and Write are captured. Read Waveform Page 41 Creating XDR Eye Pattern and Mask Testing Eye-diagram with a huge opening. A lot of margin. Eye-diagram passes the mask testing fulfilling the spec. Apply mask testing Eye-diagram is closing up. Eye-diagram failure Page 42 B4-21

103 Debugging XDR eye-diagram failure Page 43 Other Debugging Capabilities InfiniiScan tracks a glitch in the clock signal. Use EZJIT Plus to debug jitter related issue. It can break down the jitter component into RJ, PJ, DJ and others to identify the root cause of failures. InfiniiScan zone trigger is also a powerful tool to find glitches and anomalies in the high speed XDR signal. Page 44 B4-22

104 Summary New DDR and XDR technology speeds and architecture are driving new design and measurement techniques. Superior signal integrity and BGA probing technology is required for the most accurate DDR validation. Validation that would have otherwise been very difficult are made easy through new instrument capabilities Powerful triggering and signal processing Automated testing of compliance thru SW applications Protocol aware calibration and data capture Powerful debugging tools that will help you quickly and easily identify the root cause of the failures. Page 45 For Additional Information Agilent s DDR technology webpage: BGA Probe Information: A Time-Saving Method for Analyzing Signal Integrity for DDR Buses Application Note: InfiniiScan Product Info Memory Solution with Logic analyzer: Page 46 B4-23

105 Questions and Answers Page 47 Backup Information Page 48 B4-24

106 Page 49 DDR2 and DDR3 BGA Probe Model Number DDR2 BGA Probe Adapter for Logic Analyzer and Scope W2631A DDR2 x16 BGA command and data probe (4 units) W2632A DDR2 x16 BGA data probe (4 units) W2633A DDR2 x8 BGA command and data probe (4 units) W2634A DDR2 x8 BGA data probe (4 units) E5384A 46-ch single-ended ZIF probe for x8/x16 DRAM BGA probe connect to 90-pin LA cable E5876A 46-ch single-ended ZIF probe for x16 DRAM data only BGA probe connect to 90-pin LA cable E5877A 46-ch single-ended ZIF probe for 2 x8 DRAM data only BGA probe connect to 90-pin LA cable 1130/60A InfiniiMax probe amplifier N5424A/25A ZIF probe head and tips N5381A Solder-in probe head DDR3 BGA Probe Adapter for Scope W2635A-010 x8, 10 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units) W2635A-011 x8, 11 mm width DDR3 BGA probe adapter for x4 and x8 DRAM package (10 units) W2636A-010 x16, 10 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units) W2636A-011 x16, 11 mm width DDR3 BGA probe adapter for x16 DRAM package (10 units) 1130/60A InfiniiMax probe amplifier N5424A/25A ZIF probe head and tips N5381A Solder-in probe head B4-25

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