3D modeling in PCI Express Gen1 and Gen2 high speed SI simulation

Transcription

1 3D modeling in PCI Express Gen1 and Gen2 high speed SI simulation Runjing Zhou Inner Mongolia University E mail: auzhourj@163.com Jinsong Hu Cadence Design Systems E mail: jshu@cadence.com 17th IEEE Workshop on Signal and Power Integrity May, 2013 Paris, France

2 Agenda 1. Introduction 2. Freq domain modeling with 3DFEM solver 3. Time domain simulation with Hspice 4. Add in card compliance measurement 5. Summary and conclusions 6. Reference 2

3 High speed Serial Interface Data Rate Increasing Rapidly 3

4 Stratix IV GX FPGA Development Board 40nm FPGA support PCIe Gen1/2, DDR3, HDMI, LVDS, USB2 PCIe Interface 4

5 Add in card passive topology Segment1: PowerSI general extraction; Segment2: 3D modeling PowerSI General Extraction 3D modeling 5

6 PowerSI trace impedance check Z0 of the PCIe golden finger is about 60ohm Z r 87 ln 5.98h 0.8w t 6

7 SystemSI trace impedance check Zdiff of the PCIe golden finger is about 84ohm 7

8 PowerSI 3DFEM Freq domain modeling 3DFEM solver was used to extract trace and edge connector Note: The special 3DFEM FW port should be setup before simulation. 8

9 HFSS 3DFEM Freq domain modeling 3DFEM solver was used to extract trace and edge connector Note: The lumped port should be setup before simulation. 9

10 Return loss for Segment2 3D modeling Note: Both tools can correlate well within 5GHz. 10

11 Insertion loss for Segment2 3D modeling Note: Both tools can correlate well within 5GHz. 11

12 Total channel loss for PCIe TX nets Note: From PCIe CEM spec 1.1, add in card total loss budget is LAT < 3.84dB LAT < 2.94dB 12

13 PCIe Add in card compliance Time domain simulation topology Hspice was used for system level time domain simulation Note: 1) The PCIe standard defines two different levels of de emphasis: 3~4 db and 5.5~6.5 db; 2) In this paper PCIe transistor model was provided by Altera, and its pre tap, 1 st tap, 2 nd tap parameters can be adjusted accordingly. 13

14 PCIe Tx compliance measurement and eye spec Note: From PCIe CEM spec 1.1, the add in card compliance eye spec is shown as above. Transition and non transition bits must be distinguished in order to measure compliance against the de emphasized voltage level (VTXA_d). 14

15 CBB1.1 board for PCIe Gen1 compliance measurement CBB1.1 board MSO70804C real time Oscilloscope Note: For compliance measurement, it is required to plug the add in card into the CBB board, then let PCIe devices generate compliance pattern per spec, finally use the real time oscilloscope to measure the eye diagram. 15

16 PCIe Gen1 simulation and measurement results PCIe Gen1 Data Rate=2.5Gbps Note: Gen1 was measured by Tektronix MSO70804C with 33GHz bandwidth. 16

17 PCIe Gen2 simulation and measurement results PCIe Gen2 Data Rate=5Gbps Note: Gen2 was measured by Lecroy Wavemaster 813ZI A with 13GHz bandwidth. 17

18 Summary and Conclusions With higher and higher data rates for PCIe, more attention should be paid to the layout design, simulation and measurement in order to meet the electrical spec. 3D modeling of edge connector can provide accurate enough model to PCIe system SI simulation, thus it s very helpful to ensure the accuracy of PCIe channel SI simulation. The PCIe Gen1 and Gen2 compliance measurement validated the simulation effectiveness and the interface functionality. Due to the limitations of PCIe buffer model, transition and non transition bit generation and the software post processing capability, there are still some discrepancies happened between the simulation and measurement results. If the current EDA tools can incorporate PCI SIG SigTest post processing functions then it should be much easier for SI engineers to do PCIe SI simulations. 18

19 Reference [1] Jason Boh, Signal Integrity Simulation of PCI Express Gen 2 Channel, Agilent Technologies XrossTalk Magazine, pp.16 20, Jan [2] Altera Corporation, Stratix IV GX FPGA Development Board Reference Manual, pp.38 39, Aug [3] PCI SIG, PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1, pp.43 48, March 28, [4] Zale Schoenborn, Board Design Guidelines for PCI Express Architecture, PCI SIG APAC Developers Conference,

20 Thanks For Your Time! 20