Novel Optimization Technique for PI Controller Parameters of ac/dc PWM Converter using Genetic Algorithms

Transcription

1 nternatinal Jurnal f Pwer Electrnics and rie System (JPES) Vl., N., June 01, pp. 151~159 SSN: Nel Optimiatin echnique fr P Cntrller Parameters f ac/dc PWM Cnerter using Genetic Algrithms V M Mishra*, A N iwari**, N. K. Sharma*** *G.B.Pant Engg. Cllege, Pauri- Garhwal,( Uttrakhand, ndia),** M.M.M.Engg. Cllege, Grakhpur (U.P., ndia), *** KE, Ghaiabad (U.P., ndia) Address: G B Pant Engg Cllege, Pauri-Garhwal, tel/fax institute E mail:[email protected],[email protected],[email protected] Article nf Article histry: Receied N 9 th, 011 Reised Mar 9 th, 01 Accepted Apr 11 th, 01 Keywrd: Genetic Algrithms P ltage cntrller PWM rectifier H ABSRAC he aim f this paper is t present a nel cntrl scheme and designing f reactance parameter f PWM cnereter and find the ptimied alue f parameters fr ltage P cntrller. Paper describes the applicatin f Genetic Algrithms fr ptimiatin f cntrller parameters f PWM cnerter. he behair f the stability regin is pltted with different sampling perids.genetic Algrithms used fr ff-line searching using the MALAB, the simulatin mdel f the dc- link PWM ac/dc cnerter is built up. Accrding t the simulatin results, it is knwn that, the presented cntrl strategy is feasible and alid, and the cnerter can wrk well under PMC mtr lad cnditin. Cpyright 01 nstitute f Adanced Engineering and Science. All rights resered. Crrespnding Authr: A N iwari, epartement f Electrical Engineering, M M M Engineering Cllege, Grakhpur, Uttar pradesh, ndia. [email protected] 1. NROUCON ue t nn-linear nature f the cnerter peratin and nn-linear nature f the drie lad, analysis and cntrller design f the PWM cnerter is challenging. he PWM rectifier permits pwer flw frm ac t dc link, in case the lad is drawing pwer and, frm dc link t ac surce, in case the lad is generating pwer. Fr the fur-quadrant drie cntrl the PWM rectifier is used as frnt-end cnerter. uring the drie peratin, the dc link capacitr ltage is kept cnstant and ripples free. he three-phase input currents are maintained sinusidal and in phase with the supply ltages [1,, 9, 1]. he PWM rectifier cntrls the harmnics inected in t the supply system and ensures unity pwer factr peratin. he surce inductrs pride a pwer transfer link between tw three-phase ac systems i.e., (i) three-phase ac supply and (ii) three phase ac regeneratie/back emfs f the PWM rectifier [3, 6, 8]. GA is ery different frm mst f the traditinal ptimiatin methd. t needs design space t be cnerted in t genetic space. S, genetic algrithms wrk with a cding f ariables. he adantage f wrking with a cding f ariable space is that, cding discreties the search space een thugh the functin may cntinuus. A mst imprtant difference between genetic algrithms and mst f the traditinal ptimiatin methds is that GA uses a ppulatin f pints at ne time in cntrast t the single pint apprach by a traditinal ptimiatin methds, transitin rules are used they are deterministic in nature but GA uses randmied peratrs. Randm peratrs impre the search space in an adaptie manner [5, 13]. Each chrmsmes f the ppulatin are decded fr K P and K. PWM mdel including hysteresis current cntrller, is simulated n MALAB, with each alue f chrmsme (K P and K ). here is ne fitness alue crrespnding t each chrmsme in the ppulatin. Each fitness alue is diided by the summed up fitness alue t btain fitness rati (FR) crrespnding t each chrmsme. Scaled fitness alues are summed up. Each scaled fitness alue is diided by the summed up scaled fitness alue t btain Jurnal hmepage:

2 15 SSN: scaled fitness rati (SFR) crrespnding t each chrmsme. A cumulatie SFR is assigned t each chrmsme by cumulatie additin f the crrespnding SFRs. he cumulatie SFRs lie between 0 and 1. he prcess f reprductin, crsser and mutatin is repeated fr many generatins till an ptimum slutin is reached [4, 13]. PROPOSE PWM CONVERER MOEL AN CONROLLER SCHEMES he schematic diagram f prpsed high pwer factr three-phase PWM bst cnerter is shwn in figure 1. he PWM cnerter permits pwer flw frm ac t dc link in mtring peratin and frm dc link t ac surce during generating peratin mde f the dc mtr. uring the drie peratin the dc link capacitr ltage is kept cnstant and ripples free. he three-phase input currents are maintained sinusidal and in phase with supply ltages. he cnerter cntrls the harmnics inected t the supply system and ensures unity pwer factr peratin. he surce inductrs pride a pwer transfer link between tw threephase ac systems i.e., (i) three-phase ac supply and (ii) three phase ac regeneratie/back emfs f the PWM cnerter. he cnerter is perated with uter dc link ltage cntrl lp and inner hysteresis current cntrl lp actins. he dc link ltage is sensed and it is subtracted frm the reference ltage. he dc link capacitr filters ut the ripples present in the dc link ltage. Larger ripples present in the dc link current drawn by the drie inerter, prduces larger dc link ltage ripples; hence, apprpriately large alue f the dc link capacitr is chsen t minimie the ripples. he reference ltage is kept equal the line ltage rating f the PMC mtr. Actual ltage is subtracted frm the reference ltage and errr is send t P cntrller. he utput f the P cntrller is peak alue f reference current. aid the reference current amplitude mre than the current rating f the cnerter, a limiter is applied. he limiter limits the peak alue f reference currents between a maximum and minimum set alues [10, 11, 14, 16]. Hysteresis current cntrllers are used t cntrl the PWM cnerter three-phase input currents. he peak amplitude f the reference current is multiplied with three unit ectrs. he three unit ectrs are generated using three-phase supply ltages btained frm the cmmn cupling pint. he three-phase supply ltage templates are diided by their peak amplitudes resulting in U a, U b and U c three unit ectrs in phase with phase a, phase b and phase c, ltages respectiely. hese unit ectrs are multiplied with peak alue f the reference current (btained frm the ltage cntrller) t gie ut three phase reference currents. Phase a and phase b currents are sensed and phase c current is prduced as negatie sum f the tw phase sensed currents. Actual currents are subtracted frm the respectie phase reference currents rendering the three current errrs. Using the three current errrs * a_err, * b_err and * c_err the hysteresis current cntrllers generate switching pulses fr upper and lwer GBs f phase a, phase b and phase c legs respectiely. With ltage and current cntrllers, the dc link ltage is maintained cnstant and input three phase current is made sinusidal and in phase with respectie supply phase ltages[5,9,10]. hree-phase ac L R C MOOR ic-(i a i b ) - a b c - a_err a b b_err c c_err Current Cntrller * m Ua, Ub, Uc Unit sine current templates Pulse Generatin Circuit Limiter Vltage Cntrller V errr - * ea,eb,ec Peak etectr igital Prcessr Figure 1. Cntrl scheme f PWM cnerter. JPES Vl., N., June 01 :

3 JPES SSN: OPMZAON OF P GANS USNG GENEC ALGORHMS GA wrks n natural elutin prcess. he elutin prcess is perated n chrmsmes. he decded structures uses f the chrmsme are respnsible fr the perfrmance and natural selectin is linked with the perfrmance. n natural selectin, the chrmsmes haing structure which pride desirable perfrmance are reprduced mre ften than thse that haing undesirable perfrmance. his natural elutin prcess is apprpriately incrprated in cmputer algrithms t sle difficult search prblems.he aim f the GA is t sle the prblem f maximiatin (r minimiatin) t be stated in the frm f an bectie functin Generatin f nitial Ppulatin he ppulatin sie is the number f chrmsmes in the ppulatin. Randm bits are generated 1 times (equal t the length f chrmsme) and ne chrmsme (string) is frmed. he chrmsme is decded fr K P and K and tested whether it is within the OK P4 K 4 O regin f Figure 3 r nt. f K P and K are within the OK P4 K 4 O regin the chrmsme is accepted therwise reected. tal numbers f acceptable chrmsmes generated are equal t the ppulatin sie. Fr ppulatin sie is 0 and the randmly generated chrmsmes fr initial r first ppulatin are shwn in Figure Obectie Functin and Fitness Value Each chrmsmes f the ppulatin are decded fr K P and K. PWM mdel including hysteresis current cntrller is simulated n MALAB, with each alue f chrmsme (K P and K ). he perfrmance f cntrller gains is udged by alue f AE (ntegral ime Abslute Errr). he perfrmance index AE is chsen as bectie functin. Fitness functin is defined as 1/ (AE1). f mre than 5% ersht ccurs in starting ltage respnse a 75% f the penalty is impsed t the fitness alue. here is ne fitness alue crrespnding t each chrmsme in the ppulatin Reprductin (Using Rulette Wheel Selectin Criteria) Each fitness alue is diided by the summed up fitness alue t btain fitness rati (FR) crrespnding t each chrmsme. he fitness alues crrespnding t each chrmsme in the ppulatin are scaled as (FR-min.FR)/(max. FR min. FR). Where, min.fr and max.fr are minimum and maximum alues f fitness ratis btained frm the fitness alues f the chrmsmes in the ppulatin. Scaled fitness alues are summed up. Each scaled fitness alue is diided by the summed up scaled fitness alue t btain scaled fitness rati (SFR) crrespnding t each chrmsme. A cumulatie SFR is assigned t each chrmsme by cumulatie additin f the crrespnding SFRs. he cumulatie SFRs lie between 0 and 1. Randm numbers between 0 and 1 are generated 0 (ppulatin sie) times. f the magnitude f generated randm number is equal r immediate belw t cumulatie SFR f a chrmsme in the ppulatin, the chrmsme is cpied t new ppulatin. tal 0 times (equal t ppulatin sie) chrmsmes are cpied. he prbability f generating a randm number is unifrm thrughut between 0 and 1, hence, prbability f selectin f mre number f cpies is high fr the chrmsme haing high fitness alue Crsser and Mutatin Crsser prbability is chsen 70%. Out f 0 chrmsmes, first 7 chrmsmes are randmly chsen in ne grup and ut f remaining 13 chrmsmes, anther 7 chrmsmes are randmly chsen in ther grup, the third grup stres remaining 6 chrmsmes. A randm number is generated frm 1 t 1(length f bits in chrmsme), this number is taken as crsser site. First chrmsmes f first grup and secnd grup are picked up and bits f their chrmsmes beynd the crsser site are exchanged. Anther randm crsser site is generated and secnd chrmsmes f first grup and secnd grup are picked up and bits f their chrmsmes after the crsser site are exchanged. Similar prcess is repeated fr all the 7 chrmsmes f the first and secnd grups are crsser. A new ppulatin is btained by cmbining the 14 chrmsmes f crsser grups and 6 chrmsmes f the third grup. Mutatin prbability is chsen 0.5%. n the new ppulatin ttal 0.5% string elements are altered randmly. Chrmsmes f the new ppulatin are decded fr K P and K, and any chrmsmes fund lying utside f the regin OK P4 K 4 O f Figure 4 are replaced by a randmly generated new chrmsme lying inside the regin OK P4 K 4 O. Nw, the prcess f reprductin, crsser and mutatin is repeated fr many generatins till an ptimum slutin is reached. he ppulatin sie, crsser prbability, mutatin prbability and number f generatins can be aried fr repeated search t ptimise the slutin. Nel Optimiatin echnique fr P Cntrller Parameters f ac/dc PWM. (V M Mishra)

4 154 SSN: Optimum Gains using GA he GAs is run fr ff line ptimisatin f the cntrller gains fr the ppulatin sie0, crsser prbability70%, mutatin prbability0.5% till 5 generatins. he fitness alues fr 1 st and 5 th generatin are shwn in figure 7 and chrmsmes fr 1 st and 5 th generatin are pltted in figure 5 shws the best alues f chrmsmes after 5 th generatin. he best pair f cntrller gain btained as K P and K CONROLLER ESGN FOR HE PWM CONVERER he cntrl strategy f PWM Cnerter regulates input current and utput dc link ltage. he cntrl analysis f the cnerter can be simplified by making minr (inner) current lp independent f the uter ltage lp. he nly way t delink the inner current lp with uter lp is t make the inner lp much faster than the uter lp. he inner current lp can be made faster by keeping high rati f the dc bus ltage t the alue f the phase ltage and/r by reducing the alue f surce inductr and/r by impring the gain parameters f the current lp cntrller. he current cntrl scheme pted is hysteresis current cntrller as shwn in Fig 1, which makes the input line currents in phase with their respectie utility phase ltages. At steady-state peratin f the cnerter, the switching pattern generated by the current cntrller is fixed fr ne cycle f the utility supply frequency. Hence, the aerage ltage generated due t PWM ramp switching is als a sinusidal EMF [15]. he hysteresis current cntrller is in inner lp and it perates in statinary reference frame.he space ectr current equatin is represented as Es R L s E (1) i nput line currents, supply phase ltages and regeneratie emfs are represented by space ectr (Using Park s ransfrmatin) as belw π π iae ibe ice ; 3 π Es eane ebne ecne 3 π Ei eane ebne ecne 3 π π Pwer balance cncept is applied fr design f uter ltage cntrl lp. he pwer balance equatin f the PWM Cnerter is d 1 VC 3 d 1 CV C Es R L () dt RL dt he erall aim f the cntrller is t cntrl input line current and utput dc link ltage. Hence, at steadystate perating pint f dc link ltage ( ) and input current ( ), the equatin () can be written as V C 3 E s R R L (3) Chsing smaller alue f the line current frm equatin (3), the line current space ectr ( ) is, 1 Es Es 8V (4) c R R 3RRL mpsing small disturbance arund the perating pint, i.e., replacing the dc link ltage with ( ) and line current with ( ), the dynamic equatin f the system represented by equatin () is btained and neglecting square terms f and and simplifying it, we get and. L s 1 V R ( ) ( R ES ) c L ES R 3 4 RLC s 1 he abe dynamic equatin f the ltage transfer functin can be written as ( n s 1) G ( s) A ( s 1 ) (5) (6) JPES Vl., N., June 01 :

5 JPES SSN: Where ( ) 3R E R L R C A ; and. L S L n 4Vc ( R ES ) Figure shws a hybrid cntrl system fr implementing the cntrl f the PWM cnerter. he ltage cntrller prcesses the ltage errr and current cmmand is generated. * GC ( ) Limiter Gh ( s) GV ( s) GAL SYSYEM ANALOG SYSYEM Figure. Clsed lp cntrl system f dc link ltage cntrller he limiter is replaced with escribing Functin in rder t linearie the saturatin nn-linearity. t is bsered that the describing functin f the saturatin nn-linearity is nly amplitude dependent. Hence, it is frequency inariant haing er phase shift. Fr stability analysis purpse the limiter blck is mitted. he blck G h (s) is transfer functin f Zer Order Hld. t is gien as s ( e ) G h(s ) 1 (7) s Cntrller gain functin is gien as KPV ( 1) KV G C( ) (8) ( 1) Clsed lp transfer functin f the erall ltage cntrl system is, VC ( ) GC ()G hgv ( ) NZ ( ) G ( ) (9) * VC () 1 GC ()G hgv () Z ( ) he -transfrm f numeratr f equatin (9) is written as A n ( 1) (1 α ) ( -1) KPV KVZ N Z( ) (10) ( α ) ( 1) - e V Where, α. he characteristic equatin f the system is ( ) 1 N ( ) 0 (11) Substituting equatin (11) int equatins (9) and after simplificatin; the clsed lp transfer functin is written as N N1 N0 G ( ) (1) N N 1 α N α ( ) { 1 ( )} ( 0 ) ( ) ( α )( ) ( ) Where, N A K K, N A 1 K K A K K and n PV V 1 PV V V n PV V N0 A KPVn A KPV (1 α ); Frm equatin (1), the characteristic equatin is ( N ) { N ( 1 α )} ( N α ) (13) Fr stability analysis f the system, Bilinear transfrmatin i.e., (1r)/(1-r) e θr is applied with equatin (13). Accrding t Bilinear transfrmatin, n unit circle in the -plane, arying θ r anticlckwise frm π thrugh 0 t π, ω r aries frm - thrugh 0 t in r-plane, where rω r. he left half r- plane maps the interir f the unit circle in the -plane. Substituting (1r)/(1- r) in the characteristic equatin (13), we get, ( ) { 1 ( α )} ( 0 α ) {( ) ( 0 α )} ( N ) ( N1 ( 1 α )) ( N0 α ) 0 N N 1 N r N N r { } (14) Nel Optimiatin echnique fr P Cntrller Parameters f ac/dc PWM. (V M Mishra)

6 156 SSN: he rts f secnd rder characteristic equatin are always in the left half f r-plane if all cefficients are psitie. Hence, three cnditins are deduced crrespnding t each cefficient f the characteristic equatin t be greater than er. Cnditin : [( N ) { N ( 1 α )} ( N α )] > Substituting alues f N, N 1, N 0, and simplifying, we get K pv { A n A ( 1 α )} KV { A n A ( 1 α )} ( 1 α ) > 0 (15) he term { ( 1 α )} > 0 fr cnerter peratin, diiding by psitie quantity ( 1 α ) n bth sides f the equatin (15) and sling, we hae KPV K V < 1 KP1 K1 (16) Where, ( 1 α ) K P1 and K 1 K P1. { A ( 1 α ) A } Cnditin : n {( N ) ( N α )} 0 0 > Substituting alues f N, N 1 and simplifying, we get K pv { A ( 1 α )} KV ( A n ) ( 1 α ) > 0 Since, ( 1 α) is always psitie fr the cnerter, hence, diiding by ( 1 α) inequality (17), we get K K PV K K V < P ( ) Where, 1 1 K P A Cnditin : and K A 1 n α. {( N ) ( N ( 1 α )) ( N α )} > Substituting alues f N, N 1 & N 0, and simplifying, we hae A ( 1 ) K 0 > Placing alues f A, and α, we write (17) n bth sides f (18) α (19) 3R LC K V ( E s R ) 1 e > 0 8V c Plarity f and gain K V are always kept psitie. Hence, t satisfy the stability cnditin, the tw terms in braces are required t be either psitie r bth negatie. he first term in braces is (E s - R)>0 fr the cnerter. he secnd term in braces is (1-e (-/) )>0 when R L is psitie i.e., fr cnerter peratin. Hence, the inequality represented by equatin (0) is always satisfied fr K >0. he parameters f the PWM cnerter are chsen as, V C 590 Vlts, E s 30 Vlts, L4.90 mh, R.5 Ω, R L 50 Ω, C5050 µf and sampling perid 0.4 ms. he steady-state current ( ) is btained frm equatin (4), fr the gien parameters. he calculated alue f is amp fr the cnerter. f sampling perid is increased, the stability regin shrinks. Figure 3 shws stability regins fr sampling perids 0.4m sec, 0.8m sec, m sec and 10m sec as OP 1 1 O, OP O, OP 3 3 O, and OP 4 4 O respectiely. Equatin (1) is simplified and written as N N N 1 N G ( ) N { 1 ( α )} ( N ) ( ) ( )( ) 1 (0) (1) JPES Vl., N., June 01 :

7 JPES SSN: Where, { } ( α ) ( α ) N N N N N 1 0 1, { N ( 1 α )} ( N ) and c ( N α ) ( N ). b 1 0 mpulse respnse f equatin (1) is btained as, N { N 1 N ( 1 α )} G ( k ) δ ( k ). N ( N ), b b 1 c, b b c N N 1 ( ) ( ) ( ) k N ( ) ( ) k δ t Als, unit-step respnse f the ltage cntrl system represented by equatin (1) is btained as N { N1 N ( 1 α )} G ( k ) u ( k ). Unit _ step (3) N ( N ) ( N 1) ( N 1 ) ( ) ( )( ) ( )( ) ( ) k ( N ) ( )( ) ( ) k u k Values f K PV and K V are chsen near t rigin in stable range f figure 3; as t make the system mre stable. () 10msec mse C B A 0.8mse 0.4ms Figure 3. Variatin in stability regin with sampling perid n K PV and K V plane 5. RESUL AN ANALYSS he gains btained by trial and errr cannt be ptimum. btain near ptimum alue f the gains in regin OP 4 CO f the K PV -K V plane f figure 3; space search methd, based n Genetic Algrithms is applied. nitially 300 chrmsmes [K PV K V ] ppulatin is generated. he minimum alues f bth K PV and K V are kept and the maximum alues are restricted in the shaded prtin f figure 3. he unit step respnse is bsered and integral time abslute errr (AE) is chsen as bectie functin. he fitness functin is defined as Fitness (1-0.5 penalty)(100/(1ae)). he alue f penalty is chsen 1 if there is an ersht mre than %, therwise the alue f penalty is kept er. A chrmsme with higher alue f scaled fitness has fair chance t surie and prduce ff springs in next generatins. he prcess t prduce next generatin is ia reprductin, crsser and mutatin. 4(a) is initial ppulatin f 300 chrmsmes and figure 4(b) is ppulatin f the chrmsmes after 00 generatins. After 00 generatins, marity f the chrmsmes bear higher alues f fitness. he chrmsmes shwn in figure 4(b) are cncentrated at higher alue f K PV and lwer alue f K V. n figure 4(b) and (c) the chrmsmes after 00 generatins are pltted with their scaled fitness and decded alues f respectie K PV and K V. he chrmsme haing highest scaled fitness decded as K PV and K V he step respnse cures with different cntrller gains K PV 1.30 and K V 0.14, K PV 1.1 and K V 0.1, K PV and K V , K PV and K V are shwn in figure 5. he ptimised gain K PV and K V is mst suitable fr the ltage cntrller. Nel Optimiatin echnique fr P Cntrller Parameters f ac/dc PWM. (V M Mishra)

8 158 SSN: Figure 4.distributin f chrmsmes in (a) initial ppulatin (in K PV -K V pane) (b) after 00 generatins final ppulatin (in K PV -K V pane) (c) with respect t scaled fitness and K PV and (d) with respect t scaled fitness and K V. Figure 5.Unit step respnses with different cntrller gains. 6. CONCLUSONS he clsed lp cntrl system is deelped based n the cnerter mdel. An analysis has been carried ut t find the stability regin f the ltage cntrller n K P and K plane. he unit impulse and unit step respnses are deried fr the clsed lp ltage cntrller f the PWM cnerter. he ptimum P ltage cntrller gain parameters are btained using the Genetic algrithms search methd. he PWM cnerter system prides the desired respnse with the ptimied gains. REFERENCES [1] Bn ech Oi, Jhn C.Salmn et al, A three Phase cntrlled- current PWM cnerter with leading pwer factr, EEE rans.n nd. Applns, Vl.A-3, N.1, pp.78-84, Jan/Feb [] Bn ech Oi, Juan W.ixn et al, An ntregrated AC drie system using a cntrlled- current PWM rectifier/nerter link, EEE rans. On ndustrial Electrnics, Vl.3, N.`1,pp.64-70, Jan [3] Rusng Wu, S. B. ewan and G. R. Slemn, Analysis f a PWM ac t dc Vltage Surce Cnerter Using PWM with Phase and Amplitude cntrl,'' EEE rans. n nd. Applns., Vl. 7, N., pp , March/April, [4] M.O. Eissa, S.B. Leeb, G.C. Verghese and A.M. Stankic, Fast cntrller fr a unity-pwer-factr PWM rectifier, EEE rans. On Pwer. Electrnics, l. 11, n.l, pp 14, January JPES Vl., N., June 01 :

9 JPES SSN: [5] K.F.Man, K.S.ang and S.kwng, Genetic Algrithms: Cncepts and applicatin, EEE rans. On nd. Electrnics, l. 43, n.5, pp , Oct [6] R. Blundell, L. Kupka and S. Spiteri, AC-C Cnerter with Unity Pwer Factr and Minimum Harmnic Cntent f Line Current: esign Cnsideratins,'' EE Prc. Electric Pwer Applicatins, Vl. 145, N. 6, pp , Nember [7] N. Bruyant, M. Machmum and P. Cherel Cntrl f a three-phase actie pwer filter with ptimised design f the energy strage capacitr,in Prc. PESC Cnference, Kbe, Japan, l. 1, pp ,1998 [8] M.. sai, W.. sai, Analysis and design f three-phase AC-tC cnerters with high pwer factr and nearptimum feedfrward, EEErans. n nd. Electrnics, l. 46, n. 3, pp , June [9] Ming-sung sai and W..sai, Analysis and esign f hree Phase AC t C Cnerters with High Pwer Factr and Near Optimum Feed Frward,EEE rans. ndustrial Applicatin,Vl.46,N3,pp ,June [10] A. N. iwari, Pramd Agarwal and S. P. Sriastaa, Analysis and Simulatin f PWM Bst Rectifier, nternatinal cnference n Cmputer Applicatin in Electrical Engineering, (CERA 01) at... Rrkee, pp , Feb. 1-3, 001. [11] Bhim Singh, B. P. Singh and Mukesh Kumar, Pwer Quality mprement f AC Mains fr Single-Phase Rectifier-nerter Fed PMBLC Mtr rie fr Air Cnditining,'' Prceedings f the nternatinal Cnference n Cmputer Applicatins in Electrical Engineering Recent Adances, CERA 01, pp , Feb. 1-3, 00. [1] A. N. iwari, Pramd Agarwal and S. P. Sriastaa, Mdified Hysteresis Cntrlled PWM Rectifier, EE Prc. Electric. Pwer Applicatins, Vl. 104, ssue- 4, pp , July 003. [13] Bimal K. Bse.Mdern. Pwer Electrnic and AC ries, Beiing: Machine ndustry Publishing Huse, 003. [14] Hngin Sng1*, Xinchun Shi, Guliang Zhu, Research On hree Phase Vltage-surce PWM Rectifier Based On Nnlinear Cntrl Strategies, Prceeding f nternatinal Cnference n Electrical Machines and Systems, Oct. 8-11, Seul, Krea, 007. [15] unisha Wieralne and Gerry Mschpus, Analysis & esign f a Nel ntegrated hree Phase Single Stage AC/C PWM cnerter, EEE 010. [16] Wang Jianhna, Zhang Fangha et al, Mdeling and analysis f a Buck/Bst Bidirectinal cnerter with eelped PWM Switch Mdel, nternatinal cnference n Pwer Electrnics ECEE Asia,May30-June 3,011,he Shilla Jeu, Krea. BOGRAPHY OF AUHORS Mr. V M Mishra brn in ndia. He receied B.E. egree frm MMM Engineering Cllege Grakhpur, ndia in 1988, Mech frm Reginal Engineering Cllege, Kurushetra, ndia in 1995, and pursuing Ph. degree frm the UP echnical Uniersity Lucknw, ndia, all in electrical engineering. n 005 he ined G B Pant Engg Cllege Pauri Garhwal. Befre 005, he was wrking in MMM Engg Cllege Grakhpur.His main area f interest includes pwer electrnics cntrl, pwer quality applicatins, actie pwer filters, electrical dries and wind energy cnersin systems r.a.n iwari brn in india. He receied B.E. egree frm N Calicut, ndia in 1988, Mech frm Uniersity f Rrkee (Nw it is ndian nstitue fechnlgy Rrkee) ndia in 1994, and the Ph. degree frm the ndian nstitute Of echnlgy Rrkee ndia in 003, all in electrical engineering. n 1989 he ined M M M Engg Cllege Grakhpur. His main area f interest includes pwer electrnics cntrl, pwer quality applicatins, actie pwer filters, electrical dries and wind energy cnersin systems. r N K Sharma (B, 86 and M, 93) gt his B. Sc. Engg. frm Faculty f Engg. ayalbagh Educatinal nstitute (eemed Uni.) Agra, M. ech. and Ph.. frm Kanpur. Presently he is prfessr in KE, Ghaiabad, NA. He is Member Bard f studies (Electrical and Electrnics), Mahamaya echnical Uniersity, Nida, UP. He hae written mre than 30 research papers, superised 5 M. ech. and superising 4 Ph..s. His area f research includes Pwer System Restructuring, FACS, Netwrk Analysis and Synthesis. Nel Optimiatin echnique fr P Cntrller Parameters f ac/dc PWM. (V M Mishra)