Clock-driven distributed real-time implementation of endochronous synchronous programs

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1 Clck-drven dstrbuted real-tme mplementatn f endchrnus synchrnus prgrams D. Ptp-Butucaru INRIA Rcquencurt, France [email protected] R. de Smne INRIA Spha Antpls, France [email protected] J.-P. Talpn INRIA Rennes, France [email protected] Y. Srel INRIA Rcquencurt, France [email protected] ABSTRACT An mprtant step n mdel-based embedded system desgn cnssts n mappng functnal specfcatns and ther tasks/peratns nt executn archtectures and ther ressurces. Ths mappng cmprses bth tempral schedulng and spatal allcatn aspects. Therefre, we prmte an apprach whch starts frm lsely-tmed/asynchrnus mdels and prceeds by refnng them t fully synchrnzed nes, usng s-called clck calculus technques under the archtecture cnstrants. In ths paper we prvde a mdelng framewrk based n an ntermedate representatn frmat, called clcked graphs, fr plychrnus endchrnus specfcatns, whch are the nes that can be safely cnsdered fr determnstc dstrbuted real-tme mplementatn usng statc schedulng technques. Our frmalsm allws the specfcatn f bth ntrnsc crrectness prpertes f the specfcatn, such as causalty and clck cnsstency, and external crrectness prpertes, such as endchrny, whch ensure cmpatblty wth the desred mplementatn archtecture, ncludng bth hardware and sftware aspects. Usng ths frmalsm, we defne a new methd fr dstrbuted real-tme mplementatn f synchrnus specfcatn. The mve frm (endchrnus) synchrnus specfcatn t realtme scheduled mplementatn s a seamless sequence f mdel decratns. Categres and Subject Descrptrs D.3.4 [Prgrammng Languages]: Prcessrs Cde generatn, Optmzatn; D.4.7 [Operatng systems]: Organzatn and Desgn Dstrbuted systems, Real-tme systems and Embedded systems Keywrds synchrnus mdel, ntermedate representatn, clck calculus, dstrbuted real-tme schedulng Permssn t make dgtal r hard cpes f all r part f ths wrk fr persnal r classrm use s granted wthut fee prvded that cpes are nt made r dstrbuted fr prft r cmmercal advantage and that cpes bear ths ntce and the full ctatn n the frst page. T cpy therwse, t republsh, t pst n servers r t redstrbute t lsts, requres prr specfc permssn and/r a fee. EMSOFT 2009 Grenble, France Cpyrght 200X ACM X-XXXXX-XX-X/XX/XX...$ INTRODUCTION Synchrnus reactve frmalsms [1, 2] are mdelng and prgrammng languages used n the specfcatn and analyss f safety-crtcal embedded systems. They cmprse (synchrnus) cncurrency features, and are based n the Mealy machne paradgm: Input sgnals can ccur frm the envrnment, pssbly smultaneusly, at the pace f a gven glbal clck. Output sgnals and state changes are then cmputed befre the next clck tck, gruped as ne atmc reactn, als called executn nstant. Because cmmn cmputatn nstants are well-defned, s s the ntn f sgnal absence at a gven nstant. Reactn t absence s allwed,.e., a change can be caused by the absence f a sgnal n a new clck tck. Snce cmpnent nputs may becme lcal sgnals n a larger cncurrent system, absent values may have t be cmputed and prpagated, t mplement crrectly the synchrnus semantcs. When an asynchrnus, pssbly dstrbuted mplementatn s meant, where pssbly dstrbuted cmpnents cmmuncate va message passng, the explct prpagatn f all absent values may clg the system t a certan extent. A natural questn arses: when can ne dspse f such absent sgnal cmmuncatns? Suffcent cndtns, knwn as (weak) endchrny [3, 4, 5], have been ntrduced n the past t fgure when the absent values can be replaced n the mplementatn by actual absence f messages wthut affectng ts crrectness and determnsm. These cndtns establsh that cmpund reactns that are apparently synchrnus can be splt nt ndependent smaller reactns that are asynchrnusly feasble n a cnfluent way (as cned by R. Mlner [6]), s that the frst ne des nt dscard the secnd. Ths s als lnked t the Kahn prncples fr netwrks [7], where nly nternal chce s allwed, n rder t ensure that verall lack f cnfluence cannt be caused by nput sgnal speed varatns. In ths paper, we use these theretcal results as the fundatn f a new methd fr dstrbuted real-tme mplementatn f synchrnus specfcatns. Fllwng the tradtnal apprach n cmpler develpment, ur methd s centered arund a new ntermedate representatn frmat, called clcked graphs (CG). On ne hand, ths frmat allws the fathful representatn f specfcatns wrtten n hghlevel synchrnus languages lke Esterel [8], Scade/Lustre [9], Sgnal [4], r dscrete Sccs [10], ncludng sme structural nfrmatn that can be used fr effcent cde generatn purpses. On the ther hand, a CG specfcatn s

2 clse enugh t the target machne cde t allw fne manpulatns such as schedulng, allcatn, and ptmzatn. We fcus n ths paper n the real-tme mplementatn f CG specfcatns n dstrbuted hardware archtectures (a large crpus f wrk exsts n the translatn f hgh-level synchrnus specfcatns nt ntermedate representatns related t urs). The CG representatn s based n the separatn f cmputatns, under the frm f a dataflw graph, frm cntrl, under the frm f clcks whch dentfy the synchrnus executn nstants where the dataflw elements are executed. The tw parts are ntercnnected, as all cmputatns and cmmuncatns are asscated a clck defnng ther executn cndtn, and clcks may depend n values cmputed by the dataflw. We stress the clck-drven specfcty f ur methd. Clcks are lgcal actvatn cndtn defnng the sequence f synchrnus executn nstants where sme cmputatn r cmmuncatn takes place. Whle such actvatn cndtns are tradtnally represented wth events, the actvatn events asscated wth ur clcks are lgcal, n the sense where they are cmputed by the system tself at each executn nstant, and nt receved frm the exterr (e.g. under the frm f nterrupts). Ths mdel s nwadays cmmn n cmputer scence and engneerng, even at hardware level where clck gatng technques are used t mnmze pwer cnsumptn. The mplementatn f ur CG specfcatns s defned as a sequence f transfrmatns whch gradually add nfrmatn t the representatn. The frst mplementatn step s t make explct the dependences between the cmputatns f the varus lgcal clcks n a clcked graph wth dependences (CGd). Then, we prvde cndtns determnng when such a graph s endchrnus. Endchrny beng a schedulng-ndependence crtern, we knw that fr endchrnus clcked graphs (CGe), untmed asynchrnus smulatn s determnstc and equvalent wth the synchrnus semantcs. The last step f ur mplementatn prcess prduces a real-tme schedule by assgnng real-tme dates and executn ressurces (prcessrs and buses) t each element f a CGe. Ths apprach, nspred frm the AAA/SynDEx methdlgy [11], results n a scheduled clcked graph (CGsch) that descrbes the real-tme schedulng f ne clck cycle. The executn f the scheduled mplementatn s an nfnte repettn f such executn nstants. The dffculty here s t ensure the cnsstency between the lgcal clcks f the CGe specfcatn and the real-tme dates and ressurce allcatns f the CGsch scheduled mplementatn. We prvde a schedulng algrthm ensurng by cnstructn these cnsstency prpertes, and we cmpare t wth the exstng ne f SynDEx. Fr smplcty, we restrct urselves t smple target hardware archtectures frmed f a unque asynchrnus message-passng bradcast bus that cnnects a set f (pssbly dfferent) sequental prcessrs. We als make the smplfyng assumptn that the bus s relable, whch s realstc n certan settngs fr real-lfe buses such as CAN [12, 11], pendng the use f fault tlerant cmmuncatn lbrares and a relablty analyss that are nt cvered n ths paper. Our schedulng technque als wrks fr statc TDMA buses such as TTA r FlexRay (statc segment), but des nt take full advantage f the tme-trggered nature f these archtectures. Future wrk wll cver better mplementatns n tme-trggered and hetergenus archtectures and mre cmplex ntercnnect tplges. 2. RELATED WORK Our wrk s clsely related t the wrk f Benvenste et al. n tagged systems [13]. Indeed, the man rgnalty f ur wrk the cmbnatn f lgcal clcks and real tme n a sngle frmalsm ccurs n the frm f a tme refnement, whch can be mdeled usng tag refnements. The dfference s that we als need t deal wth spatal allcatn ssues, causalty, and that we fcus n specfc tme mdels n rder t gve effcent mplementatn algrthms. The secnd man nspratn f ths wrk s the AAA/SynDEx methdlgy fr dstrbuted real-tme mplementatn f synchrnus specfcatns [11]. The schedulng apprach we use here s much nspred frm the SynDEx ne. The dfference s that SynDEx des nt treat clcks as frst-class ctzens, allwng ther defntn nly thrugh structured dataflw cnstructs. By cnsequence, executn cndtns f a specfcatn are ften pessmstc, whch als pessmzes the mplementatn. Our wrk prvdes, n ne hand, a mre flexble language supprtng better specfcatns and mplementatns and n the ther hand, a mre general frmal framewrk fr reasnng abut the crrectness f such mplementatn prcesses. The thrd man nspratn f ur wrk s the prevus wrk n endchrny, already mentned abve. Our wrk extends ths lne by prpsng a frmalsm cmbnng the manpulatn f endchrnus lgcal clcks wth that f real tme. In ths sense, t ges beynd results n the mplementatn f the Sgnal/Plychrny language [14]. Als related t Sgnal are the results f Kunturs and Wlnsk [15] n the schedulng f herarchcal cndtnal dependency graphs, a frmalsm allwng the representatn f data dependences and executn cndtns. The man dfference wth ur wrk s that we fcus n tmed and dstrbuted mplementatn, whereas Kunturs and Wlnsk fcus n ptmzng mn-prcessr untmed mplementatns. The ntermedate representatn prpsed n ths paper s als nspred frm the large crpus f wrk cncernng clck analyss and the cmplatn f synchrnus languages. We als mentn here the large crpus f wrk n ptmzed dstrbuted schedulng f dataflw specfcatns nt tme-trggered archtectures [16, 17]. Gven the prxmty f the specfcatn frmalsm, we nsst here n the wrk f Casp et al. n the dstrbuted schedulng f Scade/Lustre specfcatns nt TTA-based archtectures [18]. The man dfference s that n TTA-based systems cmmuncatns must be realzed n tme slts that are statcally assgned t the varus prcessrs. 3. INTERMEDIATE REPRESENTATION Ths sectn defnes the syntax f clcked graphs. A clcked graph s a dataflw graph G whse elements (ndes and arcs) are labelled wth clcks. We frst ntrduce the clck defntn language, whch s the fcus f ur apprach. Then, we ntrduce the dataflw cnstructs, and cnclude wth an example. 3.1 Clcks Clcks represent executn cndtns defnng when a cmputatn r cmmuncatn s perfrmed, r when sme data s avalable t be used n cmputatns. In ur purely syn-

3 nstant utput prt x true x > (01) (01) (x > 0) (01) (01).0(01) Fgure 1: Examples f clcks chrnus settng, clcks are functns asscatng t each executn nstant a value f 1 (true, actve) r 0 (false, nactve). A cmputatn r cmmuncatn whse clck s c wll be executed n the executn nstants where c s true. We defne here the syntax allwng the defntn f clcks. Regular repettns f actve and nactve nstants, such as data-ndependent cunters, are specfed usng ultmately perdc nfnte Blean wrds f the frm w t(w p), where w t, w p are fnte wrds ver {0, 1}, and w t(w p) stands fr the nfnte wrd startng wth w t and cntnung wth an nfnte sequence f w p. Fr nstance, 11(001) stands fr The cnstant clcks are dented true = (1) and false = (0). Cndtnal data-dependent cmputatns are represented usng Blean expressns ver the utput prts f the dataflw ndes. 1 Fr nstance, f s an nteger utput prt f dataflw nde n, = 3 s the clck defnng the executn nstants where has a value f 3. Smlarly, 1 = 2 ntutvely defnes executn nstants where 1 equals 2. Much effrt wll be dedcated n the fllwng sectns t ensure that the arguments needed t cmpute such clcks are avalable when the Blean expressns are evaluated. These elementary clcks (cnstants, ultmately perdc wrds, and Blean atms) can be cmpsed usng: The Blean cmbnatrs,, and, whch wrk nstant-wse. Fr nstance, c 1 c 2 s true at executn nstants where bth c 1 and c 2 are true. We als dente wth c 1 \ c 2 = c 1 c 2 the dfference peratrs n Bleans and clcks. The subclck peratr c 1.c 2, whch evaluates c 2 nly n nstants where c 1 s true. The subclck peratr s dfferent frm a smple cnjunctn. When c 2 s a ultmatelly perdc wrd, we advance n c 2 nly when c 1 s true. When c 2 s a Blean expressn, we need ts arguments nly when c 1 s true. Fg. 1 gves examples f clcks, bth elementary and cmpsed Clck semantcs In the synchrnus mdel, each varable (utput prt f a dataflw nde 1 ) s ether absent n an executn nstant, r s assgned a unque value that wll be used n cmputatns thrughut the nstant. T facltate ntatns, we shall append t the data dmans f all the utput prts f the specfcatn a specal value that dentes the absence f a value n a gven executn nstant. When a dataflw nde 1 All dataflw cnstructs are defned n Sectn 3.2. We als explan there why nly nde utputs are cnsdered. s nt executed n a gven nstant, all ts utputs are set t. Gven a dman D, we shall dente D = D { }. Usng ths ntatn, we can represent each clck c wth a predcate defnng the nstants where the clck s actve: Y c : N D S {0, 1} n N O(n) where N s the set f all dataflw ndes f the specfcatn, O(n) s the set f utput prts f nde n (defned n the Sectn 3.2), and N s the set f pstve nteger ndces f executn nstants. Ths nterpretatn f clcks as predcates naturally rganzes the clcks n a Blean algebra where the Blean cmbnatrs have ther usual meanng. 2 We dente wth the partal rder between clcks, where c 1 c 2 means that at each executn nstant c 2 s true whenever c 1 s true. Gven that the subclck peratr s nn-standard, we lst here sme f ts prpertes: true.c = c.true = c, false.c = c.false = false; asscatvty: (a.b).c = a.(b.c); left dstrbutvty f the bnary Blean peratrs: c.(c 1 p c 2) = c.c 1 p c.c 2. Determnng clck nclusn r equalty (a frm f satsfablty mdul theres) s undecdable n the general case, because t nvlves the cmplexty f dealng wth the functns f the dataflw ndes. Hwever, varus suffcent cndtns (and asscated decsn algrthms, knwn as clck calcul ) have been prpsed fr clck nclusn and equalty, rangng frm smple syntactcal nes (as n SynDex [11]), t BDD-based technques lke thse f Kunturs and Wlnsk [15]. All schedulng algrthms prpsed later n ths paper are desgn t functn wth such suffcent cndtns, nstead f exact equalty and nclusn tests. 3.2 Clcked graphs A clcked graph s a par G = (N, A) frmed f the set f dataflw ndes N and the set f arcs A. Each nde n N has a set f named nput prts I(n), a set f named utput prts O(n), and a clck clk(n). The name f a prt p s dented name(p), and we assume that the prts f a nde have all dfferent names. The prt f name name f nde n shall be dented wth n.name. Each nput and utput prt p s assgned a data type (a dman) D p. Each dataflw arc a A cnnects ne utput prt dented src(a) t ne nput prt dented dest(a) upn a cmmuncatn cndtn (a clck) dented clk(a). Therefre: A [! O(n) [! I(n) C n N n N where C dentes the set f all clcks that can be defned usng the prevusly-defned syntax. Each arc has a data dman D a and we requre that fr all arc a A we have: D src(a) = D dest(a) = D a There are tw types f dataflw ndes: cmputatns and delays. Cmputatn ndes represent atmc stateless cmputatns (functn calls) that are cmpleted nsde ne executn cycle. The state f the system s mantaned by the delays, whch allw data t be passed frm ne executn cycle t the next (but therwse perfrm n cmputatn). We dente wth N C the set f cmputatn ndes, and wth N the set f delays. 2 Nte that ur nterpretatn means that the set f clcks s a tag system, n the sense f Benvenste et al. [13].

4 c 1 1 n f m c c (cmputatn blck) (delay) (dentty) c Mem c c c c c c c c c \ c Fgure 2: Basc dataflw ndes (dentty s a specal knd f cmputatn blck) Fr each cmputatn nde n N C, we assume an mplementatn (a pece f cde n a lbrary) s prvded that takes as nput ne value fr each nput prt I(n) and prduces ne value fr each utput prt O(n). The cmputatn needs nt be determnstc, t allw the mdelng f sensrs. It s assumed, hwever, that n hdden dependences (e.g. sde effects n unspecfed varables) exst between mplementatns f dfferent ndes, r between successve cmputatns f a gven cmputatn nde. The cmputatn s assumed t be atmc, n the sense where all nputs are read befre perfrmng the cmputatn and befre all utput s prduced. One partcular type f cmputatn nde s the dentty nde that has ne nput prt, named, ne utput prt, named, and whse functn s dentty (cpy the value frm the nput prt t the utput prt). T an dentty nde n we asscate ts dman D n, whch s the dman f ts nput and utput prts. A delay δ N f clck clk(δ) specfes the passng f values between the successve executn nstants defned by clck δ. A delay δ has a data dman D δ, ne nput prt f type D δ, ne utput prt f type D δ, and ne ntal value δ 0 D δ. In the frst executn nstant where clk(δ) s true, δ prduces δ 0 thrugh the utput prt, and reads a new value thrugh the nput prt. In subsequent executn nstants where clk(δ) s true, the utput prt prduces the value prevusly nput thrugh. We use fr dataflw ndes the smple graphcal representatns f Fg. 2. Delay ndes are labelled wth, dentty ndes are labelled wth, and ther cmputatn ndes (ncludng nn-determnstc nes) are labelled wth ther cmputng functn. Ths paper beng fcused n cde generatn and schedulng prblems that are f a glbal nature, we d nt gve prvsns fr ntercnnectng dataflw specfcatns. Our frmalsm nly allws the specfcatn f cmplete systems, where acqustn f data and actuatn s represented wth cmputatn ndes (nn-determnstc fr the sensng part). Hwever, extendng the frmalsm t allw cmpstn can be easly dne. Derved dataflw blcks. The semantcs f ur frmat wll be drectly defned fr the prevusly-defned prmtve dataflw cnstructs. Hwever, we allw the defntn f derved dataflw cnstructs that serve as syntactc sugar at specfcatn tme, and whch may be drectly used (fr effcency purpses) by analyss and ptmzatn algrthms. The defntn f a derved dataflw blck ncludes the syntax f the blck, and ts semantcs under the frm f an expansn ver prmtve dataflw. Fg. 3 prvdes ne example f derved blck: the classcal memry cell that can be wrtten and read at dffer- (a) c \ c (b) Fgure 3: The memry cell wrtten n clck c and read n clck c : graphcal representatn (a) and semantcs by expansn (b). ent rates (as ppsed t the synchrnzng message passng phlsphy f delays). 3 Its defntn by expansn s gven n Fg. 3, and als shws the frm f ur dataflw specfcatns. 3.3 Example We gve n Fg. 4 the ntermedate representatn crrespndng t the smple SynDEx synchrnus specfcatn f Fg. 5. The specfcatn represents a system wth tw swtches (Blean nputs) cntrllng ts executn: hghspeed (HS) vs. lw-speed (), and fal-safe (F S) vs. nrmal peratn ( FS). In the lw-speed mde, mre peratns can be executed, whereas n the fal-safe mde the peratn that gets executed (N) des nt use any f the nputs, because the sensrs r treatment chan are assumed t be faulty (cntrl s dne usng default values). The behavr f ur CG representatn s: Ndes F S IN and HS IN have clck true, s they are executed at each executn cycle t read FS and HS. If HS = false then clck s true fr the nstant, whch trggers the executn f F1, fllwed by F2 and F3. Otherwse, execute G (n clck HS). Clck dependences, such as clck HS dependng n the utput prt HS IN.HS, are nt explct. Bth F1 and G are cmputng thrugh ther utput prts named the SynDEx-level utput value f the herarchcal cndtnal nde C1. The executn f M (n clck FS) can start after s receved frm ether F1 r G. The executn f N can start as sn as we can determne that F S s true fr the nstant. Dataflw blcks havng n dependency between them can be executed n parallel. Fr nstance, f FS = true then N can be executed as sn as FS s read, ndependently f the executn f F1, F2, F3, r G. On the cntrary, the cmputatn f M must wat untl bth FS and have arrved. 3.4 Clcked graph semantcs The prevusly-defned frmalsm allws the representatn f prgrams wrtten n languages such as Esterel [8], Scade/Lustre [9], Sgnal [4], r dscrete Sccs [10]. In partcular, t s flexble enugh t allw the defntn f semantcs cmpatble t the semantcs f the afrementned 3 The functnng f the memry element s as fllws: Whenever readng and wrtng ccur n the same synchrnus nstant, the nput value s drectly cped t the utput, hence the c c clck n the arc between the tw dentty blcks. When readng ccurs wthut wrtng (clck c \c ), the value s taken frm the delay element. Each wrte updates the value f the delay (clck c ). In nstants where the cell s read, but nt wrtten (clck c \c ), we need t explctly refresh ts delay value (the lpback arc frm the utput t the nput f the delay).

5 true FS = 10 FS FS IN F1 F2 F3 N READ INT true HS HS IN HS G FS HS FS FS M Fgure 6: A glbally nn-causal example Fgure 4: Example f specfcatn n ur frmalsm FS IN FS HS HS IN HS C1 F1 G F2 V F3 F S Fgure 5: Crrespndng SynDEx specfcatn languages. Hwever, ur gal s the defntn f effcent mplementatns, s we are nt nly nterested n specfcatn crrectness. Indeed, the remander f the paper s mstly dedcated t the defntn at the level f ur ntermedate representatn f: Intrnsc crrectness prpertes f the specfcatn that shuld be ncluded n all the semantcs assgned t the frmat. Classcal crrectness prpertes used n synchrnus prgram analyss, such as causalty and clck cnsstency, fall n ths categry. External crrectness prpertes ensurng cmpatblty wth the desred mplementatn archtecture, ncludng bth hardware and sftware aspects. Such prpertes are: The absence f reactn t sgnal absence [19], whch ensures that a dstrbuted mplementatn can be cnstructed that uses absence f messages t encde the sgnal absence f the synchrnus mdel. Endchrny [3], whch ensures the exstance f a statc schedule, whch can be cmputed fflne. Real-tme schedulablty [20], whch ensures that a schedule exsts satsfyng the desred real-tme cnstrants. These prpertes reman cmpatble wth the semantcs f the hgh-level prgrammng languages, n the sense where they dentfy (effcently) mplementable sub-classes f semantcally crrect prgrams. At the same tme, hwever, the defntn f these prpertes requres the refnement f the CG specfcatn nt a real-tme mplementatn. In ths sectn we nly defne sme f the ntrnsc crrectness prpertes crrespndng t the synchrnus hypthess. The next sectns shall cntnue wth the ntrductn f endchrny and schedulng prpertes. F S C2 M N T ensure cmplance wth the synchrnus hypthess and the atmcty assumptn fr nde executns, the cmputatn f the dataflw ndes must satsfy at each executn nstant 3 crrectness prpertes: N unntalzed data: All the nputs f a nde n are cmputed and transmtted n nstants where n s executed. Frmally, we requre that: fr all n N and fr all I(n) we have: _ clk(n) clk(a) a A,dest(a)= fr all a A we have clk(a) clk(src(a)). Nte that we allw data t be cmputed and transmtted n nstants where t s nt needed. Sngle assgnment: Each nput f a nde n s receved frm at mst ne surce at each executn nstant (n wrte cnflct s pssble). Frmally, we requre that fr all a 1, a 2 A wth dest(a 1) = dest(a 2) we have clk(a 1) clk(a 2) = false. N causalty cycle: All cycles n the dataflw graph ether cntan a delay nde, r have the cnjunctn f all cndtns f all arcs equal t false. Ths cndtn, specfc t the synchrnus apprach, ensures that the cmputatn f each cycle can be perfrmed n bunded tme. A gd abstractn f the last cndtn s the absence f cycles that cntan n delay. Hwever, the acyclcty f the dataflw s nt suffcent t ensure by tself the causal crrectness f a specfcatn. Indeed, the cmputatn f the clcks may nduce addtnal causal dependences. Fr nstance,we want t reject specfcatns such as the ne n Fg. 6, where the utput f a sensr () s used t cmpute ts clck. We deal wth these ssues n the next sectn. 4. EFFICIENT IMPLEMENTATION: USING ENDOCHRONY We explaned n the ntrductn that endchrny [3] s a schedulng-ndependence prperty allwng us t encde sgnal absence wth absence f messages. By cnsequence, endchrny allws us t perfrm n cmputatn n parts f the system that are semantcally nactve (smethng whch s nt pssble n the general synchrnus mdel). Mrever, endchrny ensures that an asynchrnus smulatn f the specfcatn gves the same results as the synchrnus ne. Thus, endchrny dentfes synchrnus specfcatns that allw a determnstc and effcent mplementatn ver asynchrnus mplementatn archtectures. We ntrduce n ths sectn a ntn f endchrnus clcked graph (CGe) that cmbnes endchrny wth dataflw acyclcty usng a ntn f endchrnus clck whch we defne. The chce s natural, because (1) endchrny s a

6 suffcent prperty ensurng the statc schedulablty f the cmputatns n a synchrnus specfcatn, and (2) glbal acyclcty s a suffcent cndtn whch can be checked usng lw-cmplexty algrthms and ensures the absence f causalty cycles. 4.1 Clck wth dependences The defntn f endchrnus clcked graphs s based n asscatng t each clck f the clcked graph a data supprt the set f all the utput prts used n ts cmputatn, alng wth the clcks defnng the nstants where these utput prts are needed. In practce, ths means that each dataflw element (nde r arc) x s assgned nt just a clck clk(x), but als a supprt supp(x). We call clcks wth dependences the pars < clk(x), supp(x) > frmed f a clck and ts supprt. The supprt f a clck wth dependences c s a set f where s an utput prt f sme nde n, and c s a clck defnng the nstants where the value f s used n the cmputatn f c. We call the the samplng f n the clck c. Intutvely, the supprt f a clck gves suffcent data fr sme algrthm t cmpute the clck. Fr nstance, a gd supprt fr the clck c = ( 1 = 3) ( 2 = 5) s { 1@true, 2@( 1 = 3)} whch crrespnds t the fllwng cmputatn f c: c = false ; read(1) ; f(1 == 3){ read(2) ; f(2 == 5) c = true } Nte that a gven clck can have several supprts. Fr nstance, the clck c defned abve als accepts { 2@true, 1@( 2 = 5)} generatrs: the prts and arcs f the dataflw graph, defned by the as a supprt. Of curse, nt all pars frmed f a clck and a supprt p a fr all utgng arc a f a prt p are meanngful. Fr nstance, < a = 3, {a@(01) } > s nt, a p fr all ncmng arc a f a prt p because a s needed fr the clck cmputatn at all nstants, nt just nce every tw nstants, as t s specfed n the supprt. T dentfy meanngful clcks, we ntrduce the gen- supp(x) fr sme c x fr all utput prt and prt r arc x such that eratn relatn s c statng that c can be cmputed frm fr all nput prt and utput prt f a nde the utput prt samplngs f s. Ths relatn s nductvely n that s nt a delay defned by the fllwng rules: 1. w (w p), fr all w, w p {0, 1} 2. { 1@true,..., B( 1,..., k ), fr all Blean functn B f arguments 1,..., k 3. f s c then s c 4. f s 1 c 1 and s 2 c 2 then s 1 s 2 c 1 p c 2 fr all bnary Blean peratr p 5. f s 1 c 1 and s 2 c 2, then s 1 {@c s 2} c 1.c 2 6. f s c 1 s and c 2 c 1, then (s \ {@c 1}) {@c 2} c 7. f c 1 = c 2 and s c 1 then s c 2. The frst 5 rules naturally buld a supprt fr any clck by nductvely fllwng ts syntax. Rule 6 states that havng mre nfrmatn than s strctly necessary des nt affect cmputablty. Rule 7 s the mst dffcult. It states that f tw syntaxes c 1 and c 2 represent the same clck n the clck algebra, then a supprt generatng c 1 als generates c 2 (meanng that the algrthm used t cmpute c 1 can be used fr c 2). 4.2 Endchrnus clck Nte that the defntn f a clck wth dependences may nvlve recursve cmputatns f ther clcks. T ensure that the recursve cmputatn prcess s fnte, we ntrduce the ntns f endchrnus supprt and endchrnus clck. We shall say f a supprt s that t s endchrnus whenever we can asscate t s a subset dep (N,A) s (@c) f s such that: dep (N,A) s (@c) c The dependency sets nduce a dependency partal rder ver the supprt set s (there are n cyclc dependences) Intutvely, ths means that there are sme samplngs n s whse clcks depend n n utput prts. Once read, the crrespndng utput prts allw the cmputatn f new clck samplngs, a.s.. untl all the clcks f the samplngs have been cmputed and all crrespndng utput prts read. N cyclc cmputatn s pssble. We say that a clck wth dependences < c, s > s endchrnus whenever s s endchrnus and s c. Nte that the frst 5 rules f the prevus sectn can be used t autmatcally transfrm any clck nt an endchrnus ne, by assgnng t a supprt. 4.3 Endchrnus clcked graph Cnsder nw a clcked graph where all clcks are clcks wth dependences. We ntrduce a prerder ver the Wth ths defntn, we shall say that the clcked graph s endchrnus f, by defntn: s a partal rder relatn, and belngs t the supprt f sme clck and s an utput f nde n, then c clk(n) Ths crtern ensures a strng frm f causal crrectness, amuntng t acyclcty (ncludng the cmputatn f the clcks), and ensurng the exstence f a statc schedule f all the peratns (ncludng the cmputatn f the clcks). 5. SCHEDULING CLOCKED GRAPHS In ths sectn, we prvde a methd fr buldng dstrbuted real-tme mplementatns f endchrnus clcked graphs. The defntn f the methd s ntended t shw that the ur mdel supprts a realstc real-tme mplementatn technque. Therefre, t s restrcted t the smple bus-based dstrbuted archtectures defned n the ntrductn. Extensns t cver mre cmplex mplementatn archtectures wth mre cmplex ntercnnect tplges and dfferent bus types (tme-trggered, uncast) are the bject f ngng wrk.

7 HS IN=1 FS IN=1 P 1 F1=3 F2=8 Asynchrnus bradcast bus M=3 P 3 N=3 F3=2 G=3 P 2 F3=3 blean=2 V type=2 type=5 Fgure 7: Hardware archtecture We fllw the SynDEx apprach [11] by cmputng a schedule fr ne executn cycle, the glbal schedulng beng an nfnte repettn f the schedulng f a cycle. Ths crrespnds t the case where the cmputatns f the dfferent cycles d nt verlap n tme n the real-tme mplementatn. 4 Our schedulng methd uses a greedy heurstc nspred frm AAA/SynDEx, but deals wth clcks n a fner way, ptentally resultng n better real-tme schedules. The remander f the sectn s structured n three man parts. We frst defne the tmng nfrmatn used as nput fr ur schedulng technque. Then, we ntrduce a mdel f scheduled clcked graph (CGsch), btaned by decratng endchrnus clck graphs wth spatal and tempral allcatn nfrmatn. We als defne suffcent cndtns ensurng that the allcatn nfrmatn f an CGsch s cmpatble wth bth the clcks f the ntal endchrnus clcked graph and the underlyng hardware archtecture. The secnd part ntrduces a smple schedulng technque generatng schedules that satsfy the prevusly-defned crrectness (cmpatblty) prpertes. Ths last part ncludes a bref cmparsn wth the utput f AAA/SynDEx. 5.1 Tmng nfrmatn We explaned n the ntrductn that we cnsder n ths paper smple dstrbuted archtectures frmed f a unque asynchrnus r statc TDMA message-passng relable bradcast bus dented B that cnnects a set f sequental prcessrs P = {P = 1..n}. Fg. 7 pctures an archtecture frmed f 3 prcessrs cnnected t the central bus. The archtecture s decrated wth tmng nfrmatn that specfes: The dataflw functns that can be executed by each prcessr, and ther duratn n that prcessr. Each prcessr has a lst f tmng nfrmatn f the frm nde name=duratn. The cmmuncatn peratns that can be executed by the bus (the data types that can be sent atmcally), and the duratns f the cmmuncatns, assumng the bus s free. The bus has a lst f tmng nfrmatn f the frm data type=duratn. The duratns prvded fr cmputatns and cmmuncatns must be upper bunds btaned by sme wrst-case executn tme (WCET) analyss. Tmng nfrmatn fr ne atmc nde can be present n several prcessrs, t 4 The results f ths paper can be extended t the case where cycles can verlap by cnsderng mdul schedulng technques. dente the fact that the nde can be executed by several prcessrs. Fr nstance, nde F3 can be executed n P2 wth duratn 3, and n P3 wth duratn 2. We assume that wrtng a delay, readng a delay, and lcal cmmuncatns (that d nt use the bus) take n tme. We shall dente wth d P(n) the duratn f cmputatn nde n n prcessr P. T represent the fact that a prcessr P cannt perfrm cmputatn n, we set d P(n) =. We dente wth d B(D) the duratn f a cmmuncatn f a value f type D ver the bus (n the absence f all nterference). 5.2 Scheduled clcked graph In ths sectn we ntrduce ur mdel f scheduled clcked graph, and gve suffcent cndtns ensurng that t crrectly mplements the semantcs f the gven endchrnus clcked graph. By defntn, a scheduled clcked graph s an endchrnus clcked graph (N, A) alng wth a schedule S f ts elements ver the ressurces f the chsen archtecture. Such a schedule s frmed f: An allcatn f the delays t prcessrs determnng n whch prcessr s stred the delay value between executn cycles: S : N P A set f scheduled functns assgnng a prcessr and a real-tme date (an nteger) t each cmputatn f the dataflw: S C : N C P N A set f scheduled cmmuncatns assgnng t each arc f the dataflw the emtter prcessr, a real-tme date, and an effectve cmmuncatn clck: S A : A P N C Fr each element f the graph x N A, a set f scheduled cmmuncatns assgnng t each sampled utput f the supprt supp(x) an emtter prcessr, a real-tme date, and an effectve cmmuncatn clck: S x : supp(x) P N C Fr cnvenence, we dente wth: t x the real-tme date asscated by S t any cmputatn nde, arc, r sampled utput f sme supprt. Res(x) the prcessr asscated wth each nde, arc, r sampled utput f sme supprt (the executn prcessr fr dataflw functns, the strage prcessr fr delays, and the emtter prcessr fr arcs and supprt elements). e clk(x) the effectve cmmuncatn clck asscated wth an arc r sampled utput. d(n) = d Res(n) (n) the duratn f a scheduled cmputatn nde n. d(x) = d B(D x) the duratn f the scheduled cmmuncatn f an arc r sampled utput x.

8 We say that the schedule S s partal when ether S r S C s partal. 5 When S s a partal schedule f (N, A), then we allw ts ncremental cmpletn usng the fllwng peratr: If S (δ) s undefned, then we dente wth S {δ P } the partal schedule wth (S {δ P }) (δ) = P, and whch equals S everywhere else. Smlarly, we defne S {n (P, t)} whenever S C(n) s undefned, S {a (P, t, c)} when S A(a) s undefned, and S {@c (P, t, c)} when S x(@c ) s nt defned. Our defntn mples that cmputatns are executed n the specfcatn clck (the schedule defnes n new clck). Hwever, cmmuncatns can be realzed n a dfferent clck, t avd cases where a data s transmtted twce n the bus n the same executn nstant. In ths paper, we nterpret the real-tme date asscated t cmmuncatns and cmputatns as the latest (wrst-case) real-tme date at whch the executn f the cmmuncatn r cmputatn wll start. Nte that the defntn f S B mplctly assumes that we make n use f specalzed synchrnzatn messages, nr data encdng. We als assume that each peratn s scheduled exactly nce n S, meanng that n ptmzng replcatn such as nlnng s dne. Ths hypthess s cmmn n real-tme schedulng. 5.3 Cnsstency f an CGsch The prpertes f ths sectn frmalze the cmpatblty between the dates and ressurce allcatns f a scheduled clcked graph and the lgcal clcks f the underlyng endchrnus clcked graph. These prpertes depend n chsen target archtectures, and extendng the schedulng technques t new archtectures cnssts n defnng new cnsstency prpertes Avalablty functns Cnsder a schedule S f the endchrnus clcked graph (N, A). The executn cndtn defnng the executn cycles where the value f an utput prt s sent n the bus befre date t s dented clk S (, t, B) =, and s defned as the unn f all the clcks e clk(x), where e ranges ver: the arcs a A wth src(a) = that have been scheduled such that t a + d B(a) t the sampled supp(y) (fr sme arc r nde y) that have been scheduled (S x(@c)) such that + d B(@c) t. Obvusly, clk S (, t, B) s the executn cndtn gvng the cycles where s avalable system-wde at all dates t t. Assumng s a prt f nde n, we als defne the executn cndtn clk S (, t, P) defnng the cycles where s avalable n P at date t: If n s nt allcated n P (Res(n) P), then clk S (, t, P) = clk S (, t, B) If n s a delay nde allcated n P (Res(n) = P), then clk S (, t, P) = clk(n), meanng that the value s 5 Cmmuncatn arcs may reman unassgned, fr nstance when they represent lcal cmmuncatns fr whch n cde s necessary. avalable frm the begnnng f all executn nstants f n. If n s a cmputatn nde allcated n P at date t n, then clk S (, t,p) s clk(n) f t t n + d P(n), and false f nt. If c s a clck wth c clk(n), then we dente wth ready date(p,,c) the mnmum t such that clk S (, t, P) c, and wth ready date(b,,c) the mnmum date t such that clk S (, t, B) c. Nte that clk S (,, R) s the clck gvng the nstants where becmes avalable at sme pnt n ressurce R Cnsstency prpertes The fllwng prpertes defne the cnsstency f a statc schedule S wth the underlyng endchrnus clcked graph (N, A) and the tmng nfrmatn that was prvded. Ths cncludes the defntn f ur mdel f real-tme schedule, and allws us t reasn abut the crrectness f the smple schedulng algrthm defned n the next sectn. Exclusve resurce use. A prcessr r bus cannt be used by mre than ne peratn at a tme. Frmally: On prcessrs: If n 1 and n 2 are dfferent scheduled cmputatn ndes wth clk(n 1) clk(n 2) false, then ether t n1 (t n2 + d P(n 2)) r t n2 (t n1 + d P(n 1)). On the bus: If x 1 and x 2 are dfferent scheduled arcs r sampled utputs wth e clk(x 1) e clk(x 2) false, then ether t x1 (t x2 +d B(x 2)) r t x2 (t x1 +d B(x 1)). Causal crrectness. Intutvely, t ensure causal crrectness ur schedule must ensure n a statc fashn that when a cmputatn r cmmuncatn s usng the value f an utput prt at tme t n executn cndtn c, the prt value has been cmputed r transmtted n the bus at a prevus tme and n a greater executn cndtn. Frmally: 1. If S C(n) = (P, t) s defned fr a nde n, then: clk S (, t, P) c fr supp(n) clk S (, t, P) c fr supp(a) f dest(a) s an nput prt f n clk S (src(a), t, P) clk(a) fr all arc a wth dest(a) beng an nput prt f n 2. T derve the rule ensurng that a delay has enugh nput at the end f an nstant, we smply set n the prevus rules the date t. Mre precsely, f S (n) = P s defned fr a delay nde δ, then: clk S (,, P) c fr supp(δ) clk S (,, P) c fr supp(a) f dest(a) s an nput prt f δ clk S (src(a),, P) clk(a) fr all arc a wth dest(a) beng an nput prt f δ 3. If S A(a) = (P, t a, c a) s defned fr an arc a wth c a false and f n a s the surce nde f a, then: clk S (, t, B) c fr supp(a)

9 S C(n a) s defned and Res(n a) = P and t na + d na ( )t a 4. Assume that x N A, supp(x), and that s a nde f n. Then, f S x(@c) = (P, t, c 1) s defned wth c 1 false we have: c 1 s generated by the data that has already transted the bus befre date t (the set f S (, t, B) where ranges ver all the utput prts f the system. clk S (, t, B) c fr dep S x (@c) Functn 1 SchedulngDrver Input: (N, A): endchrnus clcked graph tmng nfrmatn Output: S: full schedule S whle exsts n wth S C(n) undefned d chse such an n mnmal n the sense f fr all P prcessr wth d P(n) d (S P,t P ) ScheduleOneNde(S,n, P) Assgn t S the S P that mnmzes t P return 5.4 Schedulng algrthm Our schedulng algrthm s a smple heurstc nspred frm the ne f SynDEx, and whch wrks n the prmtve subset f ur frmat. It wrks by schedulng ne dataflw nde at a tme n the prcessr that mnmzes ts cmpletn date. The man schedulng rutne s Functn 1. Schedulng a nde n n a gven prcessr p s realzed by Functn 2, and cnssts n: (1) schedulng the cmmuncatns allwng the cmputatn f clk(n), (2) schedulng the cmmuncatns allwng the acqustn f all nputs, and (3) schedulng the nde at the earlest pssble date. The auxlary functn FrstAvalable(S, R, t, c, d) returns the frst slt f duratn d avalable n resurce R after date t and n the cndtn c. Functn 2 ScheduleOneNde Input: S: partal schedule, P: target prcessr n: yet unscheduled cmputatn nde (the clcked graph and tmng nfrmatn are assumed glbal) Output: S: schedule (partal r nt), t: date n P where n cmpletes ts executn (S, t) ScheduleEndSupprt(S, P, supp(n)) fr all ncmng arc f n d (S,t ) ScheduleEndSupprt(S, P, supp(a) {src(a)@clk(a)}) t max(t,t ) t FrstAvalable(S,P, t, c, d P(n)) S S {n (P, t)} ; t t + d P(n) return The real cmplexty f the schedulng algrthm s hdden n Functn 3 whch schedules the cmmuncatns whch ensure that a gven endchrnus supprt s avalable n a gven prcessr P. As explaned n the ntrductn, ur algrthm can handle asynchrnus r statc TDMA buses. The nly dfference Functn 3 ScheduleEndSupprt Input: S: partal schedule, P: target prcessr s = { 1@c 1,..., n@c n}: endchrnus supprt set such that fr all k { 1@c 1,..., k } c k+1 (the clcked graph and tmng nfrmatn are assumed glbal) Output: S: schedule (partal r nt), t: date n P where the data n the supprt set becme avalable t 0 ; k n ; flag true whle flag d f clk S ( k,, P) c k then t max(t,ready date(p, k,c k )) ; k k 1 else f k utput f a delay δ nt yet allcated then S S {δ P } ; k k 1 else flag false fr j := 1 t k d d f clk S ( j,, B) < c j then t 0 max(ready dep S s (j@cj)) Assgn t c the unn f all effectve clcks c f bus cmmuncatns f j such that c c j false, and t t the greatest date f these cmmuncatns. t 0 max(t 0, t ) t 0 FrstAvalable(S, B, t 0, c j \ c, d B( j)) Let n j be the surce prcessr f j S S { j@c j (n j, t 0, c j \ c )} t max(t,ready date(b, j,c j)) return between the tw cases s the FrstAvalable functn whch gves a slt where sme peratn can be allcated. Our algrthm, hwever, s better adapted t asynchrnus archtectures, because the generated schedule des nt take advantage f the tme trggers f a TDMA archtecture. The utput f the schedulng fr the example n Fg. 4 and an asynchrnus bus s gven n Fg. 8. We smplfed the ntatns fr space reasns. The fgure als gves the result f SynDEx fr the same example (whch s wrse, because f the carser clck manpulatns). The wdth f an peratn (ts supprt) nsde ts lane ntutvely represents ts executn cndtn (the larger t s, the mre ts executn cndtn s smple). Much lke n Venn dagrams, the lgcal relatns between executn cndtns f varus peratns are gven by the hrzntal verlappng f supprts. 6. CONCLUSION We have ntrduced a new methd fr the dstrbuted real-tme mplementatn f synchrnus specfcatns. Our methd s bult arund a new clcked graph ntermedate representatn, and wrks as a seamless seres f transfrmatns that add causalty, tme refnement r allcatn nfrmatn n the clcked graph ndes and arcs. Endchrny, a schedulng-ndependence prperty related t the Kahn prncple and the ntn f cnfluence, s used as a crtern ensurng effcent mplementablty. Endchrnus clcked graphs are transfrmed nt scheduled graphs by assgnng real-tme dates and ressurces t ther elements. We defned the crrectness f such a schedule graph, and prvded an algrthm fr the schedulng f endchrnus clcked graphs n dstrbuted archtectures bult arund a sngle asynchrnus bus.

10 tme P1 0 HS IN@true 1 FS IN@true 2 3 F1@(HS=false) F2@(HS=false) Generated by ur technque P2 G@HS=true P3 Bus F3@(HS=false) Send(P1,HS)@true Send(P1,FS)@true FS=false) HS=true) Generated by SynDEx (dfferent lanes) P3 F3@(HS=false) Bus Send(P1,HS)@true Send(P1,FS)@true Fgure 8: The real-tme schedules generated by ur algrthm and by SynDEx. We nly fgure fr the SynDEx schedule the lanes that dffer frm urs. Tme flws frm tp t bttm. We gve here the schedule fr ne executn cycle. An executn f the system s an nfnte repettn f ths pattern. The wdth f an peratn nsde ts lane ntutvely represents clck nclusn and exclusn prpertes. We are currently fcusng n the extensn f the frmalsm and schedulng technques t cver (1) mult-perd mplementatns where all the cmputatns and cmmuncatns are nt bund t a sngle glbal clck, and (2) larger classes f mplementatn archtectures, such as tmetrggered nes. 7. REFERENCES [1] Nclas Halbwachs. Synchrnus Prgrammng f Reactve Systems. Kluwer academc Publshers, [2] Albert Benvenste, Paul Casp, Stephen A. Edwards, Nclas Halbwachs, Paul Le Guernc, and Rbert de Smne. The synchrnus languages 12 years later. Prceedngs f the IEEE, 91(1):64 83, January [3] A. Benvenste, B. Callaud, and P. Le Guernc. Cmpstnalty n dataflw synchrnus languages: Specfcatn and dstrbuted cde generatn. Infrmatn and Cmputatn, 163: , [4] P. Le Guernc, J.-P. Talpn, and J.-C. Le Lann. Plychrny fr system desgn. Jurnal fr Crcuts, Systems and Cmputers, Aprl Specal Issue n Applcatn Specfc Hardware Desgn. [5] D. Ptp-Butucaru, B. Callaud, and A. Benvenste. Cncurrency n synchrnus systems. Frmal Methds n System Desgn, 28(2): , March [6] R. Mlner. Cmmuncatn and Cncurrency. Prentce Hall, [7] G. Kahn. The semantcs f a smple language fr parallel prgrammng. In J.L. Rsenfeld, edtr, Infrmatn Prcessng 74, pages Nrth Hlland, [8] D. Ptp-Butucaru, S. Edwards, and G. Berry. Cmplng Esterel. Sprnger, [9] N. Halbwachs, P. Casp, P. Raymnd, and D. Plaud. The synchrnus dataflw prgrammng language Lustre. Prceedngs f the IEEE, 79(9): , [10] S. Campbell, J.-P. Chanceler, and R. Nkukhah. Mdelng and Smulatn n Sclab/Sccs. Sprnger, [11] T. Grandperre and Y. Srel. Frm algrthm and archtecture specfcatn t autmatc generatn f dstrbuted real-tme executves. In Prceedngs MEMOCODE, [12] R. Obermesser. Event-Trggered and Tme-Trggered Cntrl Paradgms. Sprnger, [13] A. Benvenste, B. Callaud, L. Carln, P. Casp, and A. Sangvann-Vncentell. Cmpsng hetergeneus reactve systems. ACM TECS, 7(4), [14] P. Amagbégnn, L. Besnard, and P. Le Guernc. Implementatn f the data-flw synchrnus language sgnal. In Prceedngs PLDI, [15] A. Kunturs and C. Wlnsk. Effcent schedulng f cndtnal behavrs fr hgh-level synthess. ACM Transactns n Desgn Autmatn f Electrnc Systems, 7(3): , July [16] Z. Gu, X. He, and M. Yuan. Optmzatn f statc task and bus access schedules fr tme-trggered dstrbuted embedded systems wth mdel-checkng. In Prceedngs DAC, [17] W. Zheng, J. Chng, C. Pnell, S. Kanajan, and A. Sangvann-Vncentell. Extensble and scalable tme trggered schedulng. In Prceedngs ACSD, [18] P. Casp, A. Curc, A. Magnan, C. Sfrns, S. Trpaks, and P. Nebert. Frm smulnk t scade/lustre t tta: a layered apprach fr dstrbuted embedded applcatns. In Prceedngs LCTES, [19] D. Ptp-Butucaru, R. de Smne, and Y. Srel. Necessary and suffcent cndtns fr determnstc desynchrnzatn. In Prceedngs EMSOFT 07, Salzburg, Austra, Octber [20] C. L. Lu and J. Layland. Schedulng algrthms fr multprgrammng n a hard real-tme envrnment. Jurnal f the ACM, 20(1):46 61, January 1973.