VNH3SP30 FULLY INTEGRATED H-BRIDGE MOTOR DRIVER

Transcription

1 VNH3SP3 FULLY INTEGRATED H-BRIDGE MOTOR DRIVER TYPE R DS(on) (*) I OUT V CCmax VNH3SP3 34mΩ 3 A 4 V (*) Typical per leg at 5 C OUTPUT CURRENT:3 A 5V LOGIC LEVEL COMPATIBLE INPUTS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN OVERVOLTAGE CLAMP THERMAL SHUT DOWN CROSS-CONDUCTION PROTECTION LINEAR CURRENT LIMITER VERY LOW STAND-BY POWER CONSUMPTION OPERATION UP TO KHz PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF V CC MultiPowerSO-3 DESCRIPTION The VNH3SP3 is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic HSD and two Low-Side switches. The HSD switch is designed using STMicroelectronics VIPower M-3 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/protection circuitry. The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronics proprietary EHD ( STripFET ) process. BLOCK DIAGRAM V CC OVERTEMPERATURE A O V + U V OVERTEMPERATURE B CLAMP A CLAMP B HS A DRIVER LOGIC DRIVER HS B HSA HS B CURRENT LIMITATION A CURRENT LIMITATION B LS A DRIVER DRIVER LS B LSA LS B GND A DIAG A /EN A IN A IN B DIAG B /EN B GND B April 4 /6

2 The three dice are assembled in MultiPowerSO-3 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals IN A and IN B can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A /EN A or DIAG B /EN B, when connected to an external pull CONNECTION DIAGRAM (TOP VIEW) up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 7. The, up to KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the pin will turn off both the LS A and LS B switches. When rises to a high level, LS A or LS B turn on again depending on the input pin state. Nc Vcc Nc Heat Slug3 3 Nc GND A GND A IN A EN A /DIAG A Nc Nc EN B /DIAG B IN B Nc Vcc Nc V CC Heat Slug Heat Slug 5 6 GND A Nc Vcc Nc GND B GND B GND B Nc PIN DEFINITIONS AND FUNCTIONS PIN No SYMBOL FUNCTION, 5, 3, Heat Slug Source of High-Side Switch A / Drain of Low-Side Switch A, 4,7,9,,4,7,, 4,9 NC Not connected 3, 3, 3 VCC, Heat Slug Drain of High-Side Switches and Power Supply Voltage 5 IN A Clockwise Input 6 EN A /DIAG A Status of High-Side and Low-Side Switches A; Open Drain Output 8 Input 9 NC Not connected EN B /DIAG B Status of High-Side and Low-Side Switches B; Open Drain Output IN B Counter Clockwise Input 5, 6,, Heat Slug3 Source of High-Side Switch B / Drain of Low-Side Switch B 6, 7, 8 GND A Source of Low-Side Switch A (*) 8, 9, GND B Source of Low-Side Switch B (*) (*) Note: GND A and GND B must be externally connected together /6

3 PIN FUNCTIONS DESCRIPTION NAME V CC GND A GND B IN A IN B EN A /DIAG A EN B /DIAG B DESCRIPTION Battery connection. Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to V CC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible. Gates of Low-Side FETS get modulated by the signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins. These pins must be connected to an external pull up resistor.when externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). BLOCK DESCRIPTIONS (see Electrical Block Diagram page 4) NAME LOGIC CONTROL OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION DESCRIPTION Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [5.5V..36V] for the battery voltage. Protect the High-Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a good R DS(on) for the leg of the bridge. In case of short circuit for the High-Side switch, limits the motor current by reducing its electrical characteristics. In case of short-circuit with the increase of the junction s temperature, shuts-down the concerned High-Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin. 3/6

4 ABSOLUTE MAXIMUM RATING Symbol Parameter Value Unit V CC Supply voltage V I max Maximum output current (continuous) 3 A I R Reverse output current (continuous) -3 A I IN Input current (IN A and IN B pins) +/- ma I EN Enable input current (DIAG A /EN A and DIAG B /EN B pins) +/- ma I pw input current +/- ma V ESD Electrostatic discharge (R=.5kΩ, C=pF) - Logic pins - Output pins:,, V CC 4 5 KV kv T j Junction operating temperature Internally Limited C T c Case operating temperature -4 to 5 C T STG Storage temperature -55 to 5 C CURRENT AND VOLTAGE CONVENTIONS I CC V CC I INA I INB I ENA IN A IN B V CC I OUTA I OUTB V OUTA I ENB DIAG A /EN A V OUTB DIAG B /EN B GND A GND B I pw GND V INA V INB V ENA V ENB V pw I GND 4/6

5 THERMAL DATA See MultiPowerSO-3 Thermal Data section. ELECTRICAL CHARACTERISTICS (V CC =9V up to 8V; -4 C<T j <5 C; unless otherwise specified) POWER Symbol Parameter Test Conditions Min Typ Max Unit V CC Operating supply voltage V R ONHS On state high side resistance I LOAD =A; T j =5 C 3 3 mω R ONLS On state low side resistance I LOAD =A; T j =5 C 5 mω R ON On state leg resistance I LOAD =A 9 mω I s Supply current ON state; V INA =V INB =5V 5 ma OFF state 4 µa V f High Side Free-wheeling Diode Forward Voltage I f =A.8. V I L(off) High Side Off State Output Current (per channel) SWITCHING (V CC =3V, R LOAD =.Ω) PROTECTION AND DIAGNOSTIC T j =5 C; V OUTX =EN X =V; V CC =3V T j =5 C; V OUTX =EN X =V; V CC =3V Symbol Parameter Test Conditions Min Typ Max Unit f frequency khz t D(on) Turn-on delay time Input rise time < µs (see fig. 3) 3 µs t D(off) Turn-off delay time Input rise time < µs (see fig. 3) µs t r Output voltage rise time (see fig. ).5 3 µs t f Output voltage fall time (see fig. ) 5 µs t DEL Delay time during change of operation mode (see fig. ) 6 8 µs Symbol Parameter Test Conditions Min Typ Max Unit V USD Undervoltage shut-down 5.5 V V OV Overvoltage shut-down V I LIM Current limitation 3 45 A T TSD Thermal shut-down temperature V IN = 3.5 V 5 7 C T TR Thermal Reset Temperature 35 C T HYST Thermal Hysteresis 7 5 C 3 5 µa µa 5/6

6 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions Min Typ Max Unit V pwl low level voltage.5 V I pwl Low level pin current V pw =.5V µa V pwh high level voltage 3.5 V I pwh High level pin current V pw =3.5V µa V pwhhyst hysteresis voltage.5 V V pwcl clamp voltage I pw = ma V CC +.3 V CC +.7 V CC +. V I pw = - ma V V pwtest Test mode pin voltage V I pwtest Test mode pin current V pwtest = -.V - -5 µa LOGIC INPUT (IN A /IN B ) Symbol Parameter Test Conditions Min Typ Max Unit V IL Input low level voltage.5 V I INL Input current V IN =.5V µa V IH Input high level voltage 3.5 V I INH Input current V IN =3.5V µa V IHYST Input hysteresis voltage.5 V V ICL Input clamp voltage I IN =ma V I IN =-ma V ENABLE (LOGIC I/O PIN) Symbol Parameter Test Conditions Min Typ Max Unit V ENL Enable low level voltage Normal operation (DIAG X /EN X pin acts as an.5 V input pin) I ENL Low level Enable pin current V EN =.5V µa V ENH I ENH V EHYST V ENCL V DIAG Enable high level voltage High level Enable pin current Enable hysteresis voltage Enable clamp voltage Enable output low level voltage Normal operation (DIAG X /EN X pin acts as an input pin) 3.5 V V EN = 3.5V µa Normal operation (DIAG X /EN X pin acts as an input pin) I EN =ma I EN =-ma Fault operation (DIAG X /EN X pin acts as an input pin) I EN = ma.5 V V V.4 V 6/6

7 WAVEFORMS AND TRUTH TABLE TRUTH TABLE IN NORMAL OPERATING CONDITIONS In normal operating conditions the DIAG X /EN X pin is considered as an input pin by the device. This pin must be externally pulled high. IN A IN B DIAG A /EN A DIAG B /EN B Comment H H Brake to V CC H L Clockwise L H Counter cw L L Brake to GND pin usage: In all cases, a on the pin will turn-off both LSA and LSB switches. When rises back to, LS A or LS B turn on again depending on the input pin state. NB: in no cases external pins (except for GND B and GND A ) are allowed to be connected with ground. TYPICAL APPLICATION CIRCUIT FOR DC TO KHz OPERATION V CC Reg 5V +5V +5V 3.3K 3.3K V CC K K DIAG A /EN A DIAG B /EN B K HS A HS B µc K IN A CW IN B K (*) K LS A M LS B GND A CCW GND B G D S b) N MOSFET (*) Open load detection in off mode 7/6

8 REVERSE BATTERY PROTECTION Three possible solutions can be thought of: a) a Schottky diode D connected to V CC pin b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on page 7) c) a P-channel MOSFET connected to the V CC pin The device sustains no more than -3A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNHSP3 will be pulled down to the V CC line (approximately -.5V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If I Rmax is the maximum target reverse current through µc I/Os, series resistor is: R V IOs V CC = I Rmax OPEN LOAD DETECTION IN OFF-MODE It is possible for the microcontroller to detect an open load condition by adding a simply resistor (for example kω) between one of the outputs of the bridge (for example ) and one microcontroller input. A possible sequence of inputs and enable signals is the following: IN A =, IN B =X, EN A =, EN B =. - normal condition: =H and =H - open load condition: =H and =L: in this case the pin is internally pulled down to GND. This condition is detected on pin by the microcontroller as an open load fault. SHORT CIRCUIT PROTECTION In case of a fault condition the DIAG X /EN X pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides; - short to battery condition on the output (saturation detection on the Low-Side Power MOSFET). Possible origins of fault conditions may be: is shorted to ground ---> overtemperature detection on high side A. is shorted to V CC ---> Low-Side Power MOSFET saturation detection. () When a fault condition is detected, the user can know which power element is in fault by monitoring the IN A, IN B, DIAG A /EN A and DIAG B /EN B pins. In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (OUT X ) again, the input signal must rise from low to high level. () An internal operational amplifier compares the Drain-Source MOSFET voltage with the internal reference (.7V Typ.). The relevant Lowside PowerMOS is switched off when its Drain-Source voltage exceeds the reference voltage. TRUTH TABLE IN FAULT CONDITIONS (detected on ) IN A IN B DIAG A /EN A DIAG B /EN B OPEN H OPEN L OPEN H OPEN L X X OPEN OPEN X OPEN H X OPEN OPEN Fault Information Protection Action 8/6

9 TEST MODE The pin allows to test the load connection between two half-bridges. In the test mode (V pwm =-V) the internal Power Mos gate drivers are disabled. The IN A or IN B inputs allow to turn-on the High Side A or B, respectively, in order to connect one side of the load at V CC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIAD X /EN X pin corresponding to the faulty output is pulled down. ELECTRICAL TRANSIENT REQUIREMENTS ISO T/R Test Level Test Level Test Level Test Level Test Levels 7637/ I II III IV Delays and Impedance Test Pulse -5V -5V -75V -V ms, Ω +5V +5V +75V +V.ms, Ω 3a -5V -5V -V -5V.µs, 5Ω 3b +5V +5V +75V +V.µs, 5Ω 4-4V -5V -6V -7V ms,.ω V +46.5V +66.5V +86.5V 4ms, Ω ISO T/R Test Levels Result Test Levels Result Test Levels Result Test Levels Result 7637/ I II III IV Test Pulse C C C C C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 9/6

10 HALF-BRIDGE CONFIGURATION The VNH3SP3 can be used as a high power half-bridge driver achieving an on resistance per leg of.5mω. Suggested configuration is the following: V CC IN A IN B DIAG A /EN A DIAG B /EN B IN A IN B DIAG A /EN A DIAG B /EN B M OUTA GND A GND B GND A GND B MULTI-MOTORS CONFIGURATION The VNH3SP3 can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAG X /EN X pins allow to put unused half-bridges in high impedance. Suggested configuration is the following: V CC IN A IN B DIAG A /EN A DIAG B /EN B IN A IN B DIAG A /EN A DIAG B /EN B M OUTA GND A GND B GND A GND B M M 3 /6

11 Figure : Definition of the delay times measurement (example of clockwise operation) V INA, t V INB t t I LOAD t DEL t DEL t Figure : Definition of the Low Side Switching times t V OUTA, B 9% 8% t f % % t r t /6

12 Figure 3: Definition of the High side Switching times V INA, t D(on) t D(off) t V OUTA 9% % t /6

13 Waveforms NORMAL OPERATION (DIAG A /EN A =, DIAG B /EN B =) DIAG A /EN A DIAG B /EN B IN A IN B (int. pin) GATE A (int. pin) GATE B NORMAL OPERATION (DIAG A /EN A =, DIAG B /EN B = and DIAG A /EN A =, DIAG B /EN B =) DIAG A /EN A DIAG B /EN B IN A IN B (int. pin) GATE A (int. pin) GATE B CURRENT LIMITATION/THERMAL SHUTDOWN or SHORTED TO GROUND IN A IN B I LIM I OUTA T TSD T j DIAG A /EN A DIAG B /EN B (int. pin) GATE A (int. pin) GATE B normal operation shorted to ground normal operation 3/6

14 Waveforms (Continued) shorted to V CC and undervoltage shutdown IN A IN B (int. pin) GATE A (int. pin) GATE B DIAG B /EN B DIAG A /EN A V CC normal operation shorted to V CC normal operation undervoltage shutdown Load disconnection test (IN A =, =-V) IN A IN B (test mode) (int. pin)gate A (int. pin) GATE B DIAG A /EN A DIAG B /EN B load connected load disconnected load connected back 4/6

15 On State Supply Current Off State Supply Current Is (ma) 8 Is (ua) Vcc=8V INA or INB=5V Vcc=8V High Level Input Current Input Clamp Voltage Iinh (µa) 8 Vicl (V) Vin=3.5V Iin=mA Input High Level Voltage 6 Input Low Level Voltage Vih (V) Vil (V) /6

16 Input Hysteresis Voltage Vihyst (V) High Level Enable Pin Current Ienh (µa) Vcc=3V 7 6 Ven=3.5V High Level Enable Voltage Venh (V) 4 Low Level Enable Voltage Venl (V) Vcc=9V.6.4 Vcc=9V Enable Output Low Level Voltage Enable Clamp Voltage Vdiag (V).6 Vencl (V) Ien=mA Ien=mA /6

17 High Level Voltage Vpwh (V) 5 Low Level Voltage Vpwl (V) Vcc=9V.6.4 Vcc=9V High Level Current Overvoltage Shutdown Ipwh (µa) 8 Vov (V) Vcc=9V Vpw=3.5V Undervoltage Shutdown 34 Current Limitation Vusd (V) Ilim (A) /6

18 On State High Side Resistance Vs. T case Ronhs (mohm) 8 On State High Side Resistance Vs. V CC Ronhs (mohm) Iload=A Vcc=9V; 3V; 8V 7 6 Iload=A Tc= 5ºC 3 3 Tc= 5ºC Tc= -4ºC Vcc (V) On State Low Side Resistance Vs. T case On State Low Side Resistance Vs. V CC Ronls (mohm) 4 Ronls (mohm) Iload=A Vcc=9V; 3V; 8V 35 3 Iload=A 5 5 Tc= 5ºC Tc= 5ºC Tc= -4ºC On State Leg Resistance Vcc (V) Delay Time during change of operation mode Ron (mohm) tdel (µs) /6

19 Turn-on Delay Time td(on) (µs) Output Voltage Rise Time tr (µs) Turn-off Delay Time td(off) (µs) Output Voltage Fall Time tf (µs) /6

20 MultiPowerSO-3 THERMAL DATA MultiPowerSO-3 PC Board Layout condition of R th and Z th measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 6cm ). CHIPSET CONFIGURATION HIGH SIDE CHIP HS AB LOW SIDE CHIP A LS A LOW SIDE CHIP B LS B Auto and mutual R thj-amb Vs PCB copper area in open box free air condition (according to page definitions) C/W RthA RthB = RthC RthAB = RthAC RthBC 5 5 cm of Cu Area (refer to PCB layout) /6

21 THERMAL CALCULATION IN CLOCKWISE AND ANTI-CLOCKWISE OPERATION IN STEADY- STATE MODE HS A HS B LS A LS B T jhsab T jlsa T jlsb ON OFF OFF ON P dhsa x R thhs + P dlsb x P dhsa x R thhsls + P dlsb x R thhsls + T amb R thlsls + T amb OFF ON ON OFF P dhsb x R thhs + P dlsa x R thhsls + T amb P dhsb x R thhsls + P dlsa x R thls + T amb P dhsa x R thhsls + P dlsb x R thls + T amb P dhsb x R thhsls + P dlsa x R thlsls + T amb Thermal resistances definition (values according to the PCB heatsink area) R thhs = R thhsa = R thhsb = High Side Chip Thermal Resistance Junction to Ambient (HS A or HS B in ON state) R thls = R thlsa = R thlsb = Low Side Chip Thermal Resistance Junction to Ambient R thhsls = R thhsalsb = R thhsblsa = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips R thlsls = R thlsalsb = Mutual Thermal Resistance Junction to Ambient between Low Side Chips THERMAL CALCULATION IN TRANSIENT MODE (*) T jhsab = Z thhs x P dhsab + Z thhsls x (P dlsa + P dlsb ) + T amb T jlsa = Z thhsls x P dhsab + Z thls x P dlsa + Z thlsls x P dlsb + T amb T jlsb = Z thhsls x P dhsab + Z thlsls x P dlsa + Z thls x P dlsb + T amb Single pulse thermal impedance definition (values according to the PCB heatsink area) Z thhs = High Side Chip Thermal Impedance Junction to Ambient Z thls = Z thlsa = Z thlsb = Low Side Chip Thermal Impedance Junction to Ambient Z thhsls = Z thhsablsa = Z thhsablsb = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips Z thlsls = Z thlsalsb = Mutual Thermal Impedance Junction to Ambient between Low Side Chips Pulse calculation formula Z THδ = R TH δ + Z THtp ( δ) where δ = t T p (*) Calculation is valid in any dynamic operating condition. P d values set by user. /6

22 MultiPowerSO-3 HSD Thermal Impedance Junction Ambient Single Pulse C/W Z thhs Z thhsls Footprint 4 cm 8 cm 6 cm Footprint 4 cm 8 cm 6 cm.... tim e (sec) MultiPowerSO-3 LSD Thermal Impedance Junction Ambient Single Pulse Z thls Z thlsls Footprint 4 cm 8 cm 6 cm Footprint 4 cm 8 cm 6 cm C/W.... tim e (sec) /6

23 Thermal fitting model of an H-Bridge in MultiPowerSO-3 Thermal Parameter (*) Area/island (cm ) Footprint R=R7 ( C/W).5 R=R8 ( C/W).3 R3 ( C/W).5 R4 ( C/W).3 R5 ( C/W).4 R6 ( C/W) R9=R=R5=R6 ( C/W).6 R=R7 ( C/W).8 R=R8 ( C/W).5 R3=R9 ( C/W) R4=R ( C/W) R=R=R3 ( C/W) 5 C=C7 (W.s/ C). C=C8 (W.s/ C).5 C3 (W.s/ C). C4=C3=C9 (W.s/ C).3 C5 (W.s/ C).6 C6 (W.s/ C) C9=C5 (W.s/ C). C=C=C6=C7 (W.s/ C).3 C=C8 (W.s/ C).75 C4=C (W.s/ C) (*) The blank space means that the value is the same as the previous one. 3/6

24 MultiPowerSO-3 MECHANICAL DATA DIM. mm. MIN. TYP MAX. A.35 A.85.5 A3. B.4.58 C.3.3 D E E e F F F L.8.5 N deg S deg 7deg 4/6

25 MultiPowerSO-3 SUGGESTED PAD LAY-OUT 5/6

26 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 4 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 6/6

27 This datasheet has been download from: Datasheets for electronics components.