Rajeev Kumar. i.mx Product Line Manager. August 2011

Transcription

1 Rajeev Kumar i.mx Product Line Manager August 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMAROS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 i.mx 6 overview Core subsystem (Single, Dual, Quad) Triple Play Graphics subsystem Video, Display, Memory IO overview, Boot modes, Packaging Power Management SW, Development Platforms, Documentation Freescale on Kaixin Tag yourself in photos and upload your own! Weibo? Please use hashtag #FTF2011# 2

3 Display centric devices are the fastest growing segment of the market Freescale Target Markets Industrial Medical Automotive Smartphones, Smartbooks & Tablets Connected Displays Over 150 million processors shipped ereaders Top 3 AP silicon vendor Power & Performance Leadership 1 st Quad A9 + 64b memory, 1 st Cortex CPU + integrated EPD Multi-core CPU, multi-core graphics, multi-stream video, console class 3D, rich interfaces i.mx53: 400mW SOC for 1080p, H.264 HP, XGA screen Smooth Scalability Quad, Dual and Single core CPU offerings Best in class flexibility/integration: Consumer, Auto, Industrial IO s + qualifications + BGA/POP offerings 3 GbE, PCIe, SATA, MIPI, USB, HDMI, LVDS, EPD, etc Full PMIC integration (lower complexity & BOM) LP-DDR2 / DDR3 (cost versus power options) Single SW investment, multiple devices in market Pin compatibility Trusted Technology Up to 15 year life cycle support Auto grade quality design practices Fully featured, market targeted reference designs Android, Microsoft, QNX, Linux, Ubuntu optimizations

4 Freescale Ref Soln SW/Pin Compatibility Support Competitors $ BOM Out of the Box Experience Longevity PMIC fast boot Docs Channel Partner Program Multiple Markets; Embedded Leadership Scalable Platforms Targeted SW Ease of Use Secure Solutions Trusted Partner 4

5 Dragonball 1 st FSL Apps Processor i.mx1 1st FSL ARM9 Apps Processor i.mx2 Series 90 nm LP HW Video Accel Analog Integration i.mx3 Series ARM11 GPU Integration i.mx5 Series 65 nm LP/GP ARM Cortex-A8 >1GHz i.mx 6 Series 40 nm LP ARM Cortex-A9 Multi-core family 50+ Products >150M Units Clear market leader for ereader apps processors (IDC) No. 2 in Auto Infotainment (Strategy Analytics) No. 3 in Mobile Apps Processors (Linley 5/2011) 5

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7 Performance/ Multimedia Capability Content Creation, Technology Driver Good, Better, Best Differentiation i.mx 6Quad NEW i.mx53 Media Tablet Netbook Luxury Infotainment Advanced HMI i.mx 6Dual NEW i.mx51, i.mx50 Color ereader Business Tablet Mainstream Infotainment Medical i.mx 6Solo NEW i.mx28, i.mx233, i.mx25, i.mx27, i.mx31, i.mx35 Monochrome ereader Single Function Tablet Connected Radio Smart Energy Meter 7

8 Industry s most scalable family of multimedia applications processors Easily build scalable product lines with the i.mx 6 series ultimate versatility with compatible single, dual and quad core devices Best-in-Class Performance enabled by quad core processing, low power consumption and bleeding-edge multimedia and graphics Optimized peripheral sets tailored to serve auto, industrial and consumer markets Fast development through simplified hardware design, flexible interfaces and easy-to-use development kits 8

9 Breaking the Boundaries of User Experience Freescale: The most powerful ARM yet? By Steve Bush January 5, 2011 With the i.mx 6 series, Freescale offers the broadest and highest performance family of products -Jim McGregor, chief technology strategist at In-Stat. Applications Processors Scale From One to Four Cores January 6, 2011 The i.mx 6Quad is ideal for netbooks and high end tablets, offering more total CPU performance than any other application processor, even Intel s Atom processors. - Linley Gwennap Freescale Boosts Share Of Tablet Processor Market By Esther Shein December 10, 2010 Power. We need more. More for streaming video, more for playing games, and more just so that we can say we have it. Freescale hears us, and it's delivering. By Darren Murph February 4, Freescale ups ante for tablets, phones with quad-core i.mx 6 January 3, 2011

10 i.mx 6Solo Single ARM Cortex A9, 1 GHz 512KB L2 cache, Neon, VFPv3, Trustzone Next generation video, 3D graphics (6Solo only) External memory support up to 32bit DDR3 and LPDDR2 Integrated EPD controller i.mx 6Dual Dual ARM Cortex A9, 1/1.2GHz 1 MB L2 cache, Neon, VFPv3, Trustzone 3D graphics with 4 shaders up to 200MT/s Dual stream 1080p/720p dec/enc External memory support up to 64- bit DDR3 and 2-channel 32-bit LPDDR2 Integrated SATA-II i.mx 6Quad Quad ARM Cortex A9. 1/1.2GHz 1 MB L2 cache, Neon, VFPv3, Trustzone 3D graphics with 4 shaders up to 200MT/s Dual stream 1080p/720p dec/enc External memory support up to 64- bit DDR3 and 2-channel 32-bit LPDDR2 Integrated SATA-II Common Features of the i.mx 6 Series Platform ARM Cortex A9 based solutions up to 1.2GHz Dual HD 1080p decode, Dual 720p encode, single stream up to 1080p60, 50Mb/s 3D video playback in High definition Low power 1080p playback at 350mW Integrated IO s that include HDMI v1.4 w/phy, LVDS display ports, MIPI CSI/DSI for camera/display, MIPI HSI, Gigabit Ethernet, multiple USB 2.0, PCI-Express, CAN controller, MLB bus Consumer, Industrial and Automotive temperature range qualifications POP, BGA packaging options using low layer count PCB design rules SW support: Google Android, Microsoft Windows Embedded CE, Ubuntu, QNX, Linux, Linaro, Adobe Flash, Skype 10

11 Development under way on new PFUZE PMIC family First product family using new Modular Development Strategy (MDS) Family of products supports entire i.mx6x family Quad core Dual core Solo Various integration levels target different applications PFUZE100: Embedded/ auto-infotainment PFUZE101: Single-cell applications PFUZE201: Solo low-cost single-cell applications PFUZE100 will be available in two versions: MCxxxxx Consumer and Industrial applications (-40C to +85C) MCxxxxxA Automotive Grade 3 applications (-40C to +85C) 11

12 Applications Applications processor Processor Drivers 2 optional interrupts MMA MMA9550: 32-bit CPU + 3-axis accelerometer Optimized Architecture for sensors 14-bit ADC SPI, I2C (2) 3x3x1mm LGA Package Benefits: Up to 2MBps (Slave) Save System Power Local control and power management of multiple sensors Up to 400KBps (Master) Save System Processing Preprocessing of multiple sensor inputs Fusion of multiple sensors into higher level data Mag Cap Touch Pressure Algorithm Abstraction Remove sensor specific algorithms from application software build Other Sensor Peripherals 12

13 SATA SDIO USB SP, HSI I I2S MIPI CSI l2c l2c GPS Bluetooth WiFi Flash Memory Dual LP- DDR2 or Dual DDR3 DRAM up to 2GB 3G Modem (if needed) SDIO UART UART USB ULPI HDMI i.mx 6 Applications Processor SSI ESAI LVDS Audio CODEC Dual Displays ZigBee RF4CE Speakers Dual MIC Home Wireless PFUZE100 Platform Power Management IC l2c 1.2Ghz Dual 1080p Video Triple Play Graphics 0.8mm BGA or 0.4mm POP Compass Gyro Accelerometer Sensors Watt Saver AC adapter MCU MCU Wireless charging/docking station Device Storage and Connectivity 13 Cap Touch Sensors 3D (Dual) Camera Multi-Format Radio RF RF

14 System Control i.mx 6Quad/6Dual Connectivity Specifications Secure JTAG MMC 4.4 / SD 3.0 x3 CPU: i.mx 6Quad 4x GHz, DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC Process: 40nm Core Voltage: 1.1V i.mx 6Dual 2x GHz, 6000 DMIPS Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 32KB D-cache per core P per core UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Watch Dog x2 Power Mgmt Power Supplies Temp Monitor Internal Memory ROM RAM Security RNG TrustZone Ciphers Security Ctrl Secure RTC efuses 1MB L2-cache + VFPv3 Multimedia Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI Updated from i.mx53 Keypad S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz 14

15 Pin Compatible Freescale Portfolio ARM Cortex A5/A9 High Tier i.mx6q ARM A9 Quad Core USB / MLB Mid Tier i.mx6d ARM A9 Dual Core USB / MLB Pin Compatible Software Compatible Common IP Entry Tier i.mx6s ARM A9 Single core USB / MLB Common ARMV7 architecture 15

16 ARM Coresight Multcore Debug and Trace Architecture FPU/NEON P I/F FPU/NEON P I/F FPU/NEON P I/F FPU/NEON P I/F HW Components: Cortex-A9 CPU Instruction Cache Data Cache Generalized Interrupt Control and Distribution Cortex-A9 CPU Instruction Cache Snoop Control Unit (SCU) Cache-2-Cache Transfers Primary AMBA 3 64bit Interface Data Cache Cortex-A9 CPU Instruction Cache Snoop Filtering Data Cache Advanced Bus Interface Unit Timers Cortex-A9 CPU Instruction Cache Optional 2 nd I/F with Address Filtering Data Cache Accelerator Coherence Port System: 2x/4x Cores in i.mx 6 Dual/Quad 32 KB L1 (I and D) 1MB L2 Cache 128 Interrupts Using 2x 64-bit AXI to L2C Per core 32 KB I and 32KB D L1 Cache Neon, VPU, Jazelle, Trustzone L2 Cache Controller (PL310) AXI 64-bit AXI 64-bit AXI 64-bit AXI 64-bit AXI Fabric 16

17 Core1 Core2 Core3 Core4 Game Image Editing Productivity Playback Video Editing Browsing Bioshock 35% 25% 27% 11% Call of Duty 4 37% 27% 26% 10% Crysis 39% 44% 14% 2% Maya3D 41% 21% 5% 13% Photoshop 59% 17% 6% 10% Adobe Reader 36% 19% 5% 1% Excel 40% 12% 2% 0% Powerpoint 42% 16% 4% 1% Streets & Trips 34% 20% 5% 2% itunes 9 45% 24% 6% 1% Quicktime 7 39% 28% 23% 6% Quicktime HD 26% 22% 22% 19% Handbrake.9 88% 2% 10% 0% Powerdrive v8 58% 19% 11% 8% Firefox % 19% 9% 5% Safari % 21% 12% 8% % Utilization of 1.6GHz Quad Processor* * Evolution of Thread-Level Parallelism in Desktop Applications, Blake, The Bad News: Even 5 years after launch, Dual and Quad Core Desktop Processors are not fully utilized by popular desktop software applications. Software has not kept up with hardware But: How consumers use Desktop/laptops is fundamentally different than mobile/auto. So does Multicore make sense for mobile?

18 The Great News: i.mx 6Quad enables a richer experience across the board. Four cores means more services, richer standard apps, faster response times, and headroom to expand and grow as the market evolves Richer Standard Apps Full suite of Enhanced Mobile Services Cortex A9 (1) Cortex A9 (2) Cortex A9 (3) Cortex A9 (4) 18

19 Playing rich 3D game and VOIP over HDMI with Rich Web Browser on main screen (requires 2GHz) i.mx 6Dual 2.4Ghz Dual A9 i.mx 6Quad 4.8Ghz Quad A9 Hypothetical Processor 2.4Ghz Single A9 Hypothetical single core processor at 2.4Ghz Single core must double frequency to do use case Rich Game VOIP 1 1 Same Performance 1 Power.64P (vs Single).82P (v dual).44p (v single) P 36% Lower Power 18 to 56% Lower Power Assumption Power impact Note Frequency P.25P F linear scaling 2 vs 4 Cores 2 Core 4Cores 4* 0.25P 1P Quad Cores Voltage 1.2Volt 1.0Volt.82@ P.82P V2 scaling factor Frequency P.25P F linear scaling 1 vs 4 Cores 1 Core 4Cores 4* 0.25P 1P Quad Cores Voltage 1.5Volt 1.0Volt.44@ 1P.44P V2 scaling factor Frequency P.5P F linear scaling 1 vs 2Cores 1 Core 2 Core 2*.5P 1P Dual Cores Voltage 1.5Volt 1.2Volt.64@ 1P.64P V2 scaling factor 19

20 15.7 mm Actual results from processor X Processor MMP2 Goal: determine the correct CPU package size and the type of heat spreader (graphite or heatsink) to maximize power envelope of the processor without overheating the entire platform Results: recommended 5 cent graphite headspreader instead of $1.50 heat sink mm 78.4 mm LCD Assumptions: System Size: x 78.4 x 15.7 Outside ambient temperature at 40 C Processor usage power 2W continuous Processor is the only power source in the system Board System PCB is a 6 layer 1.2 mm thickness CPU package size 2.19mm HFCBGA 1.7mm HFCBGA 1.7mm FCBGA 1.2mm FCBGA 1.2mm TFBGA Max pkg power without heatsink (goal 2Watts) Max pkg power with graphite heat spreader 5 cents (US) cost adder Max pkg power with heatsink $1.50 (US) cost adder 2.3W 2.3W 1.8W 1.8W 1.7W 4.6W 4.6W 3.6W 3.6W 3.4W 5.5W 5.5W 4.5W 4.5W 4.2W 20

21 Max Available DMIPs Better than A9 Dual 2Ghz requires 3.2 Watts thermal budget to equal 4 1.2Ghz Better than A15 Dual Cortex A15 s require ~1W more to reach same performance as Quad Cortex A9 s A9 A15 Using case study from previous example: Up to ~1.7W with no heat sink Up to ~3.4W with graphite heat spreader($0.05) Up to ~4.2W with heat sink ($1.50) CPU thermal budget, W Max Performance Comparison (Dual A15 and Quad A9) Assumes LVT cells used for A15 at 2Ghz vs 1.2Ghz Quad A9 Assumes Tjunction temp of 125Deg C Equivalent to sustained performance of Cores running flat out Dual 2Ghz outputs ~ 3.25Watts vs ~2.5W for Quad A9 at same max DMIPS Dual 1.2Ghz will never provide equivalent performance of Quad A9 21

22 Web Browsing over WIFI i.mx 6Quad Dual A15 Desktop class (10 Mb/s) 1. Incoming Web traffic 1 MB/s 1 MB/s Desktop class (10 Mb/s) 2. Display Frame buffer sent to LCD 93 MB/s 93 MB/s 3. OS Traffic, Audio, etc. 900 MB/s 900 MB/s Total bandwidth Consumed 994 MB/s 994 MB/s Raw available Bandwidth 8528 MB/s 8528 MB/s Available Bandwidth (70% utilization) 5970 MB/s 5970 MB/s % Available Bandwidth consumed 16% 16% Apps Processor: Current + Leakage (125 Deg Tjunction) 540mA(740mW) 900mA (2100mW) Main Memory 45 ma (164mW) 45 ma (164mW) WIFI 45mA (162mW) 45mA (162mW) PMIC 1.88 (6.8mW) 1.88 (6.8mW) Display 47 ma (171mW) 47 ma (171mW) Audio codec 1.4mA (5mW) 1.4mA (5mW) Total Battery Power: (System) 680mA ( 1248mW) 1040mA (2608mW) Battery life (6400mAh) 9.4 hrs 6 hrs Quad 600Mhz/core provides 3.4 hours more browsing time at >50% lower total current/power than Dual 800Mhz per core (note assumes high DMIPS/Mhz of A15) Desktop class browsing (2.4Ghz) 10 Mb/s, 5 rich sites open Lots of always on content Subnote class browsing (1.7 Ghz) 10 Mb/s, 5 rich sites open Lots of always on content Mobile tabbed web ( Mhz+) 5Mbit/s, 5+ rich websites open Frequent updates Rich web site ( Mhz) 300+ Kb/s, Animated UI s, Embedded media 22

23 System Control i.mx 6Quad/6Dual Connectivity Specifications Secure JTAG MMC 4.4 / SD 3.0 x3 CPU: i.mx 6Quad 4x GHz, DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC i.mx 6Dual 2x GHz, 6000 DMIPS Process: 40nm Core Voltage: 1.1V Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Watch Dog x2 Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 32KB D-cache per core 1MB L2-cache + VFPv3 P per core UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Keypad 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 Power Mgmt Power Supplies Temp Monitor Internal Memory ROM RAM Security Multimedia Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 RNG TrustZone Ciphers Security Ctrl Secure RTC efuses LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz Updated from i.mx53 23

24 Diverse markets and applications call for multiple GPUs: GC320 Accelerate existing windowing environments (Android, X11, etc.) and base user interfaces with a low-power high-performance composition engine GC355 Providing compelling vector capabilities for high-quality fonts and automotive clusters in a manner that assures quality of service in performance GC2000 Accelerate next-generation 3D and GPGPU applications with a feature-rich high-performing unified graphics processor 24

25 Rightware GPU Benchmarks Leading 40 nm Application Processors i.mx 6 GC2000 GL benchmark GPU Benchmarks 25

26 Vivante s anti-aliased rendering of the complex shaders in the BaseMark ES 2.0 Hover test is the best we have seen to date. I immediately asked for a video we can place on our web site - Teemu Uotila, Manager at RightWare Vivante applies multisampling anti-aliasing by rendering into larger textures for ultra-high image quality Blinn-Phong shader produces realistic colors calculated from the surrounding environment Smoke particle system produces realistic plums which must be present Hover

27 AHB Command System Vertex Handling & Interpolation Shader Processor Shader Processor Shader Core Processor Shader Core Processor Core Core Texture Texture System System & & Cache Cache Pixel Pixel Backend Backend MMU System Interface AXI AXI GC2000 AHB Command System Vector Graphics Pipeline Texture + Gradient Unit & Cache MMU System Interface AXI GC355 Tessellation Engine Pixel Backend AHB Command System 2D BLIT Composition Engine Engine Texture Texture && Cache Cache Pixel Pixel Backend Backend MMU System Interface AXI AXI GC320 27

28 Apple A5 Application Processor GPU Area (2X area GC2000) SGX543 MP2 GC2000 GC2000 Power Controlled Ultra-threaded Architecture Lower intrinsic power from smaller gate count Benchmarks 1024x768 ipad 1 SGX535 (A4-40nm) (fps) GC860 (55nm) (fps) GC860 vs ipad 1 ipad 2 SGX543MP2 (A5-40nm) (fps) GC2000 (40nm) (fps) GC2000 vs ipad 2 3DMark ES 2.0 Taiji Girl X X Hoverjet X X GLBench 2.0 Egypt X X PRO X X 28

29 Specifications CPU: i.mx 6Quad 4x GHz, DMIPS i.mx 6Dual 2x GHz, 6000 DMIPS Process: 40nm Core Voltage: 1.1V Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 System Control Secure JTAG PLL, Osc Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Watch Dog x2 Power Mgmt Power Supplies Temp Monitor Internal Memory Security 29 ROM RAM RNG TrustZone Ciphers Security Ctrl Secure RTC efuses i.mx 6Quad/6Dual CPU Platform Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 1MB L2-cache + VFPv3 Multimedia 32KB D-cache per core Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC P per core 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI Updated from i.mx53 Connectivity MMC 4.4 / SD 3.0 x3 MMC 4.4 / SDXC UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Keypad S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz

30 Feature Format Profile i.mx53 i.mx6 Series Low-Power Audio Decode SW SW MPEG-2 Main-High HW HW H.264 BP/MP/HP HW HW VC1 SP/MP/AP HW HW Embeds a flexible, powerful and low power hardware acceleration for HD video decoding in Blu-ray disk quality Low-Power Video Decode Low-Power Video Encode RV10 8/9/10 HW HW MPEG4/Xvid SP/ASP HW HW DivX 3/4/5/6 HW HW H.263 P0/P3 HW HW Sorenson H.263 N/A HW HW AVS Jizhun SW HW On2 VP6/8 N/A SW HW SVC HP SW HW/SW MVC N/A SW/HW HW MJPEG Baseline HW, 40MP/sec HW, 120MP/sec H.264 Baseline HW HW* + 720p60 H.263 P0/P3 HW HW MPEG4 Simple HW HW MJPEG Baseline HW, 80MP/sec HW, 160MP/sec Note: in all cases, the HW CODEC meets or exceeds the bit-rate requirements specified in the standards 1080p i/p30 (* - p only) 720p30 or 720p60 720p20 WVGA D1 (PAL/NTSC) Video Telephony (SiP, H323) H.264 BP HW HW Transcode (DLNA) (M)DMS/(M)DMP HW HW Video de-interlacing HW HW Further Video Processing (deblocking, resizing, CSC) HW HW 30

31 11 to 24 hours of HD playback 1080p30 fps or 720p60 fps h.264 High Profile Single Stream at 50Mbps 350mW decode power 7 to 15 hours of 3D video playback 1080p60 h.264 MVC Dual stream at 25Mbps each 700mW decode power i.mx 6Dual/ 6Quad 12 hours of 1080p video encode 1080p30fps H.264 Single stream at 20Mbps 300mW encode power 8 hours of 3D video encode 720p60 h.264 MVC Dual stream at 25Mbps each 700mW decode power 31

32 Optional Integrated I/F Bridges IPU Sync & Control MCU Video Sources Camera Interface Processing GPU Displays Display Interface Including Image Enhancements And Conversions Memory Interface Memory Functions: comprehensive support for the flow of data from an image sensor and/or to a display device. Connectivity to relevant devices Related image processing and manipulation Synchronization and control capabilities 32

33 Combining in the Display Processor (DP) Two planes One plane may have any size and location The other one must be full-screen (cover the full output area) Maximal rate: i.mx37/ MP/sec, i.mx MP/sec, i.mx6 Series 266 MP/sec External Memory Combining methods (in both cases) Color keying and/or alpha blending Alpha: global or per-pixel; interleaved with the pixels (upper plane) or as a separate input DI DC DI IPUv3 DP IC Plane 1 Plane 2 Plane 3 Plane 4 Note: This is the capability of each of the two IPUs, so the total capability of the processor is doubled. Combining in the Image Converter (IC) Two planes; both full-screen (cover the full output area) Maximal rate: i.mx37/51 20 MP/sec, i.mx53 30 MP/sec, i.mx6 Series 40 MP/sec 33

34 Example 1: 2x 4 planes Example 2: 1x 7 planes Example 3: 4x 2 planes i.mx6 Dual/Quad DI DP DC External Memory Plane 8 (top) i.mx6 Dual/Quad DI DP DC External Memory Plane 7 (top) i.mx6 Dual/Quad External Memory IPUv3-1 IC VDIC Plane 7 Plane 6 Plane 5 (bottom) IPUv3-1 CSI IC VDIC Plane 6 Plane 5 DI DC DI IPUv3-1 DP IC Plane 8 Plane 7 Plane 6 Plane 5 (bottom) i.mx6 Dual/Quad External Memory i.mx6 Dual/Quad External Memory i.mx6 Dual/Quad External Memory DI DC IPUv3-0 DP IC VDIC Plane 4 (top) Plane 3 Plane 2 Plane 1 (bottom) DI DC IPUv3-0 DP IC VDIC Plane 4 Plane 3 Plane 2 Plane 1 (bottom) DI DC DI IPUv3-0 DP IC Plane 4 Plane 3 Plane 2 Plane 1 (bottom) Note: Some planes may be a result of additional off-line combining of several planes. Such combining may be performed either with IPUs or GPUs. 34

35 Display Conversion and output Composition and Blending Content DI DC DP External Memory Frame Buffer VPU Video Content 2 Front Cam Video Content 3 Rear Cam IPUv3 Video Content 1 Decode GPU Graphics Content 1 NAV External Memory Graphics Content 2 DI DC DP Frame Buffer Graphics Content 3 IPUv3 35

36 Capabilities Maximal display resolution: 4096x4096 pixels Maximal pixel rate: 266 MP/sec Display refresh rate The maximal refresh rate is: 266M / (W * H * B) W*H is the display resolution B is a factor >1 reflecting blanking overhead, e.g. as specified by VESA, CEA-861-D, etc. The table provides the maximal refresh rates for some typical resolutions Usually, the refresh rate is required to be at least 60 Hz, to prevent blinking. The blanking overhead factor assumed for the calculation is 1.3. The actual factor depends on the display and is often closer to 1, allowing higher 60 Hz (e.g. HD1440). For example, for HD1080, the standard specifies B~1.2 This is the capability of each of the two IPUs, so the total capability of the processor is doubled. 800 x 480 (WVGA) ~331 Hz 1280 x 720 (HD720) ~138 Hz 1024 x 768 (XGA) ~161 Hz 1920 x 1080 (HD1080) ~61 Hz 2048 x 1536 (4XGA) ~40 Hz 36 Name Resolution Width x Height Total [MP] Maximal Refresh Rate [Hz] VGA 640 x PAL 720 x WVGA 800 x NTSC 720 x SVGA 800 x WSVGA 1024 x XGA 1024 x HD x WXGA 1366 x WXGA x SXGA 1280 x SXGA x WSXGA x UXGA 1600 x HD x WUXGA 1920 x VGA 1920 x XGA 2048 x HD x WXGA 2560 x K x 2K 4096 x

37 First Display Second Display SDTV 480i30/576i25 (27 MHz) WSVGA (1024x600) (44-49 MHz) HDTV 720p60/1080i30 (74.25 MHz) WXGA (1366x768) (72-85 MHz) WSXGA+ (1680x1050) ( MHz) HDTV 1080p60 (148.5 MHz) WXGA (1366x768 ~ 1.0 MP; MHz) Full Full Full Full Full Full SXGA (1280x1024 ~ 1.3 MP; MHz) Full Full Full Full Partial Partial SXGA+ (1400x1050 ~ 1.5 MP; MHz) Full Full Full Full Partial WSXGA+ (1680x1050 ~ 1.8 MP; MHz) Full Full Full Full Partial UXGA (1600x1200 ~ 1.9 MP; MHz) Full Full Full Partial WUXGA (1920x1200 ~ 2.3 MP; MHz) Full Partial Partial 9VGA (1920x1440 ~ 2.8 MP; MHz) Partial Partial 4XGA (2048x1536 ~ 3.2 MP; MHz) Partial This is the capability of each of the two IPUs, so the total capability of the processor is doubled. The maximal pixel clock rate supported by the display ports Each display: 220 MHz; Total: 240 MHz For a TV, the clock rate is fixed by the corresponding standards For other displays The assumed screen refresh rate is 60 Hz The blanking overhead impacting the pixel clock rate may vary between displays. The table refers for concreteness to the VESA CVT (Coordinated Video Timing) specification Full support : allowing full blanking (which is typically required for CRTs) Partial support : allowing only reduced blanking (which is still typically sufficient for digital displays, e.g. LCDs) The above table describes only the capabilities of the display ports to perform screen refresh. A full use case typically includes additional activities and to confirm its support with a given display configuration, additional aspects video processing capabilities, capacity of the memory system, etc. should be also analyzed carefully. 37

38 System Control i.mx 6Quad/6Dual Connectivity Specifications Secure JTAG MMC 4.4 / SD 3.0 x3 CPU: i.mx 6Quad 4x GHz, DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC Process: 40nm Core Voltage: 1.1V i.mx 6Dual 2x GHz, 6000 DMIPS Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 32KB D-cache per core P per core UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Watch Dog x2 Power Mgmt Power Supplies Temp Monitor Internal Memory ROM RAM Security RNG TrustZone Ciphers Security Ctrl Secure RTC efuses 1MB L2-cache + VFPv3 Multimedia Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI Updated from i.mx53 Keypad S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz 38

39 Parameter LPDDR2 support DDR2 support DDR3/LVDDR3 support Bus width Max memory size Address i.mx6 Dual/Quad Yes No Yes 1x32/64 DDR3; 2x32 (Dual channel) LPDDR2 ~4GB (DDR3) CA DDR bus (LPDDR2) # of CS 2 Max.frequency ODT Calibration 533MHz (1066Mb/s) Yes Yes Support of Dynamic Frequency Scaling Software transparent, ensuring data integrity Self Refresh and Power Down support Support Real-Time priority via QoS, e.g. for screen refresh Access Latency hiding Bank interleaving, Channel interleaving Consecutive read/write access optimizations Enabling access priority to open memory pages Deep queues for read and write requests MMDC: 64-bit, 2GB LV-DDR3 / DDR3 2Gb, 2Gb, 2Gb, 2Gb, x16 2Gb, x16 2Gb, x16 2Gb, x16 2Gb, x16 x16 x16 x16 DQ [63:48] DQ [47:32] DQ [31:16] DQ [15:0] MMDC: 2xCh 32-bit, 1GB LPDDR2 2Gb, x32 2Gb, x32 2Gb, x32 2Gb, x32 CS0# - ChA CS1# - ChA CA [9:0], ChA DQ [31:0] - ChA CS0# - ChB CS1# - ChB CA [9:0], ChB DQ [31:0] - ChB CS0# CS1# A [15:0], BA [2:0] DQ [31:0] 39

40 Minimal Headroom Single LPDDR2 Dual LPDDR2 Capability Display Configuration MB/s 1x LPDDR2 2x LPDDR2 200Mhz 400Mhz 533Mhz 400Mhz 533Mhz max % Smartphone with WVGA Display (854x480 resolution) Movie Decode (720p) WVGA LCD output 792 Video Record (720p) WVGA LCD output 918 Take Picture + Video Record (720p) WVGA LCD output 1166 Movie Playback (1080p) WVGA LCD + output to TV 1194 Video Record (1080p) WVGA LCD output 1467 Take Picture + Video Record (1080p) WVGA LCD output D Game (30MT/s) WVGA LCD + output to TV 1031 Tablet or Smartphone with XGA Display (1024x768 resolution) Movie Decode (720p) Video Record (720p) WXGA LCD output WXGA LCD output Take Picture + Video Record (720p) WXGA LCD output 1881 Movie Playback (1080p) WXGA LCD + output to TV 2098 Video Record (1080p) WXGA LCD output 2431 Take Picture + Video Record (1080p) WXGA LCD output D Game (30MT/s) WXGA LCD + output to TV 1391 Insufficient 40

41 Single LPDDR2 Dual LPDDR2 Smartphone with WVGA Display (854x480 resolution) Capability Display Configuration Movie Decode (720p) WVGA LCD output 792 Video Record (720p) WVGA LCD output 918 Take Picture + Video Record (720p) WVGA LCD output 1166 Movie Playback (1080p) WVGA LCD + output to TV 1194 Video Record (1080p) WVGA LCD output 1467 Take Picture + Video Record (1080p) WVGA LCD output D Game (30MT/s) WVGA LCD + output to TV x LPDDR2 2x LPDDR2 200Mhz 400Mhz 533Mhz 400Mhz 533Mhz max % Movie Decode (720p) WXGA LCD output 1011 ablet or SmartphoneVideo Record (720p) WXGA LCD output 1731 with XGA Display Take Picture + Video (1024x768 resolution) Record (720p) WXGA LCD output 1881 Movie Playback (1080p) WXGA LCD + output to TV 2098 Video Record (1080p) WXGA LCD output 2431 Take Picture + Video Record (1080p) WXGA LCD output D Game (30MT/s) WXGA LCD + output to TV

42 System Control i.mx 6Quad/6Dual Connectivity Specifications Secure JTAG MMC 4.4 / SD 3.0 x3 CPU: i.mx 6Quad 4x GHz, DMIPS PLL, Osc CPU Platform MMC 4.4 / SDXC Process: 40nm Core Voltage: 1.1V i.mx 6Dual 2x GHz, 6000 DMIPS Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 32KB D-cache per core P per core UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Watch Dog x2 Power Mgmt Power Supplies Temp Monitor Internal Memory ROM RAM Security RNG TrustZone Ciphers Security Ctrl Secure RTC efuses 1MB L2-cache + VFPv3 Multimedia Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI Updated from i.mx53 Keypad S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz 42

43 Feature i.mx53 i.mx6dual/quad High Assurance Boot Secure Storage Cryptographic Accelerators Authenticated Boot (HABv4) On-chip zeroizable 4x4kB Secure RAM Off-chip storage protected using unique HW master key (AES-256) (SCCv2) Symmetric: AES-128, DES, 3DES, ARC4 Hash & HMAC: MD5, SHA-1, SHA-224, SHA- 256 HW Random Number Generator (SAHARA) Authenticated Boot + Encrypted boot (HABv4.1) On-chip zeroizable 4x4kB Secure RAM Off-chip storage protected using unique HW master key (AES-256) (CAAM/SNVS) Symmetric: AES-128/256, DES, 3DES, ARC4 Hash & HMAC: MD5, SHA-1, SHA-224, SHA- 256 HW Random Number Generator follows NIST/BSI recommendations > 2015 (CAAM) Run-time Monitoring RTIC None Secure Real Time Clock SRTC SNVS Hardware Firewalls External memory (EMI Watermark) On-chip peripherals (CSU) External memory (TZASC) On-chip peripherals (CSU) Secure JTAG Full or Controlled Disable (3 modes) Full or Controlled Disable (3 modes) Physical Tamper Detection Tamper Input GPIO Tamper Response (SCCv2) Tamper Input GPIO Tamper Response (SNVS) Device Configuration Open, Closed Open, Closed, Field Return TrustZone Support Peripheral DMA access control (CSU) Memory DMA access control (EMI) Interrupt separation (TZIC) Secure storage separation (SCCv2) Cryptographic separation (SAHARA) Peripheral DMA access control (CSU) Memory DMA access control (ARM TZASC) Interrupt separation (ARM GIC) Secure storage separation (CAAM/SNVS) Cryptographic separation (CAAM) 43

44 System Control i.mx 6Quad/6Dual Connectivity Specifications CPU: i.mx 6Quad 4x GHz, DMIPS Secure JTAG PLL, Osc CPU Platform MMC 4.4 / SD 3.0 x3 MMC 4.4 / SDXC i.mx 6Dual 2x GHz, 6000 DMIPS Process: 40nm Core Voltage: 1.1V Package: 21x21 0.8mm Flip-chip BGA 12x12 PoP (LP-DDR2, NAND) Clock & Reset Smart DMA IOMUX Timer x3 PWM x4 Dual / Quad Cortex-A9 32KB I-cache per core NEON per core 32KB D-cache per core P per core UART x5, 5Mbps I 2 C x3, SPI x5 ESAI, I 2 S/SSI x3 3.3V GPIO Key Features and Advantages Multi-core architecture for high performance, 1MB L2 cache 64-bit LP-DDR2, DDR3 and raw / managed NAND S-ATA 3Gbps interface (SSD / HDD) Delivers rich graphics and UI in HW OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration Drives high resolution video in HW Multi-format HD1080 video decode and encode 1080p60 decode, 720p60 encode High quality video processing (resizing, de-interlacing, etc.) Flexible display support Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI Dual display up to WUXGA (1920x1200) and HD1080 MIPI-CSI2 and HSI Increased analog integration simplifies system design and reduces BOM DC-DC converters and linear regulators supply cores and all internal logic Temperature monitor for smart performance control Expansion port support via PCIe 2.0 Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588 Watch Dog x2 Power Mgmt Power Supplies Temp Monitor Internal Memory ROM RAM Security RNG TrustZone Ciphers Security Ctrl Secure RTC efuses 1MB L2-cache + VFPv3 Multimedia Graphics: OpenGL/ES 2.x, OpenCL/EP, OpenVG 1.x Video Codecs: 1080p30 Audio: ASRC 2x Imaging Processing Unit Resizing & Blending Inversion / Rotation Image Enhancement LCD & Camera Interface HDMI & PHY MIPI DSI MIPI CSI2 24-bit RGB, LVDS (x3-8) 20-bit CSI Updated from i.mx53 Keypad S-ATA & PHY 3Gbps USB2 OTG & PHY USB2 Host & PHY USB2 HSIC Host x2 MIPI HSI S/PDIF Tx/Rx PCIe 2.0 (1-lane) FlexCAN x2 MLB150 + DTCP 1Gb Ethernet + IEEE1588 NAND Ctrl (BCH40) LP-DDR2, DDR3 / LV-DDR3 x32/64, 533 MHz 44

45 i.mx6 Dual/Quad OTG Host1 Host2 NAND WEIM PHY PHY HS IC-USB SLC/MLC SRAM, NOR, OneNAND To OTG connector HUB (USB2524) to Cellular, WLAN/WiFI/BT or/and HUB NAND: 8-/16-bit bus Up to 40 bit ECC support was 16-bit in i.mx V supply range Boot able WEIM (SRAM, NOR, OneNAND): 16-/32-bit A/D multiplexed mode 16-bit A/D demuxed Address up to 27 bit Up to 6 EIM CS (were 4 in imx53) V IO supply range Bootable SATA Host Host2 10/100/1000 Ethernet IEEE1588 AVB HS IC-USB SATA PHY To external Memory Card To HDD/SSD PHY SATA SATA 2.5 specification compliant and AHCI 1.1 compliant Serial ATA Bus Adapter and internal 1 x PHY, up to 3Gbps operations Bootable PCIe Root/Endpoint PCIe PHY x1 PCIe System extension port 45

46 i.mx6 Dual/Quad SATA Host OTG Host1 Host2 Host2 10/100/1000 Ethernet IEEE1588 AVB NAND WEIM PHY PHY HS IC-USB HS IC-USB SATA PHY SLC/MLC SRAM, NOR, OneNAND To OTG connector HUB (USB2524) to Cellular, WLAN/WiFI/BT or/and HUB To external Memory Card To HDD/SSD PHY USB: OTG with internal HS/FS/LS PHY, Host1- with HS/FS/LS PHY, Host2 and Host 3 - HS IC-USB (480 Mb/s) Ethernet Controller (FEC) 10/100/1000: Support SNI, MII, RMII and RGMII interfaces to an external PHY. 1.65V 3.6V voltage range and automated selection IEEE1588 v2 and Supports Ethernet AVB PCIe lane, 5 Gbps with integrated x1 PHY PCIe Root/Endpoint PCIe PHY x1 PCIe System extension port 46

47 SoC i.mx51 MMC Ver/MHz/Vcc/Boot v4.2 (v4.3 partially) 26/52 MHz 1.8V, 3.3V Bootable i.mx53 v4.4 26/52 MHz, DDR 1.8V, 3.3V Bootable i.mx6 Dual/Quad v4.4 26/52 MHz, DDR 1.8V, 3.3V Bootable SD Ver/MHz/Vcc/Boot SD Phy Layer spec 2.0 SDHC spec /25/50 MHz 1.8V, 3.3V Bootable SD spec /25/50 MHz 1.8V, 3.3V Bootable SD spec /25/50 MHz 1.8V, 3.3V Bootable SDXC (1) Ver/MHz/Vcc/Boot SDXC 12/25/50 MHz 1.8V, 3.3V Non-bootable SDXC 12/25/50 MHz, DDR 1.8V, 3.3V Non-bootable SDXC 12/25/50/100 MHz, DDR 1.8V, 3.3V Bootable 47

48 ecspi/cspi one CSPI and two ecspi ports, same as in i.mx53 Keypad almost same as in i.mx53. 8x8 matrix supported. (6 x 6 maim configuration, but all pads are shared with other interfaces). External keypad controller considered for Netbook applications One-wire same as in i.mx53 One wire EEPROM and battery connection. Dallas DS2205 compatible. UART: High speed (up to 4MHz) covers TIA/EIA-232-F Standard 3 ports, one of them can operate as 8 pins full UART, DCE and DTE modes. Other are four-wire IrDA 1.0 SIR protocol support (115.2kbps or lower) 32 bytes FIFOs for transmitter and receiver, autobaud. 9 bit mode supported RS-485 mode supported GPT - same as in i.mx53 Two general purpose timers, each of them is a 32-bit free-running or set and forget mode timer. o External/Internal clock selectable o External/Internal event interval capturing o Programmable output logic, external output signal, ARM interrupt. PWM - same as in i.mx53 Two pulse-width modulators (PWM): 16-bit resolution and a 4x16 data FIFO SDMA - same as in i.mx53. Two external SDMA events Interrupts - same as in i.mx53. I2C Three I2C ports compatible with I2C specifications v2.1 (all up to 400Kb/s) GPIO: All multifunctional digital pads have the GPIO functionality Total number of GPIOs 224 The GPIO supports up to 32 interrupts: programmable active interrupt edges/level of external signal All of multifunctional (muxed) IOPADs are GPIO capable and could be programmed independently Most of GPIO capable pads are of UHVIO type V operational range with automated voltage range selection Default state for most of GPIO capable pads: GPIO Input Weak PU or PD That was done to avoid on-board contentions in default state after reset. 48

49 Flash Devices NOR flash (using WEIM) OneNand (using WEIM) NAND flash (using NFC) Serial ATA Boot modes are set via efuses For development purposes, there is an option to set boot modes via external pins Expansion Devices SD/eSD/SDXC/MMC/eMMC I2C SPI Serial Downloader USB (using USB OTG) Plug-in mode For custom / user-defined boot 49

50 Toshiba emmc 1 MByte [ms] NAND MLC, 8-bit 1 MByte [ms] Fast DDR 8-bit (1)(2) 66 Normal DDR 8-bit (1)(2) 90 Normal DDR 4-bit (1)(2) 90 Normal SDR 8-bit (1)(2) 90 Normal SDR 4-bit (1)(2) MHz, SDR (1)(2) MHz, DDR, theoretical (1)(2) 34 NOR, 16-bit 1 MByte [ms] ASYNC/SYNC InPlace (1)(3) 4 SYNC DDR (1)(2) ms with HAB Notes: 1. The boot time cannot be directly scaled to other code size as it includes not scalable initialization part. 2. HAB: Add 30ms for 1MByte (11.9ms + 1MByte * 16.7us/KByte) 3. HAB: Add 46ms for 1Mbyte (18.9ms + 1MByte * 27.3us/KByte) 50

51 OEM decides which parts of image will be encrypted. Some parts of image must be in plain text, e.g. IVT Image Vector Table (flash header) DCD - Device Configuration Data CSF Command Sequence File (authentication scripts) Two keys are used for encryption: OEM Key is used for program image encryption. This enables using same program image for all devices. CAAM Key (per device) is used for OEM Key encryption. The encrypted OEM Key is attached to image. Post-production updates: If no change in OEM Key just a regular update of image, without update of stored encrypted OEM Key. If OEM Key changes - update must be done using secure channel with OEM server, or in OEM Service Lab 51

52 Pin Compatible Part Package Ball Pitch Application Comments i.mx6 Quad 21x21 FC BGA 0.8mm Automotive Consumer 25x25 ball matrix, fully populated i.mx6 Dual 21x21 FC BGA 0.8mm Automotive Consumer i.mx6 Dual 12x12 PoP FC BGA 0.4mm Consumer 25x25 ball matrix, fully populated LPDDR2 2xCh/1xCh 32-bit. 29x29 ball matrix, partially populated 52

53 Description Top Bottom Max Total heights with Top memories Requirements 12 by 12 by 0.80mm PoP Green BOM, Ultra Low Alpha BOM and assembled at ASE s 12x12mm JEDEC array, Dual channel LPDDR2 (0.5mm pitch) 216 balls 12x12 mm by 1mm thick, 569 ball (0.4mm pitch) w/vss on 4 each corner 1 ball depopulated for orientation Tentative calculations (based on Micron POD s): - 2 die in PoP top 1.45 max (.350 top mold cap) Coplanarity <= 100um Warpage <= 70um 53

54 Description Package Characteristics Requirements 21 by 21 FC TFBGA, 2.0mm zheight 0.8mm ball pitch Green BOM, 624 ball 1 center ball depopulated for orientation.480 Mold Cap.66 Substrate Thickness 1.6 package thickness (minus balls).38 NOM ball height Coplanarity <= 100um Warpage <= 70um Notes: 1. Note that the array is depopulated and has core PWR/GND balls located to minimize board routing complexity and cost, 2. Substrate thickness of 300um is worst case, but we want to evaluate warpage performance of all options before committing to thinner materials, 12 by 12 PoP at

55 Just two external power rails Optional SRTC coin-cell rail Optional USB PHY rail Internal DVS and Power-Up Sequence and Reset. No need in smart PMIC. All external supply rails could be shared with system components Two stage power conversion: external DCDC pre-regulation, integrated LDOs (incl. DVS) Total system level power delivery efficiency (including linear regulators) is similar to typical DCDC based PMU 90% or better in high power mode with internally bypassed FET Better than 65% in low power modes Lowest BoM no multiple inductors, few external capacitors, System level: low cost PMIC or few discrete DCDC Maximal flexibility in power management system design 55

56 Encapsulating power management system inside i.mx no external dependencies: Power up sequence and defaults is closed inside the chip System level power management simple and cheap off-shelf components could be used for system design Simple and fast interface with external PMIC / discrete on/off only HW dependent components of power management driver could be placed in ROM. Only standardized API could be exposed outside (to OS) System complexity reduction System BoM reduction - no multiple inductors, just few external (or onpackage) capacitors Expecting 3% power saving in high load applications, due to better IR Drop compensation and optimized power distribution Power up / Power Down Sequencing: No special requirements! 56

57 Features i.mx 53 i.mx 6Dual/6Quad Software Impact (OS, BSP, Tools and Middleware) Cores Cortex A8. ARMv7, Trustzone, 32KB I/D L1 cache. 256KB L2 cache. Single Core Dual/Quad core Cortex A9. ARMv7. 32KB I/D L1 cache 1MB L2 Cache Kernel Enhancements, Low Level Initialization code Performance Tuning for dual /Quad core. Updates to drivers for multicore operation. All is encapsulated within Freescale BSP. Multithreaded applications will benefit the most from multicore design. L2 Cache 256K L2 Cache 1MB L2 Cache Minor changes to L2-$ flush routines. General Purpose SIMD Neon, VFP Neon, VFP No changes Internal SRAM 256KB SRAM 256KB SRAM Minor addressing changes for memory map. Security MX5x Baseline Same + NIST-approved RNG, TZ ASC 380 Minor updates. Uses same block SDRAM Memory Interface LPDDR2, DDR2, single channel Dual channel LPDDR2 and 64bit single channel DDR3/LV-DDR3 Most updates are transparent to software or encapsulated in freescale BSP. LPDDR2 controller for example, automatically balances memory storage between 2 channels with zero software intervention or required knowledge. NAND Controller Baseline Same NAND controller but adds 40-bit ECC and additional CS Minor changes to driver to account for higher ECC bit correction WEIM controller Baseline Same controller with additional chipselect Minor changes to account for additional chip select System Memory Map Baseline Memory map updated for more SDRAM space and new peripherals OEMAddressTable in OAL or low level kernel. Encapsulated in Freescale BSP INTC Baseline New INTC for 2 to 4 processors Interrupt Handler changes. Will work seamlessly with single core. Encapsulated in Freescale BSP AXI Fabric AXI fabric Same AXI but use dual 64-bit AXI ports from core complex and run at higher speed Transparent to OS 2D Graphics/3D Graphics 3D: AMD Z MTri/s, 200 Mpxl/s OpenGL ES 2.0 2D: AMD Z160: 200 Mpxl/s, OpenVG 1.1 3D: Vivante GC MTri/s, 1000 Mpxl/s OpenGL ES 2.x, OpenCL EP 1.1 2D: Vivante GC320: 600Mpxl/s, BLIT VG: Vivante GC355: 300Mpxl/s, OpenVG 1.1 Freescale will provide drivers for OpenGL, OpenVG. If software on i.mx53 is using OpenGL ES 2.0, OpenVG, then no changes on customer s part LCD Single IPU with support for LVDS, parallel display Dual IPU (same version) with support for dual LVDS, parallel, MIPI DSI and HMDI v Same mechanism of accessing IPU. Changes to display driver to handle communication to new LCD interfaces like HDM I 1.4. Provided in Freescale BSP. Customer can use dual IPU s for more enhanced layering of overlays vs i.mx53. Current software will be the same.

58 Features i.mx 53 i.mx 6Dual/6Quad Software Impact (OS, BSP, Tools and Middleware) VPU Baseline VPU with support for 1080p Updated VPU from same IP provider with support for 1080p high profile, 3D video decode, VP8 codec If using industry standard APIs then no real changes at app level to communicate with the VPU. If new codec implemented, need to Integrate with DirectShow or GStreamer Camera Interface and Controller Types: 2x 20-bit parallel Two simultaneous inputs Same Controller + MIPI-CSI-2 (4lanes) with three simultaneous inputs. No changes except selection option of using MIPI CSI sensors. Driver for MIPI CSI encapsulated in Freescale BSP UART, I2C, I2S, Watchdog, PWM, SPDIF, Keypad, Timers, SmartDMA and other APB peripherals UART, APB peripheral Same, units, no changes Freescale porting drivers with minimal changes USB USB 2.0 Host, USB 12 pin ulpi, USB OTG 2.0 Add USB HSIC Adding USB HSIC physical layer driver to BSP (encapsulated in Freescale BSP). HSIC seen as just another USB Port by upper layers. SD/MMC/SDIO Four SD/SDIO/MM Card Interfaces supporting mmc 4.1, SD 2.0 Add support for SDXC, MMC 4.4 New Driver for SD 3.0/SDXC. Encapsulated in Freescale BSP GPIO and Peripheral Devices Registers GPIO and ALT Functions Updated pin mux, alt functions Minimal changes to underlying configuration code to ensure proper pin mux chosen. Audio Baseline Additional # of I2S ports + ESSAI peripheral Updated drivers to take advantage of ESAI port. No changes by customer since encapsulated in Freescale BSP. Performance Monitoring Unit Standard Cortex A8 PMU, ASSP Registers, Events, Interrupt based Updated counters for Cortex A9 and multicore Encapsulated in Freescale BSP Trust Boot Trusted Boot with Trustzone Same Minor changes due to new peripherals on tustzone list BootROM Bootrom support for USB, NAND, NOR, SD/MMC. Same + additional bootsource requirements. Freescale will change this but it is just boot routines used by customer. AP CP Interface USB, UART, SPI, SD IO. Same + MIPI HSI, USB HSIC SATA, P-Sata P-SATA, SATA II 1.5Gbps P-SATA dropped. SATA II at 3Gbps Ethernet 10/100 Ethernet, IEEE 1588 Gigabit Ethernet, IEEE 1588 Additional driver for HSI and HSIC but these are provided by Freescale. If not using P-SATA then no change. SATA-II is same IP but runs at 2X bandwidth than i.mx 53 If not using ethernet, no changes. If using ethernet, IP is same IP source but enhanced for Gigabit. Encapsulated in Freescale driver. 58

59 SABRE Platform for rapid tablet development on i.mx 6Dual/6Quad D enabled display for glassless 3D viewing 1080p 3D video decode lets you experience hours of HD video playback in full 3D. 720p 3D video encode allows you to record your life in 3D. Full duplex video in HD (720p) provides a great video conferencing experience. Conserve battery life with hardwareaccelerated Adobe Flash Player 10.x which leverages dedicated graphics and video engines to deliver an outstanding visual experience. Tri-core graphics solution gives you 200MT/s 3D games, ultrafast mapping, crystal clear UI s to reduce power consumption and improve graphics performance, giving you quicker response time and more realistic gaming. Smartly integrated i.mx 6Dual/6Quad offers more on chip including PMIC, LVDS and USB PHYs, passing on significant BOM cost savings. Smart Application Blueprint for Rapid Engineering 59

60 Feature SABRE-I (i.mx53) SABRE-II (i.mx 6Series) Enclosure Baseline Same as SABRE-I LCD Enhanced viewing angle LCD Battery 84W/H Same range Ports 2x USB, 1x HDMI, 1x USB OTG, Debug port, power adaptor, volume, audio jacks, docking connector, Full size SD Same except removal of docking connector and addition of 120-pin expansion connector Keys Standard Android capacitive keys Same WIFI Atheros Same ZigBee Freescale Same Sensors Freescale Same + Eve sensor for compass/accel Memory Micron (1GB) Same + 2GB SATA connector SATA I with Sandisk 32GB card Same + SATA-II 3G Infineon 3G modem Same + Voice capable GPS Atheros Same Camera 5MP Omnivision 8MP Omnivision 60

61 i.mx 6Quad 1.2Ghz Cortex A9 Other Freescale silicon Freescale PFUZE PMIC MMA8451Q 3-Axis Accelerometer MAG3112 Compass MC1323X Zigbee Memory 2GBs DDR3 (4GB support in 2012) 32GB Sandisk emmc OS Support Android, Ubuntu, Linux, Windows Embedded User Interface x768 3D enabled display with capacitive multi-touch Stereoscopic 5MP cameras for 3D imaging/encode 8MP rear facing camera for picture taking Capacitive Buttons: Home, Menu, Back, Search Other Buttons: Power, Reset, Volume up/down Connectivity Atheros GM22 GPS Receiver Atheros AR6133 Wi-Fi/BT Module Infineon Amazon-1 3G Module I/O s: HDMI connector 1x Full size SD Card Slot 2x High-Speed USB Host, 1 x Micro-USB 1x SATA port, 1x LVDS display footprint Debug PCB with Ethernet 10/100/1000, JTAG, UART Stereo Speaker, Headphone/Microphone 61

62 i.mx SABRE for Automotive Infotainment Modular Reference Design Concept CPU Card Capable of stand-alone operation Processor, memory, power, USB, Ethernet, SD-card slot, Display Attaches to Application Module for more comprehensive system evaluation and application benchmarking Industry standard MXM 3.0 connector Wireless Modules GPS Module Bluetooth/WiFi Module 3G Modem Module Radio Tuners IAP Main Board Expanded connectivity options (CAN, MOST, USB, dual displays, SDIO Connectors for Processor Module and Wireless Modules 62

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