Computer Architecture

Transcription

1 Universitatea din Craiova Faculty of Automation, Computers & Electronics Department of Computers & Information Technology Computer Architecture Fundamental Concepts CPU organization and functioning CPU-MM speed transfer balancing techniques I/O devices Cătălina Mancaș Dan Mancaș

2 Previous topics General structure of a computer; Von Neumann Architecture (5-unit Structure); Functioning; Instruction Cycle. 2

3 The fundamental structure Data Flux de flow date Alternative Data Flow Flux de date alternativ CPU = ALU + CU Instructions Flux de instructiuni Flow Control Comenzi sau Line linii de control Status Informatii Line de stare sau linii de stare Unitatea Control de Control Unit (CU) (UC) Date de Input Data intrare si & programe Programs Unitatea Input de Intrare Unit (IU) (UI) Unitatea Arithmetic Logico- Logic Aritmeticã Unit (ALU) Date Unitatea Output de Iesire Unit (OU) (UO) Instructiuni Instructions Date de iesire Output Data sau rezultate & Results DMA Unitatea Memory de Memorie Unit (MU) (UM) DMA 3

4 Today... The general structure of the CPU; CPU-MM transfer speed balancing techniques; Advanced organization of CPU communication: peripheral devices; I/O units; I/O processors. 4

5 General structure of the CPU 5

6 The fundamental structure Data Flux de flow date Alternative Data Flow Flux de date alternativ CPU = ALU + CU Instructions Flux de instructiuni Flow Control Comenzi sau Line linii de control Status Informatii Line de stare sau linii de stare Unitatea Control de Control Unit (CU) (UC) Date de Input Data intrare si & programe Programs Unitatea Input de Intrare Unit (IU) (UI) Unitatea Arithmetic Logico- Logic Aritmeticã Unit (ALU) Date Unitatea Output de Iesire Unit (OU) (UO) Instructiuni Instructions Date de iesire Output Data sau rezultate & Results DMA Unitatea Memory de Memorie Unit (MU) (UM) DMA 6

7 CPU CPU = ALU + UC Central Processing Unit; Processor; Role: to execute sequences of instructions stored in MM; => interpreter of a set of instructions at machine language level. Program execution is carried out as follows: 1. CPU transfers instructions (and operands), from the MM into the registers inside the CPU (a.k.a local memory); 2. CPU executes the instructions in their stored sequence (one after another); 3. When necessary, the CPU transfers results from the CPU registers into the MM. 7

8 CPU MU Communication Data CPU Local Memory Main Memory CPU Cache Memory Main Memory 8

9 CPU Functioning Flowchart 9

10 CPU Registers Instruction Register (IR): UC; stores the instruction transferred from MM. Function Register (RF): UC; stores the OPCODE for further decoding. Address Register (RA): UC; stores the addresses of the operands. Accumulator Register (ACC): ALU; stores one operand; stores the result of the operation. 10

11 CPU Registers Operand Register (Op. Reg.): ALU; temporary stores the operand(s) buffer register. Status Register Flags Register (St. Reg.): stores various characteristics of the result flags (sign, carry, parity, zero etc.). Program Counter (PC): UC; instruction pointer, program counter; stores the address of the next instruction to be executed. 11

12 CPU Must communicate with all the units (MU, CU, I/OU). Input: data, instructions, status signals, interrupts; Output: addresses, data, control signals; => System bus. Component: system bus interface: bus controller; contains drivers, buffers and switchs. 12

13 CPU Communication 1) External: Bus Control Block: system bus interface; contains buffers and communication drivers. 2) Internal: Between CPU units: internal buses. address bus; data bus; control bus: control lines + status lines. 13

14 General Structure of the CPU Magistrala Interna Data de Bus Date Magistrala Address Interna Bus de Adrese Bus Control Unitate Buffer/Driver Unit Magistrala System Bus Sistem ALU ALU CU UC Linii Control de Control Lines General Registre generale Registers R 1 Instruction Address Adresa Instructiune DEC k/2 k R 2 Operand Adresa Operand Address Operand Address PC incr. Bloc Control Secventiator Sequencer de Control er Processing Bloc de Procesare Block R 2 k EA Calcul Computation AE Decodificator OPCODE OPCODE Decoder Decoded Operatie decodificata Operation Status Reg. Register Stare ACC AR RA FR RF Operand Reg. Register Op. Generator Clock de tact Dispozitiv de procesare Processing Device Address Bloc de Block Adresa IR RI Instruction Bloc de Block Instructiune Linii interne de Control Linii interne de Stare 14

15 ALU Contains: a set of general registers (local memory): storing operands and partial results; a processing block. Processing Block: a processing unit: performing arithmetic and logic operations; Accumulator Register (ACC); Operand Register: buffer register storing the second operand; Status Register: consisting in a set of condition bits (flags) representing different features associated to the generated result (sign, carry, parity, zero etc). 15

16 CPU: ALU 16

17 UC 3 blocks: 1) Instruction Unit ; 2) Address Unit; 3) Control Sequencer Block. 17

18 CPU: UC 18

19 UC Instruction Block: PC: Program Counter (PC); Instruction Register (IR); Function (FR); OPCODE Decoder. pointer to the next instruction to execute; a register with incrementing facility and parallel load facility. Incrementation command: control sequencer (generator); PC Content: used during the FETCH phase to read the memory; The fetched instruction is stored in the Instruction Register (IR); The OPCODE field is transferred in the Function Register (FR) the content of which is decoded (interpreted) by the OPCODE Decoder, allowing the identification of the operation. 19

20 UC Address Block: Address Register (RA): storing the logic address contained by the address field of the instruction; Effective Address Computation Device: applies specific mechanisms for determination of the effective address (EA) of the operands from the logic address (LA) given in the address field of the instruction. Control Sequencer (Control Generator Device): generates all the commands required by the execution of the current instruction; the decision is taken based on the content of the Status Register (Flags). 20

21 UC The component blocks of the Control Unit must perform: Extracting of the current instruction from memory; Transferring the instruction in the Instruction Register (IR); Storing fields of the instruction in the Function Register (FR) and in the Address Register (AR); Decoding the OPCODE and generation of the corresponding control signals on control lines; Determining the address of the next instruction to execute; Identifying the effective addresses (EA) of the operands; Transferring the designated operands in ALU; Performing the operation (function) provided by the OPCODE; Storing the result. 21

22 Memory Memory Unit (MU): hierarchical structure; Secondary Memory (external); programs and data that are being processed by the CPU; offline; great capacity; medium and high access time. Main Memory (operative); programs and data that are being processed by the CPU; online; Local Memory; a set of registers inside the CPU; fastest in the hierarchy. 22

23 Memory Nivel III MS Capacity increases MP Nivel II Accesstime increases ML Nivel I CPU 23

24 Memory There exists a great difference in capacity and speed of operation between different levels of memory hierarchy; Computers: automatically regulate the flow of information between levels of memory, by software or hardware means. Regulation: less frequently accessed information kept in slower and more capacious memory levels; more frequently accessed information being kept into the faster and less capacious memory levels. MM <-> CPU; Conflict: MM speed << CPU speed; Need: CPU must get information from MM at a speed comparable to its own operation. 24

25 CPU-MM Transfer Balancing Techniques 25

26 Techniques In order to increase the productivity of the computers must be the performance of the transfer CPU-MM must be balanced; Balancing techniques are grouped into three categories: 1. Widening the data bus; 2. Increasing the number of levels in memory hierarchy; 3. Prefetching the next instruction. 26

27 Widening the memory bus Programs and data to be processed are stored in MM; Processing is carried out in CPU. The results are sent back to the MM. CPU-MM communication: memory bus; Von Neumann Model: the speed of transferring data from/into MM represents a bottleneck; CPU extracts instructions and corresponding data from the MM one at a time; => architectural limitations! 27

28 Widening the memory bus Architectural limitation: speed; CPU <-1 instruction MM Memory Bus 28

29 Widening the memory bus Solution: widening the memory bus so as to extract several instructions and data items from the MM at a time. CPU <- more instructions MM Memory Bus => would solve the architectural problem! 29

30 Widening the memory bus Critical problem: the constraint of procedural access (one instruction at a time); Solution: make MM deliver a set of instructions and data; Another problem: prioritization; => to decide which instructions and data would be allowed, when several instructions and data are extracted from MM, provided that the CPU operates in a procedural way. Solution: ensure that the set of extracted instructions and transferred on the widened memory bus represents a sequence of instructions of the program processed by the CPU; Division of MM on several parallel blocks (memory modules). 30

31 Widening the memory bus 31

32 Widening the memory bus Simultaneous access to several modules, each offering an instruction or data item; Now: a set of n instructions or data items available for the CPU; But, the CPU will process one instruction at a time (von Neumann s procedurality principle); Division of MM on several parallel blocks (memory modules). 32

33 Widening the memory bus Original organization: One single memory block containing n instruction or data items; Extracting by reading n consecutive memory locations. 33

34 Widening the memory bus New structure: m memory blocks; n elements (data or instructions); memory locations having the same address; by means of a single access a n*m bits word is being extracted; the entire n*m bits word is stored in IR; CU extracts the instructions from RI, one by one. 34

35 Widening the memory bus The efficiency depends on the probability that the entire set of instructions in a widened word to be used by the CPU; Frequently: branches in the program evolution a change of the normal sequence of instructions. => new access memory blocks will be initiated to fulfil requirements of the branch, before all instructions/data from the previous word had been executed by the CPU. Solution: a model of prediction for sequences of instructions is to be considered (beyond the scope of the course). 35

36 Increasing the number of levels in the memory hierarchy Idea: to improve the flow from the MM to CPU; Solution: inserting a smaller in size, but very fast memory layer between MM and CPU; This is referred to as Super Operative Memory (Cache Memory). 36

37 Increasing the number of levels in the memory hierarchy 37

38 Increasing the number of levels in the memory hierarchy SOM (Super Operative Memory) Cache Memory; Roles: -> closest layer of memory to the CPU; -> very low access time (units or tens of nanoseconds); -> very fast memory; => operation speed comparable to the CPU s. delivering the current instructions and the corresponding data to CPU at speeds that are comparable to CPU speed; exchanging blocks of information with OM; Based on: locality property of a program. 38

39 Increasing the number of levels in the memory hierarchy SOM (Super Operative Memory); Initially: empty; CPU calls for the starting instruction of the program; MSO extracts the starting instruction from the Operative Memory, together with an entire block of instructions/data that are clustered around the initial instruction; When a failure (cache miss) of finding an instruction/data happens, a new block of instructions/data is brought from the OM. 39

40 Increasing the number of levels in the memory hierarchy Strategy: make transfers between SOM and OM as infrequent as possible; Based on models of prediction of sequences of instructions and data; The transfers between SOM and OM: hardware mechanism (transparent for the user). 40

41 PREFETCHING Instruction cycle: 1) FETCH; 2) EXECUTE. Executing a program: executing a series of instructions has the => a sequence FETCH-EXECUTE; 41

42 PREFETCHING FETCH: read the current instruction from the MM; decode it. EXECUTE: fetch the operand (data); execute the function; yielding the result. PREFETCH: overlap the EXECUTE phase of the current instruction with the FETCH phase of the next instruction; execute the current instruction (CPU) CU extracts from the memory the next instruction; temporary parallelism. Suprapunerea fazei EXECUTE de la intrucţiunea curentă cu faza FETCH de la instrucţiunea următoare. 42

43 PREFETCHING PREFETCHING: Overlapping the EXECUTE phase of the current instruction with the FETCH phase of the next instruction. 43

44 PREFETCHING Parallelism in a time sense; Memory bus widening technique (1): spatial parallelism; Simple and efficient technique; Frequently used in designing CU; Can be refined, by considering more steps of an Instruction Cycle; Increases performance; Two units working in parallel (MM & CPU); Cheapest technique; The other two techniques are more expensive, as they require new resources (Cache Memory, widened data bus). 44

45 Organisation of the CPU Peripheral Devices Communication 45

46 I/O Units Data Flux de flow date Alternative Data Flow Flux de date alternativ CPU = ALU + CU Instructions Flux de instructiuni Flow Control Comenzi sau Line linii de control Status Informatii Line de stare sau linii de stare Unitatea Control de Control Unit (CU) (UC) Date de Input Data intrare si & programe Programs Unitatea Input de Intrare Unit (IU) (UI) Unitatea Arithmetic Logico- Logic Aritmeticã Unit (ALU) Date Unitatea Output de Iesire Unit (OU) (UO) Instructiuni Instructions Date de iesire Output Data sau rezultate & Results DMA Unitatea Memory de Memorie Unit (MU) (UM) DMA 46

47 Peripheral Devices A powerful computer: hundreds of peripheral devices connected through Input/Output (I/O) Units; I/O Unit: controls one or several peripheral devices; comunicates with the system bus. Examples of peripheral devices: keyboard; mouse; joystick; monitor; printer; scanner; components of the SM (hard-disk, floppy-disk, CD, DVD, etc). 47

48 Peripheral Devices Differences in terms of: form and function: by using different media, different principles of operation and necessitating different sets of control information; operation speed. Represent one of the main system resources; May be shared among multiple users; May be simultaneously needed by several processes; A rule of serving has to be established; The peripheral devices + I/O units = the I/O architecture of the computer system. 48

49 Peripheral Devices Any peripheral device has the following structure: Control signals: determine the function that the device will perform; Status signals: indicate the state of the device; Data: are in the form of a set of bits to be sent to or received from the I/O unit; Control Logic: controls the device operation in accordance with the commands issued by the I/O unit and the type of peripheral device; Transducer: converts data from the electrical to other forms of energy; Buffer: has to be associated with the Transducer to temporarily hold data being transferred between I/O units and the external environment. 49

50 Structure of a Peripheral Device 50

51 I/O Units Are connected to the System Bus; Control the peripheral devices; Set of mechanical connectors that wire peripheral devices; Include the logic for performing a communication function between the peripheral device and the system bus; They must: communicate with CPU and MM and one or multiple peripheral devices; ensure the communication between CPU and peripheral devices; ensure data buffering; ensure the control and synchronization; detect the erros. 51

52 I/O Units Address lines Data lines System Bus Control lines I/O unit (P1) (P2) (P3).. (Pn) Lines to peripheral devices 52

53 Data transfer CPU-Peripheral Device via I/O Unit The data transfer between a peripheral device and CPU is performed as follows: 1) CPU interrogates the I/O unit to check the status of the device; 2) The I/O unit returns the device status to CPU; 3) If the device is operational and ready to transmit, CPU requests the transfer of data item by means of a command sent to the I/O unit; 4) The I/O unit obtains the data item from the device; 5) The data item is transferred from the I/O unit to the CPU. 53

54 General Structure of an I/O Unit Linii Data de date Bus CPU Registre Data Registers de date Registre State/Control de Stare/Control Registers Linii Address de Adresa Bus Logica I/O Logic I/O Linii de Control Control Bus Interfata Ext. device cu interface disp. periferic Interfata Ext. device cu disp. interface periferic Date Data Status Stare Control Date Data Status Stare Peripheral Disp. periferice Devices Control Control 54

55 General Structure of an I/O Unit Each I/O unit must have a unique address => I/O Unit address; If an I/O unit allows connection of several devices, then each device has its own address; Data transfers to and from the I/O units are buffered in one or several data registers => local memory of the I/O unit; Status Registers: provide current status information; may function also as a control register to accept detailed control information from the CPU. CPU uses control lines to transmit commands to the I/O units. 55

56 I/O Unit - CPU communication I/O unit and the CPU communication assumes the following actions: Command decoding: I/O unit accepts commands from the CPU, signals that are sent via the Control bus; Exchange of data: carried out over the Data bus; Status reporting: because peripherals are slow it is important to know their status through the I/O unit. Common status signals are BUSY, READY, etc; Address recognition: each device must have a unique address so that I/O unit must recognize the unique address for each peripheral it controls. 56

57 CPU - Peripheral Devices Transfer Data transfers: CPU peripheral device; 3 situations: 1) Data transfer under program control or programmed I/O; 2) Interrupt initiated data transfer (interrupt driven I/O); 3) Direct Memory Access (DMA) transfer. 57

58 Program-controlled transfers Are the result of I/O instructions written in the computer program which is in progress; Each transfer is initiated by an instruction in the program; Each transfer is performed: between a register of CPU (for instance, the Accumulator) and the peripheral device, or between a register of CPU and the memory. Requires constant monitoring of the peripheral device by the CPU to identify when a transfer can again be carried out; CPU stays in a program loop until the I/O unit indicates that it is ready; It is a time consuming process since it keeps the CPU busy needlessly. 58

59 Interrupt-driven I/O Uses the interrupt facility of the CPU; When running a program: 1) an I/O instruction informs the I/O unit to issue an Interrupt Request when the peripheral device becomes available; 2) CPU switches to another program; 3) I/O unit watches the peripheral device; 4) When the device is ready for data transfer, it generates an interrupt request to the CPU; 5) CPU stops momentarily the task it is doing and branches to a service routine to process the data transfer; 6) CPU returns to the task it was performing. 59

60 DMA (Direct Memory Access) Uses a dedicated I/O unit, called DMA Controller, which transfers data into or from the Memory Unit through the memory bus. 1) CPU initiates this type of transfer by: supplying the starting memory address; supplying the number of words to be transferred. 2) CPU frees the bus and the DMA controller takes control of the bus and realizes the transfer; 3) After that it issues an interrupt request to CPU to indicate that the transfer ended; 4) The DMA controller frees the bus and CPU regains control of the bus. 60

61 I/O Processors (channels) Peripheral device < speed than CPU => 61

62 I/O Processors (channels) Peripheral device < speed than CPU => I/O operations are time consuming => 62

63 I/O Processors (channels) Peripheral device < speed than CPU => I/O operations are time consuming => CPU productivity decreases. (according von Neumann) 63

64 I/O Processors (channels) Peripheral device < speed than CPU => I/O operations are time consuming => CPU productivity decreases. (according von Neumann) In order to increase productivity: 64

65 I/O Processors (channels) Peripheral device < speed than CPU => I/O operations are time consuming => CPU productivity decreases. (according von Neumann) In order to increase productivity: CPU activity I/O Unit activity The I/O units were transformed from simple controllers into I/O processors or I/O channels. 65

66 I/O Processors (channels) According to IBM technology, IOP is called channel; Main function: controlling the I/O transfer; IOP is controlled by the CPU: CPU directs the I/O processor to execute an I/O program that is placed in memory; IOP fetches and executes these instructions without CPU s intervention => IOP executes independently the IO program; CPU continues its main task, that of making computations. CPU is released of manipulating a slow I/O operation; At transfer end IOP informs CPU; I/O processor can control a large set of I/O devices with minimal CPU involvement. 66

67 General Structure of a Digital Computer (+IOP) I/O Processor Main Memory I/O Processor I/O Processor Secondary Memory 67

68 Digital Computer Operation Today: the transfer is performed through DMA (Direct Memory Access), as follows: Control Unit (CU) Input Data & Programs Input Unit (IU) DMA Output Unit (OU) Output Data & Results Memory Uniy (MU) 68

69 I/O Processors (channels) There are two types of I/O processors: Selector; Multiplexer. 69

70 I/O Processors (channels) Selector channel: controls multiple high-speed devices; At any time is dedicated to the transfer of data with a single I/O device; The moment it is selected, the I/O device remains connected until the end of the I/O operation; => the I/O selector channel selects a single device and caries out the data transfer with this device only. 70

71 I/O Processors (channels) Multiplexer channel: can handle I/O operations with multiple low speed devices and medium speed devices at the same time. It is based on time slicing principle: multiple I/O devices transfer data sequentially through the same channel. Depending on the I/O devices speed of operation the following two types of organizing the transfers can be identified: byte multiplexer: - for a time slice, only a byte ( word ) is transferred; - it is applied in case of very slow peripheral devices. block multiplexer: - for a time slice a block of bytes (words ) is transferred; - it is applied in case of faster peripheral devices. 71

72 I/O Processors (channels) An IOP can handle one ore more I/O devices; These are connected to IOP through an I/O controller, consisting of: logical interface (IF) toward IOP; device controller (K) toward device. I/O processor IF Logical Interface K Device Controller Peripheral Device The logical interface is manipulating digital information, whereas the device controller is manipulating signals specific to the physical nature of the peripheral device. 72

73 I/O Architecture Mag. I/O IOP Selector Control Stare Mag. Memorie CPU Control Stare IOP Multiplexor IF 1 K 1 DP 11 DP 1R IF IF 1 n K n K 1 Date/ Adrese MP Date/ Adrese IF m K m DP m1 DP ms DP n1 DP 11 Dispozitive periferice medii si lente DP nq DP 1P Dispozitive periferice rapide 73